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IFTLE 4 Are We All Suffering From 3D Stress ?

According to Geert Van der Plas of IMEC ”..TSVs, die thinning, bonding and (flip-chip) packaging result in a 3D chip-stack with built-in stress which can potentially lead to yield, electrical performance and reliability issues”

To address these issues, SEMATECH held a workshop on “Stress Management for 3D ICs” on March 16, 2010 in Albany, NY. Thanks to old friend Larry Smith for sending the pertinent info from this conference to share with you.


Xiaopeng Xu detailed the use of the Synopsis TCAD software to analyze 3-D structures [ link ]. The different modules in TCAD can not only be used to extract 3-D R,C & L but can also predict interconnect stress distributions from multiple stress sources and reportedly detect stress hot spots that are susceptible to debonding, voiding and cracking.

The presence of TSV appears to create more impact on the mobility of p doped Si than n doped as shown below.

Their data shows that larger TSV diameter leads to larger mobility change in Si due to larger deformation and shear stress as shown below.

Also of significant interest is the data which reveals that low-k dielectric with its inherent lower modulus results in less resistance to copper extrusion.
On Mar 09, 2010 Synopsys, and IMEC announced they have entered into a collaboration to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs).


Kamal Karimanal of Ansys looked at techniques applicable to TSV based 3D packaging. AN example is the use of ANSYS Icepak Software to examine metal distribution and calculate temperature variations across the stack.


Riko Radojcic of Qualcomm pointed out that stress management was important because for 3-D it becomes the sum of the on chip strains + the normal chip package interactions and the new 3-D TSV issues such as:

- interaction of (big) Cu TSV and surrounding devices
- µ-Bump issues with Tier 1 and Tier 2 die
- thin Si : Enhanced BEOL-FEOL + Si-package CTE Mismatch
- backside RDL : new CTE Mismatch challenges
- die to die : stress re-distribution among the stacked die
- die alignment : stress concentration among stacked die

He points out that we currently manage this on 2D chips through design rules and that it is these design rules that must be extended to 3-D stacks such as:

- Keep Out Zone Rules
- No change to device characteristics vs. ‘normal 2D Si (all devices)
- Die Stacking & Alignment Rules
- No incremental CPI effects for T1-T2 and T1-Package Interactions
- PAD and CUP Rules for µ-Bumps
- No CPI or Performance impact on either T1 or T2

Radojcic proposes an EDA solution “ that bridges package and Si design and simulation environments without forcing re-tooling from incumbent solution in either domain”


Geert Van der Plas of IMEC indicated that insight into 3-D IC thermo-mechanical behavior requires analysis of test structures such as those shown below.

For all the latest in 3DIC and advanced packaging stay linked to Insights From the Leading Edge, IFTLEâ??¦â??¦

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