IFTLE 3 ……on Finding the Beef & Finally Addressing 3-D IC
To be frank with you (which you know I always try to be) I wasn’t a fan of the press releases by ALLVIA back in the winter and the resulting news stories derived from them [ for instance see: “ALLVIA offers New TSV Reliability Data”, Semi Int 01/25/2010 ].
My “beef” was “Where’s the beef ?”
No indication of what was built, no indication of what tests were run and no indication as to the results of said reliability tests. Interested parties were told to contact ALLVIA. My conclusion was “Nice eye catching headline – but WHERE”S THE BEEF”, in any of the storiess that were based on this press release.
In mid March Allvia offered a webcast entitled “Silicon Interposers with TSVs and Thin-Film Capacitors”. Knowing Sergey and his team, I was willing to give them “the benefit of the doubt” .
This blog was then entered into que at PFTLE, but as we all know ,factors beyond my control delayed its publication until now.
So after that long introduction, lets take a look at what ALLVIA has to offer because it is still pertinent and interesting information for all of us that are interested in 3D IC.
As you may know, ALLVIA is currently housed in Sunnyvale where they have 6000 sq ft of clean room. This past winter they announced the acquisition of an additional 60,000 sq ft of clean room at a manufacturing facility in Portland OR. Their capability summary is detailed below. With a TSV sweet spot of 30 – 150 um they are obviously focusing on vias last-backside and interposers.
They have examined thermal cycling of their TSV . Some of the results are shared below.
ALLVIA is also offering thin film capacitor technology integrated onto their interposers.
Reliability results for Si interposers mounted on BT substrates are shown below.
Novellus – Finally Putting 3D IC in their sights
When looking at the ECD (electrochemical deposition) landscape in relation to 3-D IC, the names Semitool, Nexx and Ebarra come to mind. They are attending 3-D conferences, making 3-D presentations and are engaged with customers on 3-D scaleups. When you look at this list one big copper plating player is noted by its absence – Novellus. Their equipment offerings include PVD and CVD Cu and W solutions and well as Cu plating technology. Their ECD copper tool “Sabreâ??¢” was one of the first on the market to meet the demands of dual damascene copper 12+ years ago.
I’m now glad to tell you that this lack of focus on 3-D IC seems to have been reversed in the last several months. Last July Novellus and the University at Albany’s College of Nanoscale Science and Engineering (CNSE) announced that they had formed a $20M partnership to conduct next-generation R&D into sub-22nm semiconductor manufacturing technology. As part of the agreement, Novellus will install three advanced thin film deposition tools-a VECTOR® plasma-enhanced chemical vapor deposition system (PECVD), a SABRE® copper electrochemical deposition system, and an ALTUS® tungsten chemical vapor deposition (CVD-W) system-at CNSE complex. It was announced that a team of Novellus researchers, located at CNSE, will be conducting leading-edge research into among other things copper fill for interconnects and copper TSV fill for 3-D IC.
On March 9th Novellus announced an advanced copper barrier-seed physical vapor deposition (PVD) process for the TSV market. The process uses Novellus’ INOVA platform to produce highly conformal copper seed films that are reportedly four times thinner than conventional PVD seed approaches. Novellus claims the process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent electroplating step. The ionized PVD process chamber causes a larger fraction of the sputtered film to land on the sidewall, which in turn results in a more conformal deposition. Novellus’ process can reportedly achieve void-free feature fill in a 60 micron deep, 10:1 aspect ratio TSV feature with vertical sidewalls using a 2000 angstrom thick copper seed layer. The conventional PVD approach requires an 8000 angstrom thick seed layer to achieve the same result. The 4X thinner TSV seed layer results in a substantial increase to system throughput and reduces the cost-of-consumables by greater than 50 percent as compared to conventional PVD approaches.
This was followed up a week later with an announced joint development program with the IBM “to design a manufacturing-worthy, copper-based, three dimensional (3- D) semiconductor Through-Silicon Via (TSV) process using Novellus’ SABRE(R) copper electroplating and VECTOR(R) plasma-enhanced chemical vapor deposition (PECVD) systems.”
Novellus has reportedly developed a unique, high performance SABRE ElectrofillTM TSV process that uses Novellus hardware and chemistries to achieve void-free fill with minimal copper overburden. Copper overburden is reportedly reduced by 75 percent, allowing conventional chemical-mechanical polishing (CMP) to be used instead of custom polishing slurries. They also claim that the SABRE TSV chemistries have faster plating times, resulting in higher throughputs.
To address the requirement of lower temperature dielectrics, Novellus’ VECTOR platform enables the deposition of stable dielectric films at temperatures <>