Part of the  

Solid State Technology

  Network

About  |  Contact

IFTLE 387 Broadcom Looks to Advanced Packaging; Rumors from ECTC San Diego

June 19th, 2018

By Dr. Phil Garrou, Contributing Editor

Boon Chye Ooi , Sr VP of Operations for Broadcom spoke at the IEEE ECTC luncheon addressing “Packaging advancements to enable artificial intelligence (AI), autonomous cars and wearables in the near future: cost and implications to supply chains.”

Broadcom’s Sam Karikalan, ECTC General Chair introduces Boon Chye Ooi , Sr VP of Operations for Broadcom

Ooi leads the global operations organization which is responsible for worldwide manufacturing including foundry and package engineering, outsourcing, procurement and logistics, planning and quality programs. Ooi indicated that he saw packaging as having played a vital role in enabling semiconductors to penetrate new application frontiers such as artificial intelligence (AI), autonomous cars and wearables, but for their ubiquitous deployment, the packaging community must make these technologies cost competitive and multi sourced.

He had 3 questions for the supply chain:

  1. Is the OSAT/Foundry willing to invest fab like yield tools?
  2. Will there be sufficient capacity and reliability of supply?
  3. How will cost excursions and miss-processing be handled by the infrastructure?

His call to action for the supply chain of 2022 included the following points:

  • Upgrade assembly yield management to Fab level
  • Develop u-bump probe and test technologies for improved yield
  • Develop substrates for low loss mm wave channels on large packages
  • Develop low cost thermal solutions to reduce system cost
  • Develop multiple suppliers for silicon content, packaging raw material, substrate and assembly

Specific technical challenges included the following:

  Desired Goal Issues
Data rate 112 Gbps · channel insertion loss and return loss

· crosstalk

· power integrity

Package Body size > 90 x 90mm · package warpage

· board level reliability

· socket cost and performance penalty

2.5D Integration More and larger dies · interposer reticle size

· assembly challenges

· more memory bandwidth

u-bump pitch < 30um · assembly challenges

· routing challenges

 

Power dissipation >500W · thermal interface materials

· heatsink solutions

 

Rumors from San Diego

With 1750 attendees present there were sure to be numerous rumors making the rounds at ECTC. In time some will clearly turn out to be true and some will not, but all of them are certainly interesting enough to consider.

One rumor I can confirm is that Rao Tummala, unquestioned “Father of Microelectronics Packaging”  will be retiring imminently. Tummala, now in his mid 70’s, has informed Ga Tech and his PRC that a successor should be located. He will be helping his replacement for a few years to ensure a smooth transition but he is looking forward to relaxing, spending more family time and playing more golf. It certainly will be interesting to see who Ga Tech finds to fill his shoes.

As I have detailed several times in IFTLE, BT (before Tummala) packaging was an after thought carried out by failed front end engineers. In 1989 Tummala, while still at IBM, joined Gene Rymaszewski editing the first Microelectronic Packaging Handbook categorizing this technology for the first time. In 1993 Tummala left IBM to set up an NSF PRC (packaging research enter) at Georgia Tech to explore and develop packaging concepts and, just as importantly, educate highly-interdisciplinary students in this concept. This NSF funding was supplemented by more than 50 U.S. companies and the State of Georgia. 20 new faculty were recruited with expertise in every electronics area. The 1st of a kind cleanroom pilot line for package, assembly and reliability was built at a cost of $47M. In the intervening years more than 400 PhD, 470 MS and 340 BS engineers all specializing in packaging have graduated from this program and populated the electronics companies around the world. In 1997 the Packaging handbook was rewritten in 3 volumes and more than 2000 pages. The chapter author list is a who’s who in the field of packaging. I am proud to have been part of that endeavor. Below is a photo we took in Slovenia together 21 years ago in 1997.

In 2001, Rao produced what I consider the first undergrad / grad packaging text “Fundamentals of Microsystem Packaging,” which has been used to teach electronics packaging in many of our universities. He and I co-wrote the chapter on wafer level packaging, a new concept at that time. My point in reciting all this is to simply backup my statement that these will be very large shoes to fill. It will be interesting to see who will fill them.

For all the latest in Advanced Packaging, stay linked to IFTLE…

 

IFTLE 386 IEEE EPS Awards at 2018 ECTC

June 13th, 2018

By Dr. Phil Garrou, Contributing Editor

Memorial Day in the US means the start of the IEEE ECTC meeting, which is run by the IEEE EPS society (Electronic Packaging Society). This years 68th meeting was in San Diego and broke all records with an attendance of > 1750. There were 369 presentations in 36 oral sessions (6 in parallel) with authors from 28 countries.

The exhibition has been at capacity for several years with 106 exhibitors and reportedly 40+ on a wait list. IFTLE concludes that eventually this meeting must move to convention centers because it is becoming too large for hotel spaces available.

In this first blog on 2018 ECTC we will look at the EPS 2018 award winners.

The IEEE EPS Field Award

As we have discussed in the past the major packaging award in the world is the EPS “Field Award” meaning the top award in the “field.” This year’s winner is Bill Chen from ASE. The photo below shows IEEE President Jose Moura giving the award to Bill.

Dr. Bill Chen accepts EPS Field Award

Bill received his engineering education at University of London (B.Sc), Brown University (M.Sc) and Cornell University (PhD).  He joined IBM Corporation at Endicott New York in 1963. At  IBM  he  worked  in  a  broad  range  of  IBM microelectronic packaging products. He received IBM Division President Award for his leadership and innovation in Predictive Modelling on IBM products.    He was elected to the IBM Academy of Technology for his contributions to IBM Products and Packaging Technologies. He retired from IBM in 1997.  He joined the Institute of Materials Research and Engineering (IMRE) in Singapore, as Director of the Institute till 2001 when he joined ASE Group, where he holds the position of ASE Fellow and Senior Technical Advisor with responsibilities for guidance to technology strategic directions for ASE Group.

He is Senior Past President of the IEEE/CPMT Society. He is the Co-Chair of the ITRS Assembly and Packaging Roadmap Technical Working Group. He is a Fellow of IEEE and Fellow of ASME.  He has served as an Associate Editor  of ASME Journal of Electronic Packaging, and IEEE/CPMT Transactions.

EPS Electronics Manufacturing Technology Award

The 2018 IEEE EPS Electronics Manufacturing Technology Award was given to Douglas Yu of TSMC for “contributions to the development and high volume manufacturing of interposers and wafer level fan out packaging”. Dr. Yu received his B.S. degree in Physics and M.S. degree in Materials Science and Engineering both from National Tsing Hua University, and his Ph.D. in Materials Engineering from Georgia Institute of Technology. Dr. Yu was appointed TSMC’s Vice President in November 2016. Dr. Yu joined TSMC in 1994. He was previously Senior Director of the Integrated Interconnect & Packaging Division, where he led the development of interconnect technology for integrated circuits. Below we see Dr. Yu (L) accepting his award from EPS President Avi Bar Cohen.

Doug Yu receives Electronic Manuf Award

The IEEE EPS Outstanding Sustained Technical Achievement Award went to Professor Pradeep Lall of Auburn for “outstanding sustained contributions to the design reliability and prognostics for harsh environment electronic systems”.

The IEEE EPS Exception Technical Achievement Award went to three practitioners in the 2.5/3D technical space: Prof Mohannad Bakir of Georgia Tech; Prof Kuan-Neng Chen of National Chiao Tung Univ in Taiwan and Dr Katsuyuki Sukama of IBM.

All the awards were for “contributions to 2.5 and 3D IC heterogeneous integration, with focus on interconnect technologies.”

The IEEE EPS David Feldman Outstanding Contribution award went to EPS past president Jean Trewhella for “20 years of leadership consistently driving change collaboration and engagement in EPS and ECTC, including driving our society name change, sponsoring the heterogenous Integration roadmap and establishing the ECTC student reception.”

Newly elected Fellows included:

Kuan-Neng Chen – National Chiao Tung Univ , Taiwan
Klaus-Dieter Lang – Fraunhoffer IZM, Germany
Jinmin Qu – Northwestern Univ
Guo-Quan Lu – VPI
Saibal Mukhopadhyay – Georgia Tech
Stefan Grivet-Talocia – Politecnico de Turino, Italy

…and while we are talking awards.

Corning Presents First Annual ‘Corning Leadership in Glass Award’ at ECTC 2018

At the ECTC, Corning presented the first annual “Corning Leadership in Glass Award” to Proff Rao Tummala and his group at Ga Tech. The award recognized the technical paper “Design and Demonstration of Highly Miniaturized, Low Cost Panel-Level Glass Package for MEMS Sensors,” submitted by Georgia Tech at ECTC 2017 that best demonstrated the viability of glass for semiconductor packaging applications.

“We’re pleased to accept this very special award from Corning,” said Tummala. “We have long believed that the properties and fabrication of ultra-thin glass make it the best next generation material of choice for semiconductor and system package integration manufacturing processes after metal-based packaging since 1970s, ceramics since 1980s, organic laminates since 1990s and silicon since 2010. We’re proud that the research we’ve done in glass panel packaging in both chip-first and chip-last architectures, is gaining more and more acceptance.” Because of this special and unique nature of glass packaging, we converted our whole Center to glass packaging for high-bandwidth computing, 5G communications, power, mems and sensors and others.”

Dr. Venky Sundaram, Chintan Buch (student), and Prof. Rao Tummala (left to right) accept the inaugural ‘Corning Leadership in Glass Award’ at ECTC 2018.

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 385 Samsung’s Semiconductor Focused Activities

June 8th, 2018

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at Samsung’s System LSI activities per their recent Investor program. ICs and applications that were highlighted are shown below.

Chronological advances in the Exnos microprocessor which are now being manufactured at 10nm are shown below.

Samsung has maintained a position as supplier of mobile processors, image sensors and display driver ICs. Looking into the future Samsung sees the main application drivers as:

Samsung System LSI is a provider of integrated total solution for mobile. They feel that innovations in semiconductor technologies will be the key driver in various new applications that adopts AI/Deep Learning, 5G networking, and smart mobility. Samsung LSI is now on the path to be a key player for 5G and autonomous mobility, and is investing for future device intelligence.

This will require a lot of advanced packaging!

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 384 Sony Refocuses on Smartphones for 5G

May 29th, 2018

By Dr. Phil Garrou, Contributing Editor

Sony had some interesting things to say about their semiconductor and imaging technology businesses at their recent investor relations day May 22nd in Tokyo. As the industry moves forward to 5G, they seek to provide both hardware solutions and content services. Probably most startling to those in attendance appeared to be their announcement of a major focus on their mobile smartphone business.

Shigeki Ishizuka, Exec VP of Imaging products and mobile communications business discussed their theme of “light to display” as shown below. Imaging products and solutions is currently a 660B Yen business for Sony.

Their key applications for real time broadcasting include not only sporting events and concerts but also business to business communications, the education market which they call “active learning solutions” and medical room imaging solutions.

The medical business is described below and consists of both surgical imaging and life sciences.

Their newly developed 3D surgical microscope allows doctors to operate without looking into the eye lenses of the microscope and the image can be shared real time with the whole operating team.

In the mobile communications segment Sony smartphone (Xperia) unit sales have decreasing since 2014 (see below). They will now focus on 5G phone solutions to revive their business position in that segment.

They will be seeking to advance smartphone competitiveness vs the industry leaders by bringing all their internal technology and their external partnerships to bear. They expressed a need to especially improve the design.

Post presentations, most of the questions focused on this announcement of increased focus on the mobile segment. When questioned about whether 5G mobile was an area that they HAD to be in, Sony answered that the technology hurdle for 5G is “quite high” including antenna technology “…. multi antenna array for beam focusing and switching has never happened before….high technology solutions are needed…its not like you can purchase an LSI chip and write some software and develop a solution…we will have to acquire these solutions and mature them” IFTLE assumes this answer was meant to mean that this is not likely to be a commodity product and would require the technical expertise that only companies of Sony’s stature could deliver.

When asked whether it was logical to focus on smartphones where Sony now has less than 1% market share they answered that “…with respect to smartphones the share is low-right- that’s a pity…we don’t have much product offering and product capability is very low….” The rest of the answer did not clearly explain how they intended to turn this around other than they awould be focusing all their internal technical expertise on solving this problem.

It will be interesting to see if Sony can really become competitive with the likes of Samsung and Apple in the future 5G arena.

For all the latest in advanced packaging, stay linked to IFTLE…

IFTLE 383 Global Foundries “Adv Packaging Trends in the Foundry Space”

May 16th, 2018

By Dr. Phil Garrou, Contributing Editor

At the recent IMAPS Device Packaging Conference outside Phoenix Hamid Eslampour, CMOS BU Product Management, of GlobalFoundries (GF) discussed Advanced Packaging in the Foundry Space.

Eslampour indicated that todays networking, machine learning, and other high-end computing applications have created the need for architectures that allow for processing of massive amount of data located in nearby memory through communication with the CPU/ GPU with low latency, parallel processing, and high data rate.

To enable these solutions, advanced Si nodes with High-Speed-SERDES (HSS), enhanced HBM-PHY, and highly integrated package technologies are required. The packaging solutions they see providing the level of integration required include MCM, 2.5D, and 3D.

The challenge for foundries such as GF is to enable these solutions through co-design with the customer within a business model that provides the package design, technology integration, and OSAT manufacturing processes required.

High bandwidth and high performance computing technologies for silicon and packaging are shown below. Such high performance devices will require < 40um pitch copper pillar bumping and fine line interconnect (< 10/10 L/S).

fig 1-2

14nm designs are in customer development with 7nm and beyond designs in pathfinding.

fig 2-2

Current GF interposer capabilities are shown below and include 10um TSV on 40um pitch, up to 3 metal layers of 0.8um L/S interconnect:

iftle

 

GF has the following supply chain in place:

fig 3

Higher bandwidth trends drive higher number of HBM stacks, larger silicon interposers and larger power dissipation issues.

For all the latest on Advanced packaging, stay linked to IFTLE…

IFTLE 382 Semiconductor Activity in China – Betting on AI

May 9th, 2018

By Dr. Phil Garrou, Contributing Editor

China is by far the largest consumer of semiconductors reportedly accounting for 45 percent of the worldwide demand for chips, used both in China and for exports. More than 90 percent of its consumption relies on imported ICs.

At the end of 2016 IC Insights reported that China was responsible for ~ 11% of the worlds wafer capacity.

fig 1

China has been working to reduce its dependence on technology imports, including computer chips for several years. In March, it was reported that state-backed China Integrated Circuit Industry Investment Fund Co. is in talks with government agencies to raise at least $24B to build up China’s domestic semiconductor industry. Recently, the Wall Street Journal reported that China is poised to announce a new fund of ~ $47B for development of its semiconductor industry and close the technology gap with the U.S. and other rivals.[link]

While the existence of such a fund has been rumored for months, the size of the fund has been hard to pin down. A few weeks ago, Reuters reported that the fund would be $19B, while Bloomberg reported $31.5B two months ago. The exact number appears to be under consideration among the Chinese leadership, and tied to the increasingly tense trade negotiations with the United States. If $47B is indeed the correct number, it would be identical in size to the $47 billion fund that was financed by Tsinghua University, to spur the development of an indigenous semiconductor industry back in 2015.

While China is playing catchup in many semiconductor areas, it has also been placing its bets on new areas like 5G wireless and AI (artificial intelligence) chips. [link].

China releases its first cloud AI chip

Beijing artificial intelligence (AI) chip maker Cambricon Technologies Corp Ltd has just announced two new products, a cloud-based smart chip Cambricon MLU100 and a new version of its AI processor, Cambricon 1M, in Shanghai on May 3rd.

The cloud chip MLU100, developed by China’s Cambricon Technology, is China’s first cloud artificial intelligence (AI) chip developed to have big data processing ability, for image and voice searching [link].

fig 2

Cambricon 1M is the company’s third generation AI chip (gen 1 was in 2015) for “edge devices.” An edge device is a device which provides an entry point into enterprise or service provider networks such as routers, routing switches, integrated access devices (IADs), multiplexers, and WAN (wide area network) access devices. Using TSMC 7nm technology, the AI chip can be used in smartphones, smart speakers, cameras, and smart driving.

Cambricon MLU100 supports cloud-based machine learning, including vision, audio and natural language processing. It can process under complex scenarios, such as “…with huge amounts of data, multi-tasks, multi-modality and low latency.” This processor reportedly can provide 166 TFLOPS in high-performance mode with energy consumption of no more than 110 watts at peak. The MLU100 is built with TSMC 16nm technology.

Lenovo has announced that their ThinkSystem SR650 server is based on the MLU100. Products built around MLU100 were also announced by Sugon and iFlytek who also announced collaboration with Cambricon [link]

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFTLE 381 TSMC WOW

May 4th, 2018

By Dr. Phil Garrou, Contributing Editor

TSMC Introduces WoW Technology

At the TSMC Technology Symposium in Santa Clara, the company discussed their new Wafer-on-Wafer (WOW) silicon wafer stacking technology for the 7 and 5nm nodes. The “new” technology connects chips on two silicon wafers reportedly using 10um TSV. Those of us who have been following 3DIC for over a decade recognize this as W2W 3DIC. Even the name isn’t new, since Fujitsu introduced their version of WoW technology in 2010 which we discussed way back in in IFTLE 181.

TSMC first teased us with this potential technology back in 2014 at the IEEE IEDM.

TSMC 1

The TSMC technology stacks and interconnects die while still part of the full silicon wafers vs their previous 2.5D technology CoWoS that uses silicon interposers. The advantage is obviously that this tech connects all die on two wafers in one process step. In terms of performance, direct 3D stacking has always been known as the highest performance lowest latency solution.
As we have known for a decade at least, there are several issues with W2W technology: (1) yield – bad die on wafer 1 will be connected to good die on wafer 2 resulting in a bad stack. This precludes this technology from being a viable solution for silicon that doesn’t already offer high wafer yields. Ideally, TSMC reports that chip yields should be 90% or higher to use TSMC’s Wafer-on-Wafer technology. (2) quite obviously this technology is most relevant for low-power silicon, where heat is less of an issue and (3) Also importantly, readers of IFTLE know that this solution works best for chips that are identical like memory stacking, but not for ships of different sizes and different I/O configurations which would require redistribution (RDL) before alignment and stacking is possible, thus increasing cost.

So far, TSMC has reportedly achieved “2-layer stacks, in which two silicon layers that are mirror images of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.”

Since TSMC currently manufactures graphics cards for both AMD and Nvidia and there are some predicting that we will see stacked GPUs from the WoW technology. “There won’t be latency problems between the connected GPUs as the wafer has the ability to let the GPUs communicate quickly, meaning we could see dual-GPU graphics cards based on current GPUs like the Polaris and Pascal GPUs from AMD and NVIDIA, respectively.” [link]

Certainly they wouldn’t be hyping the technology if there weren’t real customers urging them to move forward with it. It will be interesting to see if they give a more complete description of WoW at the IEEE ECTC in a few weeks. If so be sure that IFTLE will get you the details.

What about designing these complicated structures ??

Cadence Teams with TSMC for full WoW Design Flow

Cadence has announced that its full suite of Cadence digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology. [link]

Cadence announced a new WoW reference flow to complement their other TSMC integration solutions ( InFO and CoWoS). They described the following design flows, tools and methodologies that will enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process as follows:

  • Innovus™ Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
  • Quantus™ Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
  • Voltus™ IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
  • Tempus™ Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
  • Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
  • Virtuoso® Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
  • OrbitIO™ interconnect designer: Provides interface connectivity,  device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
  • Sigrity™ PowerSI® 3D-EM Extraction Option: Offers electrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
  • Sigrity PowerDC™ technology: Thermal analysis solution with interposer and die analysis capabilities that allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
  • Sigrity XcitePI™ Extraction:  Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
  • Sigrity SystemSI™ technology: Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation

For all the latest on Advanced Packaging, stay linked to IFTLE…

IFLE 380 IMAPS Device Packaging Conf Part 3: Yole Updates FO-WLP

April 25th, 2018

By Dr. Phil Garrou, Contributing Editor

This week, let’s take a look at the latest Yole update on Fan out Packaging by Jerome Azemar that was presented at the IMAPS 2018 Device Packaging Conference.

As we have discussed before, fan out packaging can be embedded in laminate or embedded in mold cmpd (EMC) . Chips can be placed face up or down with various options for interconnections.

yole 1-2

Their look inside a smartphone gives an interesting perspective on where fan out packages are being used and where they can be used.

yole 2-2

Yole sees automotive radars as an interesting market for fan out solutions

- fan out used in Rf and radar applications

- since 2015 Infineon has shipped > 10MM Radar IC in eWLB packages

Yole reports that technical challenges still exist for fan out as shown below:

yole 3-2

 

They see high density fan out (like TSMCs InFO) fan out being in competition in the future for HPC (high performance computing) and AI (artificial intelligence) applications with silicon 2.5D solutions.

While panel production would certainly reduce costs (more units per operation) such technology is not ready and will have large capital equipment costs. They see production being mainly on wafer through 2022.

fowlp iftle 380

 

CMOS Image Sensor Market

IC Insights Optoelectronic, Sensor, and Discrete report concludes that the CMOS Image sensor market is not approx. the same size and growth rate as the LED business [link]. An interesting comparison…

CIS market

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 379 IMAPS DPC 2018: Chip to Wafer Hybrid Bonding

April 18th, 2018

By Dr. Phil Garrou, Contributing Editor

IFTLE has extensively discussed the applicability of the Ziptonix technologies (acquired and now owned by Xperi): ZiBond (oxide-oxide bonding) and DBI (copper-oxide to copper-oxide “hybrid bonding”) [for example see IFTLE 303, “Sony Introduces Ziptronix DBI Technology in Samsung Galaxy S7” and refs therein]

These technologies have now been commercialized in areas such as COS image sensors, Rf and MEMS. These are all wafer to wafer bonding applications. As of yet, a die-to-wafer process has not been developed for manufacturing, imposing W2W limitations such as the requirement that die sizes match and yields are high.

experi 2-2

At the recent IMAPS Device Pkging Conf in March, Wang of Xperi discussed the “Design, characterization and testing of large area and high density 3D direct bond interconnect which discussed development of such a die to wafer technology.

DBI’s key attribute is the formation of electrical interconnects at low temperatures and pressures as shown below:

experi 3-2

The technology requires highly polished (CMP’ed) surfaces (less than 1nm deviation across wafer surface topology is typical) .

The Xperi goal was expressed as developing a process for HBM memory stacks by stacking 4 double sided DBI memory die with the following attributes:

- throughput – 3000uph                       – no underfill

- no solder                                             – stack consecutively then batch anneal

For die to wafer bonding they followed he following process sequence:

experi 4

The design that was evaluated for a HBM stack contained 10um pads on 40um pitch.

D2W vs W2W electrical test for their test vehicle is shown below:

experi 5

Die to wafer reliability for a 31K daisy chain are shown below:

experi 6

It will be interesting to see whether this data will extrapolate to the fabrication of real HBM die stack in the future.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 378 IBM/DARPA ICECool Program Summary; Apple to Inc use of Apple Chips

April 10th, 2018

By Dr. Phil Garrou, Contributing Editor

The March Issue of Electronic Cooling magazine contains a great summary article on the IBM effort in the DARPA ICECool Program [link]. I recommend reading the full article which I will summarize here.

When today’s standard cooling technology, air cooling with fans, does not meet the required needs, advanced water cooling approaches are examined. Traditional water cooling approaches replace the heat sink with a cold plate that provides more efficient heat transfer. But, because of its electrical conductivity, water cooling requires isolation measures to protect the chip, and requires large channels to cool large high-power die at reasonable pressure drops.

As part of the DARPA ICECool program, seeking to develop appropriate cooling technologies for 3D chip stacks, IBM developed a new chip-embedded cooling approach, utilizing a nonconductive fluid, doing away with the need for a barrier between the chip electrical signals and the fluid. This chip-embedded cooling technology pumps a heat-extracting dielectric fluid into ~100μm cooling channels, between the chips at any level of the stack. The coolant removes the heat from the chip by boiling from liquid-phase to vapor-phase. It then re-condenses, dumping the heat to the ambient environment. Since this system doesn’t need a compressor, it can operate at much lower power compared to typical refrigeration systems.

IBM 1

The dielectric coolant is fed in at the center of the die, moves through radially expanding channels, and exits at the edges of the die. This approach (shown below) provides better energy efficiency and maximum critical heat flux with the resulting reduced flow path.

To modify an IBM microprocessor module for embedded cooling the package lid was removed to expose the processor die, a deep reactive ion etch (DRIE) of the processor die was performed to generate the 120 µm deep cooling channels structures in the backside the processor and a glass die was bonded to the etched processor die to create the top wall of the micro-channels and a brass manifold lid, which provides for coolant supply and return, was bonded to the glass manifold die and the organic substrate using an adhesive. The coolant enters the module and passes through 24 inlet orifices to distribute the flow among the corresponding 24 radial expanding channels as shown below.

IBM 2

The figure below compares the performance of the standard air cooled module with the new embedded liquid cooled module. The cores temperature were measured with coolant inlet temperature in both cases at 25 ºC; a dielectric coolant mass flow rate of 9 kg/hr at a pressure drop of ~11 psi. The temp of the air-cooled processor levels off at around 70 ºC as the system fans speed up (~65%) to prevent overheating whereas the liquid cooled system is running at 40 – 45 ºC. At the highest power operation (4.3 GHz) the reduced operating temperature results in over a 10 watt decrease in the power consumed by the microprocessor along with a significant reduction in fan power (15+W) .

IBM 3

Apple to Replace Intel chips in Macintosh Computers

Bloomberg is reporting that Apple, which has used Intel processor chips in its computers since 1995, is planning to use its own chips in Mac computers beginning as early as 2020 (code-named Kalamata), replacing processors from Intel (link).

For all the latest on Advanced Packaging, stay linked to IFTLE…

Next Page »

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.