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IFTLE 375 EVG / IBM Laser Debonding; Samsung Increases Focus on CMOS Image Sensor Mkt

March 20th, 2018

By Dr. Phil Garrou, Contributing Editor

EVG Licenses IBM Laser deBonding Tech

IBM’s Hybrid Laser Release Process has been licensed by EV Group for inclusion in their low-temperature laser debonding equipment (link).

The IBM technology will reportedly help EVG address the industry’s requirements for temporary bonding and debonding, including high throughput, low wafer stress for high yield, and low cost of ownership of the laser equipment, processing and consumables. The EVG offering will encompasses techniques to help protect chips from heat and laser damage, as well as chemical clean technologies for device and carrier wafers.

The IBM technology was first described at the 2010 IEEE ECTC Conf (link)

Post debond cleaning is a topic that is rarely discussed but very significant from a manufacturing standpoint. Following debonding, residual polymer materials are left on the substrate. The residue level is dependent on the ablation condition. Laser fluence and total accumulated number of laser pulses need to be optimized for a given polymer adhesive. After debonding, any residue or remaining polymer adhesive needs to be cleaned prior further processing. The cleaning may be accomplished by several approaches including dry etching or chemical wet etching.



Designed for integration in the company’s benchmark EVG-850DB automated debonding system, EVG’s laser debonding modules incorporate a solid-state laser and optics designed to enable force-free debonding. Featuring both low-temperature debonding and high-temperature-processing stability, EVG’s laser debonding solution is available for a variety of applications including FO-WLP (below), memory stacking, die-partitioning, heterogeneous integration etc.

EVG debonding

Samsung to Challenge Sony on CMOS Image Sensors

Fresh from their overtaking of Intel as the worlds #1 IC Chip producer, ETNews (Korea) reports that Samsung has reportedly now set its sights on Sony and CMOS Image sensors. (link)

Samsung Electronics is reportedly planning to increase its production capacity of image sensors and it has set a goal to become #1 in the image sensor market.

Since 2017, Samsung has reportedly been working to convert its line 11 in Hwasung that was used to produce DRAMs into a line (S4 line) that would be used to produce CMOS image sensors (CIS). Conversion to the S4 line is expected to be completed by end of this year. According to ETNews Korea , when this process is done, Samsung Electronics is going to immediately start the conversion process of its 300mm line 13 in Hwasung, that is used to produce DRAMs, into another line that will be used to produce image sensors. Line 13 line can produce about 100,000 units of DRAMs per month, but because image sensors ae a more complex deposition process, it is expected that production capacity for CIS will be reduced by about 50% after conversion. They further report that Samsung Electronics will have a total production capacity of 120,000 units / mo of CIS after these conversion processes are over.

SONY and Samsung are both commercializing 3D stacked image sensors (sensor + logic + DRAM) that can process 960 frames per second (slo-mo). Samsung Electronics has launched the new ISOCELL Fast 2L3 image sensor for super slow-motion recording (link).

The Samsung ISOCELL Fast 2L3 is a high speed 3 layer 3D stacked CMOS image sensor designed with a 2 Gb LPDDR4 DRAM attached below the analog logic layer. With the integration, the image sensor can temporarily store a larger number of frames taken in high speed quickly onto the sensor’s DRAM layer before sending frames out to the mobile processor and then to the device’s DRAM. This allows the sensor to capture a full-frame snapshot at 1/120 of a second and also to record super-slow motion video at up to 960 frames per second ( 32 times the typical filming speed of 30 fps).


The design is similar to that of Sony who was the first to report integration of DRAM into the 3D CIS stack (see IFTLE 272 “2015 3D ASIP Part 1: Pioneer Awards; Sony 3D stacked CIS; Latest on SPIL Acquisition”)

ETNews reports that the number of customers purchasing Samsung image sensors is currently over 10 as Samsung Electronics is increasing points interactions with major mobile devices and automotive customers.

For all the latest on advanced packaging, stay linked to IFTLE…


IFTLE 374 IMAPS Device Pkging Conf part 1: 3DIncites Award Winners

March 12th, 2018

By Dr. Phil Garrou, Contributing Editor

The 14th Int Conf on Device Pkging was held at its normal site, Ft. McDowell, AZ, last week. I normally show a picture of the general chair of the meeting and I will this time also (below), but I thought it was about time we gave due credit to the IMAPS staff that makes the meeting possible.   Below we see (L to R) Dir of Program Dev, Brian Schieman; Membership Admin, Shelby Moirano and Exec Dir Michael O’Donoghue. Events Mgr Brianne Lamm was back in NC holding down the fort, so to speak.



On Tuesday night, we were all entertained by a local Indian tribe that showed us their various ceremonial dances. Below Chairman Ramm poses with the tribes dancers.

Ramm & the Indians


The most entertaining event of the conference was certainly the 3DInsights awards gala on Wednesday night which included, in addition to the awards ceremony, a barbecue dinner, an awards ceremony quiz and a dress up photo booth.

There were 40 nominees from 26 companies and four research institutes competing for awards in 9 categories. An amazing 40,619 votes were cast online. Winners were:

Device Manufacturer of the Year: Amkor Technology for its acquisition of NANIUM.

Device of the Year: (tie) M-Series ™ Deca Technologies, and OmniVision Technologies. Deca was nominated for their adaptive processing technology combined with planar front side molding. OmniVision was nominated for their Nyxel technology which allows their image sensor to see better and farther under low- and no-light conditions than previous generations.

EDA Supplier of the Year: Mentor, A Siemens Business was nominated in recognition of the efforts of Juan Rey, VP of Engineering, at a number of 3D-IC focused conferences in 2017.

Engineer of the Year: Gill Fountain, Xperi (Ziptronix) was nominated for expanding the chemical mechanical polishing process window for Cu damascene image sensor processing.

Equipment Supplier of the Year: FRT GmbH was nominated in recognition of its third gen surface metrology tools that combine multi-sensor technology and hybrid metrology in one measuring system.

Material Supplier of the Year: Semblant for their MobileShield technology, a nano-coating that protects mobile phones from water damage and corrosion.

Process of the Year: F.A.S.T., KOBUS  was nominated for combining the CVD and ALD deposition.

Research Institute of the Year: Fraunhoffer IZM  was nominated for launching a consortium to bring research and industry together on all questions of implementing panel level packaging (PLP)

The dress up photo booth was certainly lots of fun. Below we see General Chair Peter Ramm, 3DIncites Francoise von Trapp and a group shot of the nights award winners.


Proceeds from the event went to two charities: the IMAPS Microelectronics Foundation, which exists to support student activities related to the study of microelectronic packaging, interconnect and assembly; and Phoenix Children’s Hospital pediatric oncology programs which exists to save children with cancer.

Next week we will start to look at some of the key presentations.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 373 Semi ISS Part 2: ASE’s Hunt describes “Transformative Fan-Out” Packaging

February 28th, 2018

By Dr. Phil Garrou, Contributing Editor

Finishing up our look at the 2018 SMI ISS meeting, let’s take a look what John Hunt, ASE, had to say about the “Transformative Power of Fan-Out.”

Without question so called “fan-out packaging” has become the new packaging buzz word having replaced 3D-IC a few years ago. Focus on this technology has quickly (vs 3DIC) produced significant technical advances and led to broad commercialization. Although IFTLE has covered this technology in detail since its inception by Infineon, it is always good to review it one more time, which is what John Hunt did for the mostly front end folks assembled at Half Moon Bay.

Hunt’s slide shown below is an extension of the well worn slide showing why wafer level packaging developed with a low cost structure, i.e. the packaging was done on the wafer before dicing. Hunt contends, correctly, that the same is true for the WL FO WLP, though I would add that this also shows why the early eWLB structures from Infineon couldn’t get down low enough in cost for major market penetrations, i.e. the extra steps involved with creating the reconstituted wafer.

ASE 1-3

Fan Out Enables Multi Die Packages

  • Advanced technology nodes increase wafer cost
  • Fan out allows partitioning into different nodes
  • Fan out allows partitioning of functionality
    • Digital, Analog, Components, MEMS, and IPDs

ASE 2-2

Fan out can be done either chips first or chips last as shown below. The newer chips first, face up (followed by planarization) and chips last options have resulted in much higher density interconnect which has allowed competition with some of the silicon 2.5D applications.

The high density fan out chip on substrate (FOCoS) is capable of 2/2.5um L/S and 4 metal layers as shown below:

ASE 4-2


Significantly thinner PoP can now be fabricated I much thinner formats:


In addition, they are still looking at moving FOWLP technology to large panel format in an attempt to continue to lower costs even further.

For all the latest in Advanced packaging, stay linked to IFTLE…

IFTLE 371 Semi ISS: Market Opportunities and Drivers

February 21st, 2018

By Dr. Phil Garrou, Contributing Editor

Let’s take a look at some of the presentations given at the Semi ISS (Industry Strategy Symp) conference in January at Half Moon Bay.

VLSI Research

Lati of VLSI Research discussed “Market Opportunities in the Coming Technology Disruptions”

Six companies are now responsible for > 70% of Capex spending. Memory Capex hit $45B in 2017, more than 50% of total spending.

Fig 1 VLSI Res

- Samsung accounted for more than half of DRAM spending in 2017. Other suppliers will have to respond with increased spending in 2018 to prevent share losses.

Semiconductor assembly equipment is expected to account for $5.2B in sales in 2018 with assembly equipment trends shown below.



Versum Materials

Novo of Versum Materials discussed “The Semiconductor Industry from a Materials Suppliers Perspective.” He listed the following forces acting on Materials suppliers:

Fig 3 Versum

Consolidation means fewer and much larger customers…

  • Customer Centric vs. Market Centric model
  • Higher pressure
  • Access is critical for more limited POR opportunities
  • Risk/Rewards are greater
  • Too many suppliers for shrinking customer base

Shift to Asia requires footprint changes in terms of:

  • Supply
  • Distribution
  • Innovation

Giga sized fabs mean:

  • Greater Customer Expectations
  • Implications of Winning/Losing
  • Increased Ramp Complexity, Volume & Variability

They list the following as Criteria for Success in the 2020s:

Fig 4 Versum

IHS Markit

Jelenick of HIS Markit discussed Global Semiconductor Market Trends. Their breakout of the consumer electronics market by IC categories follows:

Fig 5 IHS 1

Electrification, automated driving and connectivity are expected to drive the growth in the automotive sector.

fig 6 IHS 2


For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 371 RIP 3D-ASIP: 2004 – 2017

February 14th, 2018

By Dr. Phil Garrou, Contributing Editor

The 14th 3D ASIP Conference (3-D Architectures for Semiconductor Integration and Packaging) has officially ended. It was decided that the longest running focused 3DIC conference was no longer needed by the community since the technology is now fully commercialized in 3D memory stacks and numerous high end applications. For sure, there will be further advances in 3D, 2.5D and ancillary technologies, but it was felt that they could best be handled at your standard advanced packaging conferences. As they say “It’s best to go out when your still on top.”

3-D Architectures for Semiconductor Integration and Packaging, or 3D ASIP as it became known, started in 2004 sponsored by RTI International as a means of showcasing its wafer to wafer bonding technology being developed by spin out Ziptronix. Through the first 12 years it was organized under RTI’s Matt MeCray, who, although not a technologist in the area, developed the vision of having a conference on 2.5/3D technology focused on commercialization and business issues and focused on corporate and Institute “invitation only” presentations. For 14 years, hundreds of 3D practitioners assembled in Burlingame CA ( except for a 1 years hiatus in AZ) in early December to discuss the latest breakthroughs in the area. I joined the team as a program chair in 2008 working with Matt to define the programs content /speakers. After working with Matt for 7 years he moved on to do other things in RTI after the 2014 meeting. In 2016 RTI transferred the meeting to IMAPS where it has resided the past two years being chaired by Mark Scannell – Leti, Mitsu Koyanagi-Tohoku Univ. and myself. Below you will find some photos of those involved with the conference through the years and those who have served as program chairs.

A personal thank you to all presenters, who were a who’s who of the 2.5/3D world, and attendees. For me it was an enjoyable decade. I hope it was informative and enjoyable for all of you as well.

3DASIP pics chairs

For all the latest on advanced packaging, stay linked to IFTLE…

IFTLE 370 3D-ASIP Part 3: Bonding and Assembly in HBM Memory Stacks

February 8th, 2018

By Dr. Phil Garrou, Contributing Editor

Continuing our look at the 14th annual 3DASIP Conference.


Tom Strothmann of K&S discussed the requirements for HBM Memory Stacking. High Bandwidth Memory (HBM 1,2) are currently assembled using C2W compression bonding. Production is mostly done by memory suppliers as opposed to OSATS. HBM 3 is projected for 2019.

K&S 1

There are two prominent stacked die process flows:

    • TC-CUF (Thermocompression with Capillary Underfill)
      • Die by die stacked using TCB
      • Die stack tacked followed by mass reflow
    • TC-NCF (Thermocompression with Non-Conductive Film)
      • Stacked die by die using TCB
      • Die stack tacked followed by Collective Bond
      • Die stack tacked followed by Gang Bond

Cost reduction has focused on units/hr for the TCB process:

    • Bondhead temperature ramp speed
    • Target and die material handling systems
    • Number of bondheads and accuracy requirements

Tacking has the potential to move machine UPH from 1700 to 3500 for a 4 die stacked process using NCF if a separate gang process is used.

K&S 3


TSV Die Stress and Warpage

  • Silicon thinned to 50 microns during the via reveal process then has backside dielectrics and UBM applied
  • Imbalanced stress resulting from the dielectrics, metals and pillars on the front of the wafer as compared to the back of the wafer causes warpage in the thinned silicon wafer
  • Stress remains after dicing, resulting in die bowing that can be as much as 40um in a 9x9mm die

TCB with CUF Process

  • TC-CUF processes have been used for stacked die production in HVM. Flux dip before placement followed by capillary underfill is a mature process.
  • Typically lower throughput because the flux dip must be done below 100ºC to avoid premature activation of the flux. UPH >1000 is still possible during bonding with a dual head machine.
  • TC-CUF die stacks have a narrow process window due to thin die warpage. Single die can be held flat during the bonding process , the next die in the stack does not. Heat is conducted through the thin silicon and Cu pillars into the die below, causng solder remelt and relaxation to original warped shape resulting in BLT variation. Since the top die is still held flat, this can create inconsistent bondline thickness throughout the stack.

TCB with NCF (non conductive film)

  • NCF has the benefit of locking the BLT during the bonding process to enable a “flat die” process and more consistent bond lines
  • TCB process can be optimized independent of die stack position
  • Potential to remelt a lower die and change BLT is removed, enabling better process capability
  • But…high forces may be required for bonding some layers based on die size and pillar count

As shown below the thickness of the NCF must be exact or the interface will suffer from particle entrapment or voiding.

K&S 2

Strothmann also offered the following opinions on alternative bonding approaches:

  • Cu-Cu bonding is an area of active development work but is less likely to be applied to memory stacking in the near future
  • Direct (hybrid) bonding of chip to wafer is unlikely for memory stacking

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 369 Samsung HBM2; Ultra Fine Pitch Interconnect; Thin Die Pick and Place

February 1st, 2018

By Dr. Phil Garrou, Contributing Editor

First introduced in June 2016, the Samsung HBM2 consists of eight 8Gb HBM2 dies and a buffer die at the bottom of the stack, vertically interconnected by TSVs and µbumps. With each die containing over 5,000 TSVs, a single Samsung 8GB HBM2 package has over 40,000 TSVs. Including spares TSVs ensures high performance, by enabling data paths to be switched to different TSVs when a delay in data transmission occurs. The HBM2 is also designed to prevent overheating beyond certain temperature to guarantee high reliability. The HBM2 reports a 256GB/s data transmission bandwidth, offering more than an 8X increase over a 32GB/s GDDR5 DRAM chip. With capacity double that of 4GB HBM2, the 8GB solution contributes greatly to improving system performance and energy efficiency, offering ideal upgrades to data-intensive, high-end computing (HPC) applications that deal with machine learning and graphics processing .

Last week Samsung announced that it has started mass production of its 2nd-generation 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) with the fastest data transmission speed on the market today.[link] Dubbed “Aquabolt”, it is claimed to be the industry’s first HBM2 to deliver a 2.4 gigabits-per-second (Gbps) data transfer speed per pin, at 1.2V for the supercomputing and the graphics card market.

This performance is reportedly 50% greater than the 1st-generation 8GB HBM2 package with its 1.6Gbps pin speed at 1.2V and 2.0Gbps at 1.35V.

A single Samsung 8GB HBM2 package will offer a 307 GBps data bandwidth, achieving 9.6 times faster data transmission than an 8 gigabit (Gb) GDDR5 chip, which provides a 32GBps data bandwidth. Using four of the new HBM2 packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth.

In addition, Samsung increased the number of thermal bumps between the HBM2 dies, enabling better thermal control in each package. The new HBM2 also includes an additional protective layer at the bottom, which increases the package’s overall physical strength.

Samsung HBM2


Continuing our look at the presentations at the 14 3D ASIP Conference.

Micross – Ultra Fine Pitch Interconnect

Matt Lueck of Micross gave a presentation on their Ultra fine pith interconnect technologies that are being used in their Northrup Grumman (NGC) DARPA CHIPS program discussed in IFTLE 367 [link].

Fine pitch (< 80 um), Cu pillar thermo-compression bonding (TCB) has been widely adopted for advanced packaging of stacked memory and many other applications. Major foundries and assembly houses are offering Cu pillar down to 30 – 50µm pitch with 20 – 30µm pitch in development. Availability of fine pitch Cu pillar bumping from foundries and OSATs are limited to high volume customers and off-shore processing.

Micross has been developing fine pitch technologies over the years under their previous ownership ( Microelectronic Consortium of NC (MCNC) and Research Triangle Institute (RTI). They re positioning themselves as a source for prototype and small volume production of such ultra high pitch interconnect.

They have used 10µm pitch Cu/Sn – Cu bonding in multiple programs since 2007 such as large area array detector applications. They report that such interconnect have shown proven reliability, even for heterogeneous integration with CTE mismatch issues.

  • For next generation area array imaging applications, sub-10 µm pitch electrical interconnects are desired between detector chip and ROIC
  • A process for the fabrication and bonding of 5 µm pitch Cu-Cu interconnects was demonstrated
  • I-V curves indicate ohmic behavior of interconnect chains
  • Leakage current measurements indicate > 100 GΩ isolation between adjacent channels of interconnects
  • Demonstrated high yield on 1280 x 1024 array sample

Micross 1

Working with NGC they are developing 4 – 10µm pitch gold-gold bonding technology. The evaporated gold bumps show RMS roughness of 3.7-3.9nm.

micross 2

BESI- Thin Die Pick and Place

Stefan Behler of Besi discussed “How to peel Ultra this dies from Wafer tape”

Behler describes 4 key properties as shown below:


(1) Wafer foil peel force depends on the foil type and the peel speed as shown in table below.

besi 2

(2) edge peel force depends on the dicing method

(3) Bending stress depends on the Ejector type with thinned die resulting in more bending stress.

besi 3


(4) die strength appears (measured by 3 point bending test) is almost independent of thickness but is dependent on :

  • surface (active structure)
  • backside (grinding, polishing…)
  • edges (dicing)

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 368 IMAPS addresses the Chip-Package Interaction (CPI)

January 25th, 2018

By Dr. Phil Garrou, Contributing Editor

This week, I am interrupting our look at the 2017 3D-ASIP conference to take a look at consolidation in the equipment industry and the recent issue of IMAPS Advancing Microelectronics magazine.

Equipment Consolidation

IFTLE has explained many times that a sure sign of industry segment maturity is when the 3 top players have a combined > 80% market share. The best examples of this currently are hard disk drives and DRAM memory.

The latest data on the equipment industry market shares points to this segment being very close [link] . Had the TEL/ AMAT merger gone through, the industry truly would have reached the definition of maturity. I would be looking for attempts at other combinations in this segment to be coming soon.


Chip Package Interaction

Urmi Ray, VP of Technology for STATS ChipPAC (JCET) has edited a special edition on the chip-package interaction, which is definitely worth a read [Advancing Microelectronics, Nov/Dec 2017, V44, No 6.][Link]

As most of you know, CPI is the interaction between the semiconductor package stresses and the semiconductor device. Package stresses are caused by thermal, mechanical and chemical mechanisms. CPI contributes to various failure modes during package assembly and field life. The emergence of both fan in and fan out wafer level packaging, while delivering unparalleled form factor and cost improvements by eliminating the package substrate, has resulted in loss of a buffer layer between the chip and PCB resulting in additional stresses being transmitted to the die surface during SMT assembly.


Zhao and co-workers at Qualcomm discussed the “Electrical Chip- Board Interaction (e-CBI) of Wafer Level Packaging Technology”.

The industry is clearly moving packaging technology toward WLP and Fan-Out WLP to reduce packaging cost and form factor. One of the key dif­ferences between Flip Chip CSP (FCCSP) and WLP/FOWLP is the absence of a package substrate in the latter packaging options. For e-CPI in FCCSP, the package substrate isolates the chip from the PCB. Without the package substrate, the silicon die in WLP/FOWLP directly inter­acts with the PCB board. The mediation of the board stresses by the packaging substrate is now gone and one must evaluate the risk of direct PCB stress on the chip, i.e. electrical chip-board interaction (e-CBI). For WLP and FOWLP, e-CBI can be signifi­cant.

For example, they point to the fact that visual in­spection of FOWLP reveals dimple patterns on the backside of the parts after board level underfill which correlate with the pat­terns of BGA depopulation. In the absence of the mechanical support from BGA solder balls in the depopulated areas, the board level underfill shrinkage pulls the thin silicon die to­wards PCB. FEA models have verified this phe­nomenon and reproduced similar “dimples”. Since the silicon die bends toward PCB in the BGA depopulated regions, this infers that tensile stress is being created on active silicon surface.

qualcomm 1



Ivor Barber and co-workers discussed “14nm Chip Package Interaction Technology Development.”

With the implementation of extreme low K (ELK) porous dielectric materials (k < 2.5) into the back end of line (BEOL) to reduce the in­terconnect capacitance and cross-talk noise and enhance circuit performance, the lower mechanical strength of the ELK, along with increased die size, difference in effective coefficient of thermal expansion (CTE) between die and substrate, and the use of higher stiffness lead free solder increasingly contribute towards ELK layer cracking. Chip package interaction (CPI) be­came one of the critical reliability issues that needed to be addressed to avoid electrical or mechanical failure in products.

In order to evaluate CPI risk and reliability concerns from a technology point of view, they developed a CPI test vehicle (TV) which must include the same BEOL stacks, same ELK ma­terial, same BEOL process, same bump technology, same substrate technology, same assembly process for the pro­duction of the same Si node. In their 14nm CPI development, a 14nm TV with die size of 21×21 mm2 with 140um bump pitch of SnAg bump has been selected. 40×40 mm2 substrate has been used in our CPI technolo­gy qualification. JEDEC standard tests (Precon, UBHAST, TCJ, MSL, and HTS) were used as criteria for the CPI tech­nology qualification.

ELK delamination / cracks called “white bumps” are encountered as rigid lead free bumps would transfer more stress to weak ELK layers causing ELK crack underneath the bump. Unlike bare silicon dies, thermal deformation of pack­aged dies can be directly coupled to Cu/low-k or ELK interconnects, inducing very high local stresses to drive fracture and delamination. ILD delamination is caused due to dicing defects like micro-cracks and poor adhesion or mechanical strength of low-k/ELK dielectric materials under the thermal load of the processes like flip-chip as­sembly process or thermal cycling tests.


In order to improve the CPI margin, studies have examined passivation thickness, polyimide thickness, under bump metallization, CTE of substrate, and FBEOL. Simulation and DOE have shown that by using thicker Aluminum terminal metal and two layers of passivation, the CPI risk reduced significantly. So foundries have now implemented this dual pas­sivation layer with Al terminal metal to enhance CPI reli­ability.


Simulation has shown that ELK stress are reduced with reduced bump pitch.

The fracture toughness of low-k/ELK dielectrics vs SiO2, is substantially reduced and is significantly lower than that of Si. It is thus much easier to induce defects like micro-cracks during dicing. Those tiny cracks can develop and propagate into the active die area and cause failure un­der thermal-mechanical stress. One approach to prevent cracking at the die edge or die corner is to apply patterned metal structures called crack stop around the perimeter, especially reinforced at the die corners. They found that double wall crack stop was necessary for products with large die size to provide protection for the dicing defects.

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 367 CIS Consolidation; DARPA CHIPS Headlines 14th 3D-ASIP Conf.

January 17th, 2018

By Dr. Phil Garrou, Contributing Editor

Consolidation in CIS Market

Remembering our IFTLE rule [ see IFTLE 241, “Simply Obeying the Laws of Economics”] that maturing markets have 3 players with > 85% of market share, we note that Gartner Assoc. has reported that the top 5 vendors accounted for 88.9% of global CIS revenue in 2016 and the top 3 companies have 78.9% of the market, up from 77.1% in 2015 so we are getting close… [link]

GArtner 1


Teledyne / DALSA

Invensas (Experi) has announced technology transfer of its Direct Bond Interconnect (DBI) to Teledyne DALSA. This capability enables Teledyne DALSA to deliver next-generation image sensors to customers in the automotive, IoT and consumer electronics markets. Invensas and Teledyne DALSA announced the signing of a development license in February 2017. All of the major image sensor players appear to be adopting this image sensor stacking technology.

Chip Stacking for Image Sensors

Ray Fontaine at TechInsights has this to say about image sensor technology in 2017 “Chip stacking (image sensor + image signal processor) for image sensors remains an enabling technology for improved camera performance, and this year we documented Sony’s first-generation TSV-based three die stack (now adding a DRAM) in mass production. For two-die stacks, we still primarily see TSV-based chip-to-chip interconnect, although Sony has been using direct bond interconnects (Cu-Cu hybrid bonding, or DBI) since early 2016. We recently saw OmniVision and foundry partner TSMC join the hybrid bonding club and claim the new world record, based on TechInsights’ findings, of 1.8 µm diameter, 3.7 µm pitch DBI pads.” [link]


The 14th annual 3D ASIP conference, in early December, deviated somewhat from its traditional focus on 3DIC content to cover ancillary and complimentary technologies. Below we see incoming IMAPS President Ron Huemoeller presenting plaques to Gen Chair Garrou and Tech Chairs Scannell and Koyanagi.

Gen Chairs



DARPA has a long history if chip integration as is depicted in the slide below showing DARPA programs and their acronyms.



IFTLE has had extensive discussions on the 2017 DARPA CHIPS program. [see IFTLE 323 “The New DARPA Program “CHIPS”…”].

In his plenary presentation, DARPA program Mgr. Dan Green pointed out that the CHIPS goal is to develop design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of DoD and commercial designs and technology. Particular emphasis is being placed on trying to develop a technology infrastructure that can be adopted by both the aerospace infrastructure and the commercial infrastructure.


The CHIPS grants are led, as shown below, by Boeing, Intel, Lockheed Martin, Northrup Grumman and the Univ of Michigan.

darpa 3

For all the latest in Advanced Packaging, stay linked to IFTLE…

IFTLE 366 IWLPC Part 3; LED WLP & IMEC & Experi Hybrid Wafer Bonding

January 10th, 2018

By Dr. Phil Garrou, Contributing Editor

IZM Fraunhoffer TU Berlin and Osram

Tanja Braun of IZM Fraunhoffer discussed “Fan-out and Panel level technology for Advanced LED Packaging.”

The ongoing miniaturization in LED chip size and thickness down to 200 μm and below requires adapted chip handling and assembly. Innovative solutions are needed to electrically connect top and bottom contacts of the LED guaranteeing at the same time a sufficient overall thermal concept. Polymer based package solutions need to consider the aging/yellowing of the polymers on constant exposure to intense light. High volume and low cost solutions are required.

A blue LED with an area of 1×1 mm² and a thickness of 120 μm was chosen for package development. The LED has one contact pad on the topside and needs an additional electrical connection to the backside. The overall concept for the SMD compatible single LED package is shown below.


Package size was designed to 1.6×1.6 mm² allowing the integration of a through mold via (TMV) with 100 μm diameter routing the contact from the topside to the SMD compatible pads on the package backside. Package mold thickness is 300 μm resulting in a mold layer of 180 μm on the backside of the LED. The backside of the LED is connected by a blind via with a diameter of 250 μm. The process flow is shown below:


Compression molding is used for reconfigured wafer encapsulation. Recent developments now allow panel molding for sizes up to 600×600 mm². Compression molding evaluation within this study has been performed on 200 mm with a wafer level machine from TOWA and with a large area panel mold machine from APIC Yamada using a tooling with a cavity size of 457 x 305 mm². For the LED package development a liquid black epoxy molding compound (EMC) has been selected with a filler particle top cut of 25μm. Material with small maximum filler particle size has been chosen to allow laser through mold and blind via drilling with precise geometries and smooth via walls.

Die shifting is one of the key challenges during “Mold first” FOWLP. Due to the different thermo-mechanical properties of carrier, thermo-release tape and epoxy molding compound dies move such that the die position is shifted with respect to placement position after cooling down from compression molding. This effect is also influenced by the chemical shrinkage of the molding compound. Die shifting can be overcome by using a fast AOI (automated optical inspection) in combination with maskless processing for die connection and rewiring. This would give the opportunity to tolerate larger die misplacement by adapting the layout to the real die position.

Vias to the top side ad backside are shown below.



Cavaco of IMEC discussed heir results on “Hybrd Copper Dielectric Direct Bonding of 200mm CMOS Wafers with 5 Meta Layers…” where IMEC reports wafer level electrical data and reliability testing results for 200-mm wafer to wafer hybrid copper to dielectric aligned bonding on short loop wafers which consist of five backend of line (BEOL) metal levels using silicon carbon nitride (SiCN) as dielectric. The fabricated 200-mm wafer pairs are representative of a real CMOS device structure as they are processed with five metal levels per test wafer in a 130-nm copper BEOL CMOS technology.

In the wafer to wafer hybrid bonding process, two substrates are connected simultaneously by a copper to copper metal bonding and by an inter layer dielectric (ILD) oxide bonding. Some of the main issues inherent to the hybrid bonding process are: the profile of the copper pads after copper chemical-mechanical-planarization (CMP); the oxide erosion; the used surface treatment before bonding; the wafer to wafer bonding alignment accuracy; the contact integrity; the contact reliability; and manufacturing yield issues.

The full bonding sequence essentially comprises a wet clean module, a plasma module for surface activation and a bonding aligner module. A bonding accuracy below 1μm can be achieved by using dedicated alignment keys on both sides of the wafers. Bonding misalignment on the X direction was of the order of 0.7μm. Afterwards, the wafers were brought into proximity and dielectric bonding took place. Subsequently, copper to copper bonds are formed during a post-bonding anneal step.

SiCN was chosen as the dielectric layer(a) because SiCN is known to have a higher bonding strength when compared to SiOx, or SiN and (b) because SiCN can act as a barrier against metal diffusion into the dielectric, which can take place when using SiOx in a hybrid bonding process that comprises copper line patterns.

To confine the copper bonding pad dishing/protrusion to values below 10 nm, a strict process control of the CMP step is required on all wafers.

IMEC 1-2

In this study, both HTS and TC reliability testing were performed at wafer level. More specifically, TC testing consisted of up to 1000 temperature cycles, of one hour each, from -40 °C to +125 °C. HTS testing consisted of storing the wafers, in a nitrogen environment, up to 1000 hours at +125 °C. Zero-yield loss observed at the end of both TC or HTS reliability testing.

Xperi (Ziptronix)

Gao and co-workers from Xperi discussed their studies on the “Development of Hybrid Bond Interconenct Tech for D2W and D2D Applications”

We have discussed previously the acquisition by Xperi (Tessera) of Ziptronix and their DBI bonding process [see IFTLE 253, “China Inc Seeks to Acquire GF; Tessera Acquires Ziptronix; Tezzaron 8 layer 3DIC “ (link)]

This DBI (hybrid bonding) technology has been licensed and widely adopted by players in the CMOS imaging sensor industry such as Sony and Omnivision [see IFTLE 325, “ Omnivision takes Ziptronix License…” (link)]

To the best of my knowledge al of the CMOS image sensor work is being done on 200mm wafers , i.e W2W. Rumor has it that the process is much more difficult when trying to do D2W or D2D bonding. Attempting to resolve this issue and expand the use of the process in their applications, Xperi has undertaken a study of the D2W process looking to compare it to the more standard TCB (thermos compression bonding).

Obviously aiming at the stacked memory business, their test structures consisted of a host wafer designed to mimic the logic controller in a HBM stack. The fig below shows an illustration of four dies stacked on top of a host wafer. Daisy chain coverage includes hybrid bonding between the following interfaces: host die to die 1 bottom: die 1 top to die 2 bottom; die 2 top to die 3 bottom; and die 3 top to die 4 bottom. Currently, the stackable die does not have through-silicon vias (TSV). Consequently, electrical testing is limited to the die 1 bottom to host die interface. For next phase of development, TSV will be included to enable electrical testing of all interfaces.

Experi 1

It is desirable to maintain the RMS roughness of silicon oxide on the bonding surface below 0.5nm to facilitate high bond energy between the silicon oxide components of the hybrid bond. A similarly low surface roughness of copper is also desirable (although less critical) to further increase bond energy. In addition, it is desirable to have the Cu surface slightly recessed from the oxide surfaces.

The table below compares the total process time and throughput of a bonder for TCB and hybrid bonding. The hybrid bonding process requires very low contact force. It is essentially a P&P only process. It requires no temperature profile, no pressure control and no dispensing of additional material. On the Toray bonder, they demonstrated that 10s and 1s bonding dwell time shows the same bonding results. On the Datacon bonder, we have demonstrated bonding dwell time of 0.1s. With addition of 0.5s material handling time to each machine, the calculated throughput is 2400 unit per hour (UPH) on the Toray bonder and 6000 UPH on the Datacon bonder.

Compared to TCB, the hybrid bonding requires additional processes for die cleaning, activation and anneal. However, all these processes are carried out in batch and does not limit the throughput of the bonder.

experi 2


Bonds with poor electrical contact appear to be the result of particulate contamination . Such contamination is considerable reduced in a class 100 clean room environment. Optical images of the die stack is shown below.

experi 3

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