Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California. (Photo Credit: Rex Gelert)

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(You can get the pdf of the full program & registration information from the website.)

THE PAPERS

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

1. Plenary: talks by Soitec and ARM
2. Fully-Depleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
10. Hot Topics: Fully-Depleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
11. Late News: tbd, of course…

THE COURSES & PANEL

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively, favorite event. This year’s invited distinguished experts — Scott Luning (GF), Ali Khakifirooz (IBM), Yang Du (Qualcomm). and moderator Sorin Cristoloveanu (Grenoble Institute of Technology) – will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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SOI in general and FD-SOI in particular were hot topics at this year’s Semicon West in San Francisco. A panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry was among the highlights.  It featured an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

• ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
• GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
• IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
• SOI Industry Consortium: Horacio Mendez – Executive Director
• Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
• STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
• UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI figured prominently in a panel on mobile challenges held during Semicon West '12. Left to right: C. Hu (UCBerkeley); R. Moore (ARM); H. Mendez (SOI Consortium); G. Patton (IBM); P. Magarshack (ST); S. Kengeri (GF); S. Longoria (Soitec)

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs (where in the past it was CPUs) and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out products based on ultra-thin layers of both SOI and insulator, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm this summer.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FD-SOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show for the SOI ecosystem, full of energy and renewed enthusiasm.

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Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)

The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop.

Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.

It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.

The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.

Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.

The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)

This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.

Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.

The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.

Here’s a preview of program – you won’t want to miss it.