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GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

Monday, October 5th, 2015

By Adele HARS

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

Over 65% Smartphone RF Switches SOI, Says Yole; Power Amps Next

Wednesday, August 14th, 2013

By Adele Hars, Editor-in-Chief, Advanced Substrate News

The industry research firm Yole Développement says that more than 65 percent of substrates used in fabricating switches for handsets are SOI-based. This is a high-growth part of the market, putting up double-digit increases.

Like a standard SOI wafer, an RF SOI substrate has an active (“top”) layer on which CMOS transistors are built, with an isolating (“BOx”) layer under it.  The main difference is that the bottom “base” layer under the layer of isolation is a high-resistivity material. This reduces noise and interference, which helps the finished die reach its target performance in terms of signal integrity, handling RF power and integration density. SOI-based devices can reach a figure of merit for on-series resistance and off-equivalent capacitance (Ron.Coff ) below 200 fs (femtoseconds) with potential for further reduction. This directly relates to improved device performance and smaller die size.

At Semicon West SOI wafer manufacturer Soitec announced that its SOI technologies are now mainstream for manufacturing switches and antenna-tuners, key RF components for cell phones and tablets.

There are also new challenges as the industry moves from from 3G to 4G/LTE and further LTE Advanced using carrier aggregation. With SOI, designers can beat the demanding linearity requirements such as intermodulation distortion (IMD), going far beyond -110 dBm, thereby helping avoid interference between networks, says Soitec.

“RF SOI technologies enable the device integration, cost effectiveness and high performance needed for high-volume 3G and LTE applications,” explains Bernard Aspar, vice president, Communication & Power Business Unit at Soitec. “RF, with over 100 percent revenue growth last year, remains a strategic market in which we have been continuously investing for more than a decade.”

Aspar says that as the leading supplier of engineered wafers, Soitec is looking to catch the next growth wave in the RF market.

Based on recent demonstrations, Soitec sees power amplifiers as likely be the next RF components based on SOI. The technology enables highly tunable amplifiers to address multi-region requirements on a single platform. The RF SOI substrates also offer a path towards further integration, such as more mixed-signal and digital content.

Soitec explains that its approach is to offer a wide choice of engineered substrates, so that RF device manufacturers can choose the solution that aligns best with their market strategies – from low-cost GSM handsets to multi-band, multi-mode LTE smartphones and tablets.

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FinFET Isolation: Bulk vs. SOI

Wednesday, May 15th, 2013

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI.  It generated immense interest, and created lots of discussion on various LinkedIn groups.  In case you missed it, here it is again.

(This article is based on an in-depth presentation Terry gave at the SOI Consortium’s Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2013.  The complete presentation is freely available on the SOI Consortium website.)

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FinFET Isolation Considerations and Ramifications — Bulk vs. SOI

By Terence Hook, Senior Technical Staff Member, IBM Semiconductor Research and Development Center

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, reliability, and product performance.


In bulk wafers, isolation is formed in a manner similar to planar devices, with implanted wells and shallow-trench-isolation oxide separating fins from one another.

With an SOI (silicon-on-insulator) wafer, however, the fins are formed in the silicon layer, the isolating dielectric is already extant, and no well implants are required.

Figure 1: Schematic representation of bulk junction and dielectric-isolated FinFETs

The most important differences in the devices formed in these two manifestations lie in the shape of the fin, the processes that determine the effective fin height, and the presence of doping, which consequently affects the device in many adverse ways such as the variability and the reliability.

The final realization of the full potential of fully-depleted FinFETs is dependent on optimally addressing the issues enumerated herein. Dielectric isolation is shown to provide superior characteristics in all of the above-named aspects. Figure 1 shows a schematic representation of FinFETs for the two isolation architectures, with the various critical points of distinction noted as are discussed below.


Definition of the fins on an SOI wafer is relatively straightforward; vertical fin sidewalls may easily be obtained.

In a bulk-based process, as the spaces between the lower, electrically inactive portions of the fins must be filled with an insulator, some angling of the fin is required to prevent the formation of voids.

Figure 2: Typical bulk junction and dielectric-isolated FinFET fin profiles

Bulk and SOI fin profiles are pictured in Figure 2.  As tapering the fin compromises the subthreshold slope and degrades the effective drive current as well as the output conductance, minimization of the taper is important to the electrical integrity of the device.


Whereas in an SOI design the transistor-transistor and subfin source-drain current paths are inherently interrupted by the dielectric layer, in a bulk-based process adequate doping for electrical isolation and latchup immunity needs to be established.  This requires additional masking levels and connections for electrical bias.

Conventional design criteria of doping, depth, and overlay tolerances apply to the deep interdevice isolation wells, but suppression of undesired current in the drain-source region has unique features in the FinFET configuration.

Suppression of punchthrough current requires some level of doping at least in the bottom portion of the fin. The adverse effects of doping on mobility and random-dopant-fluctuation have been reported; non-uniform doping is particularly egregious as it increases capacitance without a concomitant increase in drive current.

However, the level of doping required depends on the alignment of the gate and the source junction depth. An optimum choice for the conjunction seeks to minimize the dopant required while respecting physical process window constraints (see Figure 3).

Figure 3: Short-channel effects as a function of doping and gate recess depth relative to the source junction depth in bulk FinFETs

Another adverse effect of doping in the fin is the implication for the gate work function. For junction-isolated FinFETs, the gate metal work function is established so as to provide the desired threshold voltage in the presence of doping; for undoped dielectric-isolated FinFETs the appropriate work function is closer to midgap, which reduces gate leakage and improves reliability.

Figure 4: Voltage operating range as a function of fin doping

Between RDF-driven Vmin and work function-driven Vmax, the operating window of bulk FinFETs is more limited than that of undoped SOI FinFETs (see Figure 4).


Designing with planar bulk technology has historically differed from planar SOI technology in three aspects: well contacts, self-heating, and floating body effects.

At the expense of area, planar bulk technology has enjoyed the advantages of controlling the threshold voltage through the well potential.  No such benefit exists in bulk FinFET devices, as it is not possible to influence the transistor through the well bias except in the spurious and undesirable region below the active fin.

In fully-depleted devices the concept of a floating body (charge storage in an isolated neutral region) is not applicable, so SOI and bulk FinFETs behave the same way for all switching scenarios.

Self-heating effects, while not important for fast switching operation, can be relevant for DC circuits. While large-area planar structures will continue to enjoy the advantage in thermal conduction relative to SOI traditionally observed, bulk and SOI FinFETs have very similar self-heating characteristics, as the only difference in thermal conductance is a tall, thin sliver of silicon, which provides only a small increase in thermal conductance.

While bulk FinFET technology has lower soft error rates than planar bulk technology, SOI FinFETs are better yet.


Fin height variation has a much more serious impact than the planar analog of transistor width variation. Wide transistors (i.e., many fins) have the same variation as narrow (i.e., few fins).

Figure 5: Calculated dependence of SOI and bulk transistors on key process variations, and relative variations in the two architectures

Whereas in the SOI-based version the electrical fin height is determined by the starting silicon thickness, in the bulk-based FinFET process the fin height is determined by several processes, and the distinction between “active” and “inactive” fin is blurred by the conjunction of the gate alignment with the source junction.

The sensitivities to various key variables have been calculated with hardware-calibrated 3D simulations, and the variation of those key parameters determined with respect to state-of-the-art processes (see Figure 5).

The fin variation-driven performance tolerance of a bulk FinFET is larger than that of an SOI FinFET.   That benefit of SOI is not only found in sort yield and worst-case design corners, but smaller variation within a chip enables a faster chip for any given level of leakage.


Complete realization of the benefits of fully-depleted transistor architecture is affected by the choice of isolation. Increased range of operating voltage, process simplification, reduced variation, lower soft error rate, and higher circuit density are all features of a dielectric-isolated architecture.

For these reasons the ability of an SOI-based FinFET to reap the full benefits of fully depleted transistors is demonstrably superior to a doped, bulk-based implementation.

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GF’S Two Flavors Of FD-SOI

Wednesday, April 17th, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.

Subi Kengeri, VP Advanced Technology Architecture, GlobalFoundries

What do you see as the FD-SOI benefits for chip designers?

  • Lower SRAM Vmin for retention and lower operating Vmin for Logic
  • Wider range of Voltage operation for performance/power trade-off
  • Total dielectric isolation equates to lower capacitances, lower leakage, and latch-up immunity
  • Ultra-thin silicon film provides excellent electrostatic control and optimum transistor performance
  • Back-bias control gives an additional speed boost
  • Simple planar process using same front end and back end as our 28SLP process, which means fewer process steps and fewer masks, helping to absorb the additional substrate cost

What are your plans for making FD-SOI available to your customers?

We are the manufacturing partner for ST’s FD-SOI technology. We also are planning to offer the technology to other customers who may be interested, but we have not announced details yet. We are the only pure-play foundry with deep experience in both bulk and SOI technologies, which allows us to offer a broader range of technologies at advanced nodes.

GlobalFoundries’ Fab 8 in upstate NY

Can you elaborate on the “maximum” version of FD-SOI — tuned for specific applications — what sorts of things would those be?

Examples of features in the Maximum version of FD-SOI:
a. Back-bias capability on logic for higher performance
b. Denser SRAM by taking advantage of lesser variability of Fully depleted device
c. Base Vts tuned for specific applications (performance vs power trade-off)

And the “minimum” version — a simple and “out of the box” FD-SOI technology — who/what is this for?

a. No Back-bias supported
b. All SRAMs are foot-print compatible to 28SLP
c. Fully depleted device offers better Vmin and power advantages: Optimized for Mobile Applications

Are there any special logistics in terms of the PDK, IP, etc?

a. PDKs are similar to bulk CMOS, except the models will support a 4-terminal device for Back-bias
b. In the base version (termed as minimum version above), IP’s Physicals are fully compatible with bulk CMOS, but would require electrical re-characterization to take advantage of improved FD-SOI device characteristics
c. In the extended version (termed maximum version above), IPs will be designed to take advantage of Back-bias for better performance/power trade-offs in specific applications

What is the next node, and when will that roll out?

See slide 8 of [this] presentation:

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Over 50% Of Smart Phones And Tablets Leverage SOI

Monday, March 18th, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In a recent press release, the SOI wafer leader Soitec said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. 50%? That’s a lot! How do they figure that? The answer: RF.

As seen here, RF chips account for a large part of cellphone components. (Source: Soitec & UCL, ESSDERC ’12 RF Workshop)

With all the talk right now about FD-SOI for application processors, the importance of the RF chips might seem to get a little lost. Don’t expect that to last.

Soitec’s wafer shipments for RF apps have increased by 400 percent in the last two years. In their current fiscal year (which ends this month), the company says it will have shipped over 200,000 engineered wafers to customers making chips for mobile comm. Those wafers translate into about 2.5 billion ICs for RF front-end module apps, which covers half of the 600 million smart phones and 100 million tablets expected to be produced this year.

Soitec, of course, does several flavors of SOI (including bonded silicon-on-sapphire aka BSOS, and high-resistivity (HR) SOI, which Soitec markets as their Wave SOI™ product line) as well as epitaxial GaAs wafers. It all adds up.

If app chips are the heart of the smartphone, RF is the soul. But in terms of chips and substrates, the RF side of the mobile world is much more complicated than the app side. Different functions have different needs, and those needs have traditionally been best met by disparate starting substrates. Devices can have eight of more chips and modules, and the chips in any given set can have different starting substrates, depending on the critical parameters.

The advent of LTE – “long-term evolution” aka 4G – will have a phenomenal impact on the RF components market, with analysts looking for RF components to almost double in value over the next five years. Look for an alphabet soup of new chip modules designed to handle the enormous complexity of evermore frequency bands.

Front-end modules (FEMs), which handle the back-and-forth of signals between the transceiver and the antenna, already contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. With FEM real-estate reduction tracking at 15%/year and market growth continuing to increase at 15%/year for at least another five years, the quest is on for better, cheaper FEM solutions. Some are targeting SoCs, some will be multi-chip modules.

(Source: Soitec & UCL, ESSDERC ’12 RF Workshop)

A couple years ago, Soitec put together a really useful white paper on substrate technologies for RF. You can see, for example, that in choosing a substrate for switches, linear resistivity is the key parameter. This is something that can be addressed by several substrates, including GaAs, SoS and HR-SOI: the deciding factors are the trade-offs between performance and cost.

(Source: Soitec & UCL, ESSDERC ’12 RF Workshop)

There are huge opportunities in RF for the greater SOI & engineered substrates communities, so in coming issues of ASN, this is a topic we’ll be covering more. Upcoming articles by Professor Jean-Pierre Raskin of UCL (his group is working on a new generation of HR-SOI with enhanced signal integrity), as well as Peregrine and Skyworks, among others, are in the works.

Stay tuned!

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ST-Ericsson 28nm FD-SOI/ARM Chip Hits 2.8GHz at CES

Tuesday, January 22nd, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013.

And it’s a game changer – for users, for designers, for foundries, and for bean counters.  Here’s why.

The NovaThor L8580 integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

ST-Ericsson’s NovaThor(TM) L8580 on ST’s 28nm FD-SOI features a 2.5Ghz eQuad(TM) app processor with ultra-low power consumption. (Courtesy: ST-Ericsson)

In the eQuad CPU architecture, each processor core can operate as a high-performance core or a very-low-power core, depending on what’s needed at the moment. Since all the eQuad cores can adapt to the needs of the user at any given time, there’s no need for the dedicated low-power cores found in other multi-core CPU architectures. Remember, the 2.5GHz cores in the L8580 are the mobile industry’s fastest, or conversely, at 0.6V in low-power mode, the industry’s most battery-friendly. With all 2.5GHz cores working together, expect blazing high-performance when you’re doing something like browsing the web. But when phone’s your pocket, those cores will take barely a sip of power.

The NovaThor L8580 is essentially a straight port from 28nm bulk to 28nm FD-SOI of the (very successful) NovaThor L8540, with just a bit of tweaking to fully leverage cool things you can do with FD-SOI, like biasing to increase performance and conserve power.

For the folks designing smartphones and tablets (and ultimately for the end-user), that port to FD-SOI gets the NovaThor L8580:

  • CPUs running 35% faster and GPU and multimedia accelerators running 20% faster. In terms of multimedia performance, they’re supporting 1080p video encoding and playback at up to 60 frames per second, 1080p 3D camcorder functionality, displays up to WUXGA (1920×1200) at 60 frames per second and cameras up to 20 megapixels. (Hence their use of the descriptive “extraordinary”.)
  • 25% less power consumption than rival architectures when running at high-performance  levels – think Cooler Operation.
  • A low-power mode can deliver up to 5000 DMIPS at 0.6V – more than enough computing power for the majority of applications in everyday use. A key point here is that it enables stable SRAM operation at 0.6V – have you heard of anyone matching this? The result is that this low-power mode consumes 50% less power to deliver the same performance compared with alternative solutions in bulk CMOS.

It all adds up to big battery savings – this is the extra day CEO Didier Lamouche promised us in Barcelona last year when they announced this chip.

YouTube Preview Image

ST-Ericsson has posted an amazing video, filmed live at CES 13. In the first part of the demo (re: high-perf), on a Samsung Galaxy S3, they’ve got the Sky Castle 3D Graphics Demo launching twice as fast on FD-SOI as the bulk equivalent, and hitting 2.8GHz! And in the second demo (re: low power), they’re hitting 1GHz using just 0.636V, which would take 1.1V on bulk.

Design Highlights

For the ST-E designers, most of the IP blocks were directly re-used from the bulk design, so the porting to FD-SOI was extremely simple and fast.

For the manufacturing folks over at STMicroelectronics (and starting this year, at GloFo), FD-SOI is a planar technology that re-uses 90% of the process steps used in 28nm bulk. The overall manufacturing process in FD-SOI is 12% less complex, so they’ve got lower cycle time and reduced manufacturing costs (bean counters take note, please). They also point out that the manufacturing tools for FD-SOI are much simpler than those required for FinFETs.

Wondering what’s next? The 14nm FD-SOI node is already in development, the ARM Cortex-A15‘s  on the radar, and the FD-SOI roadmap is already defined up the 10nm node.

With FD-SOI, you can do much more with body-biasing (aka back-biasing) than you can in bulk (which suffers from too much leakage). Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel, so it effectively acts like a vertical double gate transistor. This facilitates the flow of electrons, leading to a higher voltage in the body, and faster switching of the transistor. (Image courtesy ST-Ericsson)

With FD-SOI, you can hit higher speeds with lower operating voltages. This is because the buried oxide layer prevents electrons from leaking away as they travel through the channel from the source to the drain (this sort of leakage is a major source of power consumption in 28nm bulk, which depends on doping to handle leakage). Interestingly, this graph shows ST-E going down to 0.5V – which is incredibly impressive. (Image courtesy of ST-Ericsson)

(Image courtesy ST-Ericsson)

(Image courtesy ST-Ericsson)

As the (now award-winning) folks over at ST and Leti described for us a few years ago, designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.  The ST-E designers use this feature to apply different voltages independently to the top and the buried gates of the FD-SOI transistor, which effectively changes its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high-performance transistor to those of a very low-power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power. (You can’t do this with FinFETs, btw.)

Just Posted: FD-SOI video & white paper

Just as this blog was going online, ST-Ericsson posted an excellent, in-depth white paper; and in partnership with STMicroelectroics, a YouTube video detailing the how’s and why’s of FD-SOI.Here are the links — you really don’t want to miss these:

Multiprocessing in Mobile Platforms: the Marketing and the Reality
In this white paper, ST-Ericsson’s Marco Cornero and Andreas Anyuru “…illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the upcoming ST-Ericsson products.”

An Introduction to FD-SOI
STMicroelectronics and ST-Ericsson have teamed up on this excellent video, which garnered 1250 views within the first four days of its posting on YouTube. The animations and comparisons highlight why FD-SOI is so fast, and so cool.

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Don’t miss Fully-Depleted Tech Symposium during IEDM (SF)

Tuesday, December 4th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium.

As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s been doing these symposia during major conferences for going on four years now, and lively debates always ensue.

(Courtesy: Hilton Hotels & Resorts)

This next FD Tech symposium happens the first day of the IEEE’s IEDM conference in San Francisco – Monday, December 10th at 8:15pm. Conveniently, it’s also taking place in the same building – at the SF Hilton.

Top technologists from STMicroelectronics, ST-Ericsson, IBM, ARM, Altera, LETI, Soitec, MEMC and others will be debating comprehensive Fully-Depleted Technology solutions.

But perhaps most importantly, we’re going to get the first product-level benchmarking results of 28nm FD-planar for mobile SoC and FPGA applications.  That’s silicon proof straight from the companies who are doing it.

If you’ve been following recent ASN postings from STMST-EricssonIBM and others, you know these folks are really excited about the results they’re seeing.

Here’s a peak at the presentations planned for the symposium:

  • Planar Fully-Depleted Technology at 28nm and below for extremely power-efficient SoCs:  SoC level 28nm Planar Fully-Depleted silicon results
    By Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics
  • Evaluation and benchmarking of 14nm planar Fully-Depleted Technology for FPGAs
    By Jeff Watt, Ph.D. Fellow, Technology Development, Altera Corporation
  • Challenges and comparisons of designing power-efficient SoCs with planar Fully Depleted transistors and FinFETS
    By Rob Aitken, ARM Fellow
  • Second-generation FinFETs and Fin-on-Oxide
    By Ed Nowak, IBM Distinguished Engineer and Device Chief Designer, Semiconductor R&D Center, IBM Systems and Technology Group

The presentations will be followed by a Q&A.

Admission is free, but space is limited, so you must reserve in advance – click here to go to the special registration site.

To recap, it’s the:

Fully-Depleted Transistors Technology Symposium
Hilton San Francisco Union Square Hotel (333 O’Farrell St.)
Monday, December 10th, 2012
8:15pm to 10:30pm

Food & refreshments will be provided.

We won’t all be in San Francisco, so if you can’t get there, the presentations will be posted on the SOI Consortium website (you can also get the presentations from previous events there, too, as well as excellent white papers).

If you do go and want to share your reactions on Twitter, use #FDchipTech and @soiconsortium.

This will be a great event – don’t miss it!


ST’s FD-SOI Tech Available to All Through GF

Monday, October 8th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics (Photo credit: Artechnic)

Advanced Substrate News (ASN): You taped out ST-Ericsson’s 28nm FD-SOI NovaThor in the beginning of September. Did that go as you expected?

Jean-Marc Chery, STMicroelectronics (JMC): 28nm FD-SOI is a pretty exciting technology, allowing better design optimization (for higher speed and power efficiency) than traditional bulk technologies, still reusing most of manufacturing bricks of planar 28nm LP technology and the same design flow and methodology.

Adoption of 28nm FD-SOI for ST-Ericsson’s NovaThor has not introduced any major difficulty in its design, and the FD-SOI version has been taped out shortly after the Low-Power bulk version. Of course special care has been dedicated to further optimize power, exploiting FD-SOI exceptional flexibility and low-power capabilities.

On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.

ASN: Can you talk about the results you expect to see or have seen in the chip? Is there anything about it, or perhaps about the ARM core in particular, that makes it especially well-suited to FD-SOI? Is there anything about the transistor back-biasing capability (which enables significant performance enhancements and power optimization) in the design that makes it challenging to manufacture?

JMC: The wide supply range (ranging from 1.2V down to 0.6V) with excellent performance, and extended back-biasing capability (allowing dynamic modulation of the transistor threshold voltage) offered by 28nm FD-SOI technology have allowed us to exploit the ARM implementation to offer an improved maximum frequency and reach an overall power reduction for the various operating modes of the SoC.

About back biasing, this is a standard feature of FD-SOI technology with no particular challenges for manufacturing. Of course, its dynamic usage to optimize operating points for power (or speed) requires an appropriate device architecture to fully benefit from it.

ASN: In the press, STMicroelectronics has indicated that the 28nm FD-SOI has better power and performance than the industry’s first-gen bulk 22nm FinFETs. Would you say that your choice of FD-SOI puts you in a position of strength, in that you’ll have the mobile industry’s leading technology for 28nm and a choice of mature technologies at 14nm?

JMC: 28nm FD-SOI technology is a unique offer in the SOC industry, allowing the introduction of a fully-depleted technology with a low-cost solution and in a timely manner.

28nm FD-SOI is a planar technology derived from 28nm LP bulk technology, with the same design rules and allowing direct layout reuse (or simplified porting) of basic building blocks and IPs, benefiting from inheriting their maturity level. Also on the manufacturing side, 28nm FD-SOI technology uses the same equipment as Low Power bulk CMOS in a simplified process flow. In ST/Crolles facility we are reaching yield levels comparable to 28nm LP bulk ones, proving that FD-SOI process does not introduce major yield detractors.

A smooth library and IP migration flow coupled with rapid availability for manufacturing is driving the success of this 28nm technology.

Looking at the technology roadmap, the same incremental step for the 14nm node is under development and is on track.

The STMicroelectronics fab in Crolles, France. (Photo credit: Artechnic)

ASN: The plan was to start production in your fab in Crolles, then shift to GlobalFoundries for high-volume production in 2013 — is this still the schedule? From a manufacturing standpoint, what does it take to get a fab ready for FD-SOI production (does it take much longer than a typical bulk scaling transition)? Are there any special tools or other preparations needed?

JMC: For manufacturing, 28nm FD-SOI technology uses the same toolset as for 28nm LP bulk. Process development is complete, and ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other.

Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013.

The ST Crolles fab is highly automated, and already runs a broad mix of products in addition to the new FD-SOI chips. The accumulated assets the company has invested in this fab will increase capacity to 4500 wafers/week by the end of 2014. (Photo credit: Artechnic)

ASN: Let’s talk about the Crolles fab for a minute. Although it may be considered small compared to the big pure-play foundries, some aspects you share with the big foundries – like a large mix of product and advanced automation, right?

JMC: Crolles’ technology mix encompasses Advanced CMOS 28/40 nm, Imaging Sensors, embedded Non Volatile Memories starting at 55nm for Microcontroller and Analog on CMOS 110nm. This mix optimizes very well the accumulated assets we have invested in this Fab toward 4500 wafers week capacity over the next two years.

ASN: How do you see the impact of STMicroelectronics’s decision on the industry? Do you expect others to follow? Will other companies be able to leverage your technology at your foundry partners?

JMC: We would like very much for others to follow us. Through GlobalFoundries, ST is making its FD-SOI technology available to anyone in the microelectronics industry. The ST wide set of silicon-proven 28nm foundation libraries and IPs, encompassing not only basic libraries (std-cells, srams, I/Os) but also complex AMS IPs, is also available to be licensed to those customers aiming for quick access to the technology.


Roundup: FD-SOI, Ecosystem Shine at Semicon West

Tuesday, August 7th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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SOI in general and FD-SOI in particular were hot topics at this year’s Semicon West in San Francisco. A panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry was among the highlights.  It featured an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

  • ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
  • GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
  • IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
  • SOI Industry Consortium: Horacio Mendez – Executive Director
  • Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
  • STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
  • UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI figured prominently in a panel on mobile challenges held during Semicon West '12. Left to right: C. Hu (UCBerkeley); R. Moore (ARM); H. Mendez (SOI Consortium); G. Patton (IBM); P. Magarshack (ST); S. Kengeri (GF); S. Longoria (Soitec)

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs (where in the past it was CPUs) and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out products based on ultra-thin layers of both SOI and insulator, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm this summer.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FD-SOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show for the SOI ecosystem, full of energy and renewed enthusiasm.


Leti Looks at Using Strain with FD-SOI for High-Perf Apps

Friday, June 29th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The researchers at Leti working on FD-SOI have extremely deep expertise in it. One of the areas they’ve looked at is performance boosters. With the interest in FD-SOI rapidly increasing on the heels of the recent ST-GF announcement, their work becomes even more timely.

A key Leti team wrote a summary of some recent strain work, which first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  In case you missed it there, here it is again.


Leti: Adding Strain to FD-SOI for 20nm and Beyond

By Olivier FAYNOT, Microelectronic Section Manager, and Francois ANDRIEU, senior research engineer at CEA-LETI.

The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.

Figure 1: Stressor options for FD-SOI technology

As illustrated in Figure 1, strain can be incorporated at various places in the transistor:

  • In the channel through the use of c-SiGe for PMOS devices and strained SOI (sSOI) material for NMOS.
  • In the source and drain region with the use of SiGe or SiC for P and NMOS respectively.
  • In the Middle-of-Line process with the deposition of tensile or compressive Contact Etch Stop Layers (t- or c-CESL).

First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si[1].

We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.

For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors[2] [1]. Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL[3] for NMOS and with rotated substrates[2], e-SiGe[4], SiGe channels[5] and (110) substrates[6] for pMOS.

For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost[1] and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel)[4]. Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).

Figure 2: Efficiency of stressor techniques for N & PMOS

In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.

NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at

- – – – -


[1] C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu, T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.

[2] S. Baudot, F. Andrieu, O. Faynot, J. Eymery, “Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator (sSOI)”, Solid State Electronics, 2010.

[3] F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, “Ultrathin Body and BOX SOI and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.

[4] S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, “Fully-Depleted Strained Silicon-On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.

[5] F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger, A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.

[6] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.

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