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GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

Monday, October 5th, 2015

By Adele HARS

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

Peregrine BSOS RF Chip in Samsung Galaxy S4 LTE-A – That’s SOI!

Thursday, October 10th, 2013

Peregrine has announced that the company’s new UltraCMOS antenna switch is driving RF performance in the Samsung Galaxy S4 LTE-A smartphone.

UltraCMOS technology is an advanced RF SOI process leveraging bonded silicon-on-sapphire (BSOS) substrates from Soitec. The new dual SP7T Multiswitch in the Samsung leverages Peregrine’s latest version of its UltraCMOS® process technologySTeP8 for RF Front End ICs.

The PE421280 MultiSwitch solves complex carrier aggregation challenges, says Peregrine. Samsung chose it for its ability to support simultaneous multi-band operation of up to 14 frequency bands while delivering exceptional linearity, insertion loss performance and small size.

With Peregrine Semi’s main antenna switch on BSOS substrates from Soitec, the Samsung Galaxy S4 LTE-A smartphone can support 14 frequency bands simultaneously, for a three-fold improvement in download times. (Image courtesy Samsung)

The Samsung Galaxy S4 marks the first implementation on the 4G LTE-A network. The LTE-A protocol uses carrier aggregation – or the simultaneous reception of multiple frequency bands – to improve data throughput. According to Samsung, a three-minute download over 4G LTE would only take about one minute on 4G LTE-A.

“The data throughput enabled by LTE-A dramatically improves the wireless experience, and we are pleased to support a leader like Samsung in delivering this technology to consumers,” said Jim Cable, CEO of Peregrine Semiconductor. “Peregrine’s MultiSwitch devices are designed specifically to solve the challenges of carrier aggregation as used in LTE-A platforms. Based on our UltraCMOS technology, the devices feature not only the linearity required for simultaneous, multi-band switching performance, but also the integration, low power, and manufacturability required of high-volume consumer applications.”

(Image courtesy Peregrine Semiconductor)

High linearity and isolation performance are critical to ensure that radio signals don’t spill into other bands during multi-band operation.

As you may have seen in the ASN Buzz in recent months, this announcement about the Samsung phone is latest in a steady stream of product announcements and design wins (others include LG and Pantech) from Peregrine leveraging the latest UltraCMOS technology.

Another recent announcement concerns the PE42423 RF Switch, which the company says is the highest isolation, carrier-grade Wi-Fi switch, delivering delivers 50 times more isolation and 10 times better linearity for 802.11ac Wi-Fi access points.

If you’d like to understand more of the technology details, Peregrine did an excellent article for ASN last spring, clearly explaining the use of sapphire as a highly insulating substrate for RF SOI CMOS processing. As stated there, “Peregrine Semiconductor’s UltraCMOS technology involves combining silicon with the highly-insulating substrate without incurring major defects, resulting in a highly-manufacturable semiconductor process. This process can be implemented in any standard CMOS foundry, leveraging existing CMOS capacity and avoiding substantial investment.”

The UltraCMOS process, an advanced form of RF SOI technology, can be implemented in any standard CMOS foundry. (Image courtesy Peregrine Semiconductor)

The article concludes, “STeP10 devices are currently in laboratory evaluation and the results look promising to follow this path, with no foreseen limits to advancing the technology further. ”

That’s SOI in action!

Over 65% Smartphone RF Switches SOI, Says Yole; Power Amps Next

Wednesday, August 14th, 2013

By Adele Hars, Editor-in-Chief, Advanced Substrate News

The industry research firm Yole Développement says that more than 65 percent of substrates used in fabricating switches for handsets are SOI-based. This is a high-growth part of the market, putting up double-digit increases.

Like a standard SOI wafer, an RF SOI substrate has an active (“top”) layer on which CMOS transistors are built, with an isolating (“BOx”) layer under it.  The main difference is that the bottom “base” layer under the layer of isolation is a high-resistivity material. This reduces noise and interference, which helps the finished die reach its target performance in terms of signal integrity, handling RF power and integration density. SOI-based devices can reach a figure of merit for on-series resistance and off-equivalent capacitance (Ron.Coff ) below 200 fs (femtoseconds) with potential for further reduction. This directly relates to improved device performance and smaller die size.

At Semicon West SOI wafer manufacturer Soitec announced that its SOI technologies are now mainstream for manufacturing switches and antenna-tuners, key RF components for cell phones and tablets.

There are also new challenges as the industry moves from from 3G to 4G/LTE and further LTE Advanced using carrier aggregation. With SOI, designers can beat the demanding linearity requirements such as intermodulation distortion (IMD), going far beyond -110 dBm, thereby helping avoid interference between networks, says Soitec.

“RF SOI technologies enable the device integration, cost effectiveness and high performance needed for high-volume 3G and LTE applications,” explains Bernard Aspar, vice president, Communication & Power Business Unit at Soitec. “RF, with over 100 percent revenue growth last year, remains a strategic market in which we have been continuously investing for more than a decade.”

Aspar says that as the leading supplier of engineered wafers, Soitec is looking to catch the next growth wave in the RF market.

Based on recent demonstrations, Soitec sees power amplifiers as likely be the next RF components based on SOI. The technology enables highly tunable amplifiers to address multi-region requirements on a single platform. The RF SOI substrates also offer a path towards further integration, such as more mixed-signal and digital content.

Soitec explains that its approach is to offer a wide choice of engineered substrates, so that RF device manufacturers can choose the solution that aligns best with their market strategies – from low-cost GSM handsets to multi-band, multi-mode LTE smartphones and tablets.

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Over 50% Of Smart Phones And Tablets Leverage SOI

Monday, March 18th, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In a recent press release, the SOI wafer leader Soitec said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. 50%? That’s a lot! How do they figure that? The answer: RF.

As seen here, RF chips account for a large part of cellphone components. (Source: Soitec & UCL, ESSDERC ’12 RF Workshop)

With all the talk right now about FD-SOI for application processors, the importance of the RF chips might seem to get a little lost. Don’t expect that to last.

Soitec’s wafer shipments for RF apps have increased by 400 percent in the last two years. In their current fiscal year (which ends this month), the company says it will have shipped over 200,000 engineered wafers to customers making chips for mobile comm. Those wafers translate into about 2.5 billion ICs for RF front-end module apps, which covers half of the 600 million smart phones and 100 million tablets expected to be produced this year.

Soitec, of course, does several flavors of SOI (including bonded silicon-on-sapphire aka BSOS, and high-resistivity (HR) SOI, which Soitec markets as their Wave SOI™ product line) as well as epitaxial GaAs wafers. It all adds up.

If app chips are the heart of the smartphone, RF is the soul. But in terms of chips and substrates, the RF side of the mobile world is much more complicated than the app side. Different functions have different needs, and those needs have traditionally been best met by disparate starting substrates. Devices can have eight of more chips and modules, and the chips in any given set can have different starting substrates, depending on the critical parameters.

The advent of LTE – “long-term evolution” aka 4G – will have a phenomenal impact on the RF components market, with analysts looking for RF components to almost double in value over the next five years. Look for an alphabet soup of new chip modules designed to handle the enormous complexity of evermore frequency bands.

Front-end modules (FEMs), which handle the back-and-forth of signals between the transceiver and the antenna, already contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. With FEM real-estate reduction tracking at 15%/year and market growth continuing to increase at 15%/year for at least another five years, the quest is on for better, cheaper FEM solutions. Some are targeting SoCs, some will be multi-chip modules.

(Source: Soitec & UCL, ESSDERC ’12 RF Workshop)

A couple years ago, Soitec put together a really useful white paper on substrate technologies for RF. You can see, for example, that in choosing a substrate for switches, linear resistivity is the key parameter. This is something that can be addressed by several substrates, including GaAs, SoS and HR-SOI: the deciding factors are the trade-offs between performance and cost.

(Source: Soitec & UCL, ESSDERC ’12 RF Workshop)

There are huge opportunities in RF for the greater SOI & engineered substrates communities, so in coming issues of ASN, this is a topic we’ll be covering more. Upcoming articles by Professor Jean-Pierre Raskin of UCL (his group is working on a new generation of HR-SOI with enhanced signal integrity), as well as Peregrine and Skyworks, among others, are in the works.

Stay tuned!

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Wafer Leaders Extend Basis for Global SOI Supply

Tuesday, October 16th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.

SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.

With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.

As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”

SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”

Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.

SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.

With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”

As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”


The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.

The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers.  What’s more, SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.

So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.

This illustration shows how Smart Cut, Soitec’s proprietary engineered wafer technology, works. The industry standard, this revolutionary wafer bonding and layer splitting processes makes it possible to transfer a thin layer of material from a donor substrate to another substrate, overcoming physical limitations and changing the face of the substrate industry. The Smart Cut technology was originally developed by the CEA-Leti. Soitec holds exclusive exploitation of CEA-Leti rights into the Smart Cut technology, including the right to sublicense to SEH. The technology was made viable for SOI high-volume commercial production by Soitec, and is now protected by more than 3,000 patents owned or controlled by Soitec.

ST’s FD-SOI Tech Available to All Through GF

Monday, October 8th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics (Photo credit: Artechnic)

Advanced Substrate News (ASN): You taped out ST-Ericsson’s 28nm FD-SOI NovaThor in the beginning of September. Did that go as you expected?

Jean-Marc Chery, STMicroelectronics (JMC): 28nm FD-SOI is a pretty exciting technology, allowing better design optimization (for higher speed and power efficiency) than traditional bulk technologies, still reusing most of manufacturing bricks of planar 28nm LP technology and the same design flow and methodology.

Adoption of 28nm FD-SOI for ST-Ericsson’s NovaThor has not introduced any major difficulty in its design, and the FD-SOI version has been taped out shortly after the Low-Power bulk version. Of course special care has been dedicated to further optimize power, exploiting FD-SOI exceptional flexibility and low-power capabilities.

On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.

ASN: Can you talk about the results you expect to see or have seen in the chip? Is there anything about it, or perhaps about the ARM core in particular, that makes it especially well-suited to FD-SOI? Is there anything about the transistor back-biasing capability (which enables significant performance enhancements and power optimization) in the design that makes it challenging to manufacture?

JMC: The wide supply range (ranging from 1.2V down to 0.6V) with excellent performance, and extended back-biasing capability (allowing dynamic modulation of the transistor threshold voltage) offered by 28nm FD-SOI technology have allowed us to exploit the ARM implementation to offer an improved maximum frequency and reach an overall power reduction for the various operating modes of the SoC.

About back biasing, this is a standard feature of FD-SOI technology with no particular challenges for manufacturing. Of course, its dynamic usage to optimize operating points for power (or speed) requires an appropriate device architecture to fully benefit from it.

ASN: In the press, STMicroelectronics has indicated that the 28nm FD-SOI has better power and performance than the industry’s first-gen bulk 22nm FinFETs. Would you say that your choice of FD-SOI puts you in a position of strength, in that you’ll have the mobile industry’s leading technology for 28nm and a choice of mature technologies at 14nm?

JMC: 28nm FD-SOI technology is a unique offer in the SOC industry, allowing the introduction of a fully-depleted technology with a low-cost solution and in a timely manner.

28nm FD-SOI is a planar technology derived from 28nm LP bulk technology, with the same design rules and allowing direct layout reuse (or simplified porting) of basic building blocks and IPs, benefiting from inheriting their maturity level. Also on the manufacturing side, 28nm FD-SOI technology uses the same equipment as Low Power bulk CMOS in a simplified process flow. In ST/Crolles facility we are reaching yield levels comparable to 28nm LP bulk ones, proving that FD-SOI process does not introduce major yield detractors.

A smooth library and IP migration flow coupled with rapid availability for manufacturing is driving the success of this 28nm technology.

Looking at the technology roadmap, the same incremental step for the 14nm node is under development and is on track.

The STMicroelectronics fab in Crolles, France. (Photo credit: Artechnic)

ASN: The plan was to start production in your fab in Crolles, then shift to GlobalFoundries for high-volume production in 2013 — is this still the schedule? From a manufacturing standpoint, what does it take to get a fab ready for FD-SOI production (does it take much longer than a typical bulk scaling transition)? Are there any special tools or other preparations needed?

JMC: For manufacturing, 28nm FD-SOI technology uses the same toolset as for 28nm LP bulk. Process development is complete, and ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other.

Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013.

The ST Crolles fab is highly automated, and already runs a broad mix of products in addition to the new FD-SOI chips. The accumulated assets the company has invested in this fab will increase capacity to 4500 wafers/week by the end of 2014. (Photo credit: Artechnic)

ASN: Let’s talk about the Crolles fab for a minute. Although it may be considered small compared to the big pure-play foundries, some aspects you share with the big foundries – like a large mix of product and advanced automation, right?

JMC: Crolles’ technology mix encompasses Advanced CMOS 28/40 nm, Imaging Sensors, embedded Non Volatile Memories starting at 55nm for Microcontroller and Analog on CMOS 110nm. This mix optimizes very well the accumulated assets we have invested in this Fab toward 4500 wafers week capacity over the next two years.

ASN: How do you see the impact of STMicroelectronics’s decision on the industry? Do you expect others to follow? Will other companies be able to leverage your technology at your foundry partners?

JMC: We would like very much for others to follow us. Through GlobalFoundries, ST is making its FD-SOI technology available to anyone in the microelectronics industry. The ST wide set of silicon-proven 28nm foundation libraries and IPs, encompassing not only basic libraries (std-cells, srams, I/Os) but also complex AMS IPs, is also available to be licensed to those customers aiming for quick access to the technology.


What’s ST’s FD-SOI Technology All About?

Friday, June 22nd, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices.  ST will also open access to its FD-SOI technology to GlobalFoundries’ other customers.  High-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Prior to the announcement, the STM published a white paper explaining why they were forging ahead on FD-SOI.  It’s an excellent paper, providing benchmarks and design considerations.

As they explained in the Executive Summary: “Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too. At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer. Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments.”

With the ST/GF news that other GF customers will have access to the ST technology, those in the fabless community will no doubt be wanting to learn more about what’s on offer.  If you have time, you can download the entire ST white paper from the SOI Consortium: Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond.

The ST team that wrote it also wrote a summary version, which first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  In case you missed it there, here it is again.


ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

By Philippe FLATRESSE, Program Manager for Fully Depleted SOI Technology, STMicroelectronics; Giorgio CESANA, Director of Technology Marketing at STMicroelectronics; and Xavier CAUCHY, Digital Applications and Strategic Marketing Manager at Soitec.

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section)

Technology overview:

  • Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

  • For the 28nm node, the selected BOX thickness is 25nm.

  • Ultra-thin BOX advantages include:

    - further improved electrostatic control and relaxed thinness requirement of the top silicon,

    - enables back-biasing through the BOX,

    - enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

    - brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

  • BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)

Excellent speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)

Focus on SRAM: The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline

SPICE Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.


28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.

ST-Ericsson 28nm FD-SOI smartphone SOC, Q3 tape-out (interview)

Tuesday, April 24th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News


ASN recently had a chance to talk to ST-Ericsson’s Chief Chip Architect Louis Tannyeres  about the move to 28nm FD-SOI for smartphones and tablet SOCs.  Take-away message:  FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm. Here’s what he said.

Louis Tannyeres, Principal Fellow, Chief Chip Architect and head of System Silicon Development at ST-Ericsson.

Advanced Substrate News (ASN): Can you give us a bit of background on the markets you’re addressing?

Louis Tannyeres (LT): Founded in 2009, ST-Ericsson is an industry leader in design, development and creation of cutting edge mobile platforms and semiconductors across the broad spectrum of wireless technologies.  Today, we are actively engaged with seven of the top nine mobile device OEM manufacturers by revenue.

ST-Ericsson’s portfolio covers all market segments, with an emphasis on mid to high-range smartphones and tablets.

ASN: What are the challenges that the product designers (your clients) face with respect to available technology vs. consumer expectations?

LT: With the recent evolution in smartphone capabilities consumer expectations are rising fast. Ultra-fast multicore Gigahertz processors, stunning 3D graphics, full HD multimedia and high-speed broadband connectivity have become the norm for high-end devices.

Consumers expect these features to be delivered in a device that is slim, light and can last for at least as long as their previous phones did. For our customers, the product designers, this translates into requirements for delivering high performance at low power in a cost effective manner.  FD-SOI is a technology that addresses exactly these requirements.

ASN: What advantages do you expect FD-SOI to bring to the platform?

LT: FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm.

ST-Ericsson's NovaThor™ family is an integrated solution for the mainstream smartphone segment, in which modems and application processors are built into a single piece of silicon. The application engine uses the latest ARM®-based multi-core CPUs optimized to deliver the highest performance and support for advanced 2D & 3D graphics cores.

ASN: How have your customers reacted to this bold move?

LT: True market disruptions are only understood after the fact. We believe FD-SOI is such a disruption and a truely differentiated solution. There is a real opportunity for a FD-SOI 28nm solution and then 20nm as a key technology differentiator.  Our customers have reacted  favorably to hearing that we will be enabling FD-SOI technology in our next generation of products. And since we are enabling this technology in STMicroelectronics’ foundries, we have also minimized our risk with respect to market adoption trends.

ASN: How difficult was it to port the existing design from bulk to FD-SOI?

LT: FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. Thanks to fully depleted devices, FD-SOI allows operating at fast speed at extremely low operating voltages – a key characteristic to allow low power operation for mobile devices.

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models. Only a limited number of critical IPs need to be tuned or redesigned.

ASN: What was the impact on design flow?

LT: The equations describing the electrical behavior of fully depleted transistors are different from those used for conventional bulk CMOS, so designing on planar FD requires specific extraction deck and SPICE models. The model we use is now integrated in all major commercially available simulators.  Apart from that, the design flows, methodologies and tools do not need any specific adaptations.

ASN: Do you foresee any major challenges in fast-ramping to high volumes?

LT: 28nm planar FD manufacturing technology has a lot of commonalities with traditional 28nm Low-Power CMOS technology and STMicroelectronics’ strategy has been to reuse as much as possible the 28nm low-power bulk CMOS process. The Back-End part of the process is a direct copy of the 28nm bulk technology. The Front-End part of the process also relies in majority on a direct re-use of equivalent process modules from the bulk technology. Only a few steps have been optimized, added or removed. Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) has 80% in common with that same process.

ASN: When do you expect to have the first prototypes available?

LT: FD-SOI will be introduced into next generation products from ST-Ericsson. At this time, our first 28nm FD-SOI products are scheduled to tape out in Q3 2012 with production start anticipated in 2013.

Louis Tannyeres, Principal Fellow, Chief Chip Architect and head of System Silicon Development at ST-Ericsson, has 30 years of experience in wireless communications and semiconductors. He was TI Senior Fellow at Texas Instruments, where he architected and designed the world’s first digital baseband SoC integrating a DSP core, a microcontroller and  ASIC on a single die.


ST-Ericsson NovaThor This Year, 28nm FDSOI, Soitec Wafers

Wednesday, March 14th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News


Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson’s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry’s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers.

Soitec has just issued an official press release, but ST-Ericsson President-CEO Didier Lamouche had already heralded the news to analysts at the Barcelona Mobile World Congress last month. (You can see/hear the presentation here.)

His Slide 29 from the Barcelona event pretty much says is it all:

Slide 29 from ST-Ericsson’s Analysts & Media Briefing at Mobile World Congress in Barcelona (28 February 2012)

This architecture is essential in implementing transistor technology that solves – with less process complexity – the scaling, leakage and variability issues that are associated with shrinking CMOS technology from 28nm to 14nm.

ST-Ericsson’s planar FD-SOI technology is supplied by STMicroelectronics.  As Lamouche said in his presentation, “The world needs to go fully-depleted.” Choosing this flavor of fully-depleted, planar SOI technology (as opposed to a 3D fully-depleted technology such as FinFETs) puts ST-Ericsson a full two-years ahead of the competition, he estimates.

With the NovaThor platform, ST-Ericsson’s been wracking up some nice wins lately – with Samsung, Nokia and Sony, to name a few. So this is a high-volume endeavor.

Wafer manufacturer Soitec has been working on these wafers with key partners for years. The wafers for planar FD-SOI require an extremely thin and incredibly uniform (+/- 5 Angstroms!) layer of silicon on top of a very thin layer of insulating buried oxide (BOX). Soitec sells them under the banner “FD-2D”; they’re now ready to roll in volume.

“We are positioned to provide the volume of qualified wafer manufacturing required to enable the industry to speed the adoption of planar fully depleted technology into mainstream mobile applications,” says Soitec COO Paul Boudre.

In case you missed it, STM went into significant detail on the advantages of the technology and announced a 28nm product line at the SOI Consortium’s recent FD-SOI workshop (see Important News Comes Out of Recent FD-SOI Workshop in ASN online).

The key planar FD-SOI advantages cited by ST-Ericsson include:

  • a fully-depleted architecture that is cost-competitive with bulk
  • simplified processing (10 percent few steps)
  • 35 percent lower power consumption at maximum performance
  • big performance boost – double (!) when supply voltage is at 0.6V
  • designers can leverage powerful back-biasing techniques to further boost performance or lower power
  • it’s processed with standard fab tools

(Look for more about these and other features in a soon-to-be-published white paper.)

Key Quotes

From the Soitec announcement, here are the key quotes from the parties involved:

ST-Ericsson’s chief chip architect Louis Tannyeres: “Next-generation mobile consumer devices will need to deliver an even better user experience and higher performance without sacrificing battery life. Together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with ST on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions.”

STMicroelectronics’ assistant general manager, Technology R&D, Joël Hartmann: “STMicroelectronics and its partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology, and ST has recently demonstrated the strong differentiation of  this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28nm and below.  This combination makes FD-SOI particularly suitable for wireless and tablet applications where it essentially provides the fully depleted transistor benefits of FinFETs on a planar conventional technology, while allowing advanced back bias techniques, which are not available with FinFETs. We are delighted that it could be adopted by ST-Ericsson for their next generation of products.”

Soitec’s COO, Paul Boudre: “FD provides a low-risk option for semiconductor companies such as ST-Ericsson that are seeking to take advantage of the benefits of a fully depleted transistor architecture while leveraging existing design and manufacturing capabilities.”

Clearly this is a very significant and exciting moment for the industry. It’s the first major fully-depleted announcement since Intel/FinFETs. Might it be the first shot across the bow in the next round of the transistor wars?


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