Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.

Subi Kengeri, VP Advanced Technology Architecture, GlobalFoundries

What do you see as the FD-SOI benefits for chip designers?

• Lower SRAM Vmin for retention and lower operating Vmin for Logic
• Wider range of Voltage operation for performance/power trade-off
• Total dielectric isolation equates to lower capacitances, lower leakage, and latch-up immunity
• Ultra-thin silicon film provides excellent electrostatic control and optimum transistor performance
• Back-bias control gives an additional speed boost
• Simple planar process using same front end and back end as our 28SLP process, which means fewer process steps and fewer masks, helping to absorb the additional substrate cost

What are your plans for making FD-SOI available to your customers?

We are the manufacturing partner for ST’s FD-SOI technology. We also are planning to offer the technology to other customers who may be interested, but we have not announced details yet. We are the only pure-play foundry with deep experience in both bulk and SOI technologies, which allows us to offer a broader range of technologies at advanced nodes.

GlobalFoundries’ Fab 8 in upstate NY

Can you elaborate on the “maximum” version of FD-SOI — tuned for specific applications — what sorts of things would those be?

Examples of features in the Maximum version of FD-SOI:
a. Back-bias capability on logic for higher performance
b. Denser SRAM by taking advantage of lesser variability of Fully depleted device
c. Base Vts tuned for specific applications (performance vs power trade-off)

And the “minimum” version — a simple and “out of the box” FD-SOI technology — who/what is this for?

a. No Back-bias supported
b. All SRAMs are foot-print compatible to 28SLP
c. Fully depleted device offers better Vmin and power advantages: Optimized for Mobile Applications

Are there any special logistics in terms of the PDK, IP, etc?

a. PDKs are similar to bulk CMOS, except the models will support a 4-terminal device for Back-bias
b. In the base version (termed as minimum version above), IP’s Physicals are fully compatible with bulk CMOS, but would require electrical re-characterization to take advantage of improved FD-SOI device characteristics
c. In the extended version (termed maximum version above), IPs will be designed to take advantage of Back-bias for better performance/power trade-offs in specific applications

What is the next node, and when will that roll out?

See slide 8 of [this] presentation:

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here to register and watch it yourself).

The Common Platform Alliance is IBM, Samsung and GlobalFoundries, operating, as IBM’s Dr. Gary Patton points out, as a “virtual IDM”.

Here’s a round-up of the SOI-based highlights.

DR. GARY PATTON, VICE PRESIDENT OF SEMICONDUCTOR RESEARCH & DEVELOPMENT CENTER, IBM

In his keynote address, Gary covered the following SOI-based innovations:

Flexible computing with FD-SOI. (Courtesy: IBM, Common Platform Technology Forum 2013)

• FinFETs: As ASN readers know, IBM is driving FinFETs very hard. With ARM & Cadence, they taped out their first 14nm FinFET processor last fall (on SOI). Gary’s talk gave an overview of the evolution of device structures, including PD-SOI (the basis for IBM’s Watson supercomputer), FD-SOI, FinFETs and future structures and materials.

• Wearable electronics & folding displays – IBM has developed a new, low-cost technique that starts with the FD-SOI technology developed with ST and Leti, for manufacturing silicon-based electronics on a flexible, plastic substrate. Gary showed a sample, and said that “research suggests that flexible, affordable electronics can be made with conventional processes at room temperature.”

• Silicon nanophotonics – most all of the industry’s nanophotonics work is on SOI, and IBM is no exception here.  As Gary notes, “…the key innovation isn’t just the technology…it’s the fact that it’s commercial and scalable…”.
• Carbon nanotubes breakthrough – IBM has attained 10,000 working nanotube transistors on a single device using standard semiconductor processes.  As we noted in ASN when this news broke last fall, IBM researchers fabricated trenches made of hafnium oxide onto SOI wafers, which allows the self-assembly by the carbon nanotubes into neat rows rather than a spaghetti-like tangle.

As seen here, carbon nanotubes start on an SOI wafer. (Courtesy:IBM, Common Platform Technology Platform 2013)

MIKE NOONEN, EXECUTIVE VP, GLOBAL SALES, MARKETING, QUALITY & DESIGN, GLOBALFOUNDRIES.

In Mike’s keynote on particularly innovative customers, he covered ST’s FD-SOI technology.  Here are the main points he made about it:

• STMicroelectronics has been a partner in the Common Platform.
• FD-SOI leverages 80% FEOL of the 28nm SLP; the BEOL is identical to 28nm LP.
• “You can really dial-in optimal transistor performance,” he said.  The thin silicon channel introduces “interesting and exciting capabilities”, including:
  - lower leakage, lower capacitance, enhanced latch-up immunity, electrostatic control;
  - speed boost through back biasing;
• This technology is a simpler planar process:
  - reduced masks offsets cost;
  - considerable IP reuse.
• With a nod to Soitec, the world-leader in SOI wafers, he said, “Soitec has been a really enthusiastic evangelist of this technology, and I really want to acknowledge their efforts in making Fully-Depleted over SOI something that the industry has become very excited about.”  He added that they’re joined by MEMC and SEH as SOI substrate suppliers.
• Regarding the roll-out, he concluded, “A PDK of this technology is available this quarter, and GlobalFoundries has partnered with ST for volume manufacturing and will be entering risk production in the 4th quarter of 2013, with volume production in the first half of 2014.”

GlobalFoundries’ keynote highlights FD-SOI. (Courtesy: GlobalFoundries, STMicroelectronics, Common Platform Technology Forum 2013)

HANDEL JONES, OWNER & CEO, INTERNATIONAL BUSINESS STRATEGIES

In a “fireside chat” with Brian Fuller, Silicon Valley Bureau Chief, EETimes, Handel Jones touched on a number of SOI-related topics.  (In case you missed it, Handel recently wrote an excellent article for ASN on FD-SOI vs. Bulk & FinFET economics.) In addition to his general discourse on the impact of design & process issues on cost/gate, the importance of the ecosystem, and general industry outlook, here are some of Handel’s SOI-related observations during the forum chat:

• RF: he is particularly impressed with IBM’s work on RF, which he says is “…doing extremely well.”  As you may have seen previously in ASN, IBM’s CMOS 7RF SOI technology, which the company says offers significant cost advantages to designers of mobile handsets, has been on SOI for over five years.
• FD-SOI: When asked about any single, major disruption on the horizon, he noted that designing with FinFETs for mixed signal is tough, so there may be a delay there.  However, FD-SOI looks very positive, he says. He sees FD-SOI offering lower power, lower cost/gate, re-usable IP and scalability to 14nm.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013.

And it’s a game changer – for users, for designers, for foundries, and for bean counters.  Here’s why.

The NovaThor L8580 integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

ST-Ericsson’s NovaThor(TM) L8580 on ST’s 28nm FD-SOI features a 2.5Ghz eQuad(TM) app processor with ultra-low power consumption. (Courtesy: ST-Ericsson)

In the eQuad CPU architecture, each processor core can operate as a high-performance core or a very-low-power core, depending on what’s needed at the moment. Since all the eQuad cores can adapt to the needs of the user at any given time, there’s no need for the dedicated low-power cores found in other multi-core CPU architectures. Remember, the 2.5GHz cores in the L8580 are the mobile industry’s fastest, or conversely, at 0.6V in low-power mode, the industry’s most battery-friendly. With all 2.5GHz cores working together, expect blazing high-performance when you’re doing something like browsing the web. But when phone’s your pocket, those cores will take barely a sip of power.

The NovaThor L8580 is essentially a straight port from 28nm bulk to 28nm FD-SOI of the (very successful) NovaThor L8540, with just a bit of tweaking to fully leverage cool things you can do with FD-SOI, like biasing to increase performance and conserve power.

For the folks designing smartphones and tablets (and ultimately for the end-user), that port to FD-SOI gets the NovaThor L8580:

• CPUs running 35% faster and GPU and multimedia accelerators running 20% faster. In terms of multimedia performance, they’re supporting 1080p video encoding and playback at up to 60 frames per second, 1080p 3D camcorder functionality, displays up to WUXGA (1920×1200) at 60 frames per second and cameras up to 20 megapixels. (Hence their use of the descriptive “extraordinary”.)
• 25% less power consumption than rival architectures when running at high-performance  levels – think Cooler Operation.
• A low-power mode can deliver up to 5000 DMIPS at 0.6V – more than enough computing power for the majority of applications in everyday use. A key point here is that it enables stable SRAM operation at 0.6V – have you heard of anyone matching this? The result is that this low-power mode consumes 50% less power to deliver the same performance compared with alternative solutions in bulk CMOS.

It all adds up to big battery savings – this is the extra day CEO Didier Lamouche promised us in Barcelona last year when they announced this chip.

ST-Ericsson has posted an amazing video, filmed live at CES 13. In the first part of the demo (re: high-perf), on a Samsung Galaxy S3, they’ve got the Sky Castle 3D Graphics Demo launching twice as fast on FD-SOI as the bulk equivalent, and hitting 2.8GHz! And in the second demo (re: low power), they’re hitting 1GHz using just 0.636V, which would take 1.1V on bulk.

Design Highlights

For the ST-E designers, most of the IP blocks were directly re-used from the bulk design, so the porting to FD-SOI was extremely simple and fast.

For the manufacturing folks over at STMicroelectronics (and starting this year, at GloFo), FD-SOI is a planar technology that re-uses 90% of the process steps used in 28nm bulk. The overall manufacturing process in FD-SOI is 12% less complex, so they’ve got lower cycle time and reduced manufacturing costs (bean counters take note, please). They also point out that the manufacturing tools for FD-SOI are much simpler than those required for FinFETs.

Wondering what’s next? The 14nm FD-SOI node is already in development, the ARM Cortex-A15‘s  on the radar, and the FD-SOI roadmap is already defined up the 10nm node.

With FD-SOI, you can do much more with body-biasing (aka back-biasing) than you can in bulk (which suffers from too much leakage). Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel, so it effectively acts like a vertical double gate transistor. This facilitates the flow of electrons, leading to a higher voltage in the body, and faster switching of the transistor. (Image courtesy ST-Ericsson)

With FD-SOI, you can hit higher speeds with lower operating voltages. This is because the buried oxide layer prevents electrons from leaking away as they travel through the channel from the source to the drain (this sort of leakage is a major source of power consumption in 28nm bulk, which depends on doping to handle leakage). Interestingly, this graph shows ST-E going down to 0.5V – which is incredibly impressive. (Image courtesy of ST-Ericsson)

(Image courtesy ST-Ericsson)

(Image courtesy ST-Ericsson)

As the (now award-winning) folks over at ST and Leti described for us a few years ago, designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.  The ST-E designers use this feature to apply different voltages independently to the top and the buried gates of the FD-SOI transistor, which effectively changes its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high-performance transistor to those of a very low-power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power. (You can’t do this with FinFETs, btw.)

Just Posted: FD-SOI video & white paper

Just as this blog was going online, ST-Ericsson posted an excellent, in-depth white paper; and in partnership with STMicroelectroics, a YouTube video detailing the how’s and why’s of FD-SOI.Here are the links — you really don’t want to miss these:

• Multiprocessing in Mobile Platforms: the Marketing and the Reality
In this white paper, ST-Ericsson’s Marco Cornero and Andreas Anyuru “…illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the upcoming ST-Ericsson products.”

• An Introduction to FD-SOI

STMicroelectronics and ST-Ericsson have teamed up on this excellent video, which garnered 1250 views within the first four days of its posting on YouTube. The animations and comparisons highlight why FD-SOI is so fast, and so cool.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics (Photo credit: Artechnic)

Advanced Substrate News (ASN): You taped out ST-Ericsson’s 28nm FD-SOI NovaThor in the beginning of September. Did that go as you expected?

Jean-Marc Chery, STMicroelectronics (JMC): 28nm FD-SOI is a pretty exciting technology, allowing better design optimization (for higher speed and power efficiency) than traditional bulk technologies, still reusing most of manufacturing bricks of planar 28nm LP technology and the same design flow and methodology.

Adoption of 28nm FD-SOI for ST-Ericsson’s NovaThor has not introduced any major difficulty in its design, and the FD-SOI version has been taped out shortly after the Low-Power bulk version. Of course special care has been dedicated to further optimize power, exploiting FD-SOI exceptional flexibility and low-power capabilities.

On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.

ASN: Can you talk about the results you expect to see or have seen in the chip? Is there anything about it, or perhaps about the ARM core in particular, that makes it especially well-suited to FD-SOI? Is there anything about the transistor back-biasing capability (which enables significant performance enhancements and power optimization) in the design that makes it challenging to manufacture?

JMC: The wide supply range (ranging from 1.2V down to 0.6V) with excellent performance, and extended back-biasing capability (allowing dynamic modulation of the transistor threshold voltage) offered by 28nm FD-SOI technology have allowed us to exploit the ARM implementation to offer an improved maximum frequency and reach an overall power reduction for the various operating modes of the SoC.

About back biasing, this is a standard feature of FD-SOI technology with no particular challenges for manufacturing. Of course, its dynamic usage to optimize operating points for power (or speed) requires an appropriate device architecture to fully benefit from it.

ASN: In the press, STMicroelectronics has indicated that the 28nm FD-SOI has better power and performance than the industry’s first-gen bulk 22nm FinFETs. Would you say that your choice of FD-SOI puts you in a position of strength, in that you’ll have the mobile industry’s leading technology for 28nm and a choice of mature technologies at 14nm?

JMC: 28nm FD-SOI technology is a unique offer in the SOC industry, allowing the introduction of a fully-depleted technology with a low-cost solution and in a timely manner.

28nm FD-SOI is a planar technology derived from 28nm LP bulk technology, with the same design rules and allowing direct layout reuse (or simplified porting) of basic building blocks and IPs, benefiting from inheriting their maturity level. Also on the manufacturing side, 28nm FD-SOI technology uses the same equipment as Low Power bulk CMOS in a simplified process flow. In ST/Crolles facility we are reaching yield levels comparable to 28nm LP bulk ones, proving that FD-SOI process does not introduce major yield detractors.

A smooth library and IP migration flow coupled with rapid availability for manufacturing is driving the success of this 28nm technology.

Looking at the technology roadmap, the same incremental step for the 14nm node is under development and is on track.

The STMicroelectronics fab in Crolles, France. (Photo credit: Artechnic)

ASN: The plan was to start production in your fab in Crolles, then shift to GlobalFoundries for high-volume production in 2013 — is this still the schedule? From a manufacturing standpoint, what does it take to get a fab ready for FD-SOI production (does it take much longer than a typical bulk scaling transition)? Are there any special tools or other preparations needed?

JMC: For manufacturing, 28nm FD-SOI technology uses the same toolset as for 28nm LP bulk. Process development is complete, and ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other.

Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013.

The ST Crolles fab is highly automated, and already runs a broad mix of products in addition to the new FD-SOI chips. The accumulated assets the company has invested in this fab will increase capacity to 4500 wafers/week by the end of 2014. (Photo credit: Artechnic)

ASN: Let’s talk about the Crolles fab for a minute. Although it may be considered small compared to the big pure-play foundries, some aspects you share with the big foundries – like a large mix of product and advanced automation, right?

JMC: Crolles’ technology mix encompasses Advanced CMOS 28/40 nm, Imaging Sensors, embedded Non Volatile Memories starting at 55nm for Microcontroller and Analog on CMOS 110nm. This mix optimizes very well the accumulated assets we have invested in this Fab toward 4500 wafers week capacity over the next two years.

ASN: How do you see the impact of STMicroelectronics’s decision on the industry? Do you expect others to follow? Will other companies be able to leverage your technology at your foundry partners?

JMC: We would like very much for others to follow us. Through GlobalFoundries, ST is making its FD-SOI technology available to anyone in the microelectronics industry. The ST wide set of silicon-proven 28nm foundation libraries and IPs, encompassing not only basic libraries (std-cells, srams, I/Os) but also complex AMS IPs, is also available to be licensed to those customers aiming for quick access to the technology.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California. (Photo Credit: Rex Gelert)

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(You can get the pdf of the full program & registration information from the website.)

THE PAPERS

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

1. Plenary: talks by Soitec and ARM
2. Fully-Depleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
10. Hot Topics: Fully-Depleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
11. Late News: tbd, of course…

THE COURSES & PANEL

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively, favorite event. This year’s invited distinguished experts — Scott Luning (GF), Ali Khakifirooz (IBM), Yang Du (Qualcomm). and moderator Sorin Cristoloveanu (Grenoble Institute of Technology) – will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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SOI in general and FD-SOI in particular were hot topics at this year’s Semicon West in San Francisco. A panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry was among the highlights.  It featured an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

• ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
• GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
• IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
• SOI Industry Consortium: Horacio Mendez – Executive Director
• Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
• STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
• UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI figured prominently in a panel on mobile challenges held during Semicon West '12. Left to right: C. Hu (UCBerkeley); R. Moore (ARM); H. Mendez (SOI Consortium); G. Patton (IBM); P. Magarshack (ST); S. Kengeri (GF); S. Longoria (Soitec)

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs (where in the past it was CPUs) and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out products based on ultra-thin layers of both SOI and insulator, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm this summer.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FD-SOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show for the SOI ecosystem, full of energy and renewed enthusiasm.

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Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Two big pieces of news have recently been announced by STMicroelectronics:

1. to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices;
2. ST will open access to its FD-SOI technology to GlobalFoundries’ other customers.

The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Here are other key points from the press release:

• The 28nm FD-SOI generation, currently in the industrialization phase, is scheduled to be available for prototyping by July 2012.
• The next node, the 20nm FD-SOI generation, is currently under development and is scheduled to be ready for prototyping by Q3 2013.

What they’re saying:

Joel Hartmann, STMicroelectronics Corporate VP, Front End Manufacturing and Process R&D, Digital Sector: “FD-SOI is ideally suited for wireless and tablet applications, where it provides fully-depleted transistor benefits using conventional planar technology, and this arrangement with GLOBALFOUNDRIES ensures our customers will have a secure source of supply.”

Philippe Magarshack, STMicroelectronics Corporate VP, Design Enablement and Services: “Porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI is straightforward, and designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to Bulk, due to the absence of MOS-history-effect. In addition, FD-SOI can be used for either extreme performance or very low leakage on the same silicon, by biasing dynamically the substrate of the circuit. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.”

Gregg Bartlett, Chief Technology Officer of GLOBALFOUNDRIES: “We have a longstanding partnership with ST spanning joint R&D and manufacturing, as well as an unmatched heritage of expertise in SOI technology. We’re pleased to be working with ST to bring this next generation of SOI technology to market and enable continued momentum in the mobile revolution.”

While it might seem like all this is happening very fast, ST has been championing FD-SOI technology for about a decade. In fact, one of the company’s top SOI gurus, Advanced Devices Program Director Thomas Skotnicki, first wrote about it for us at Advanced Substrate News back in 2006. And we’ve been covering it regularly ever since.

For an in-depth look at ST’s FD-SOI design and manufacturing strategy and benchmarking results, be sure to check out their white paper. By the way, designers take note: they also indicate in the white paper that the 28nm FD-SOI Process Design Kit (PDK) is available now, targeting risk production by mid-2012. Evaluation SPICE models are now available for the 20nm node, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

For easy access to the dozens of useful and insightful FD-SOI related articles by contributors on the leading-edge that we’ve published over the years, just hit the FD-SOI tag on the ASN website.

Seems like a new door has opened now, doesn’t it?

Fab 8, located in Luther Forest Technology Campus, Saratoga County, New York, USA is GlobalFoundries' new 300 mm Fab dedicated to advanced technologies. Maximum Full Capacity is 60,000 300mm wafers/month. GloFo also runs high-volume SOI at its fabs in Dresden and Singapore (source: Wikipedia).

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications.

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The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.

Armed with the information from the 28nm bulk vs. FD-SOI benchmarking study, the SOI Consortium members then did new benchmark simulations at the 20nm node. This confirmed the trends they saw in silicon at 28nm. When comparing FD-SOI technology to bulk technology specifically intended for System-on-Chip (SOC):

• Peak performance was improved by 12 to 30 percent at constant total power, depending on design optimization efforts,
• Low-Vdd (0.7V) performance was improved by 65 to percent,
• Total power was reduced by 22 to 40 percent at constant maximum operating frequency.

Here’s the graphic that says it all. Follow the suggestions in the annotations to see how the power vs. performance trade-off works.

By adjusting Back Bias, FD can be changed from: High Performance Mode TO Leakage Saving Mode

To use this graph: pick any point on the lower, bulk line, then move horizontally to the left to see how much less power it will take to hit the same frequency with FD-SOI.

(a) Reverse back-bias allows you to cut leakage, here by a factor of 10
(b) This line is 20 nm FD-SOI with back biasing
(c) Or with back-biasing FD-SOI, you can hit over 269 MHZ using 120 mW at 1 V power supply

(1) This line is 20 nm Bulk
(2) This line is 20 nm FD-SOI
(3) Bulk takes over 130 mW to hit frequency of about 223 MHz with supply voltage of 1 V
(4) To hit the same with FD-SOI takes just over 100 mW and a supply voltage of just 0.9 V

(Courtesy: SOI Consortium)

About the study

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this blog.

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications.

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Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technology, and can be on SOI or bulk) and other Multi-gate (MuGFET) devices each having compelling advantages in their favor.

Designers are considering the power and performance needs of their applications, assessing the manufacturing risks and evaluating the importance of extending current IP – which makes FD-SOI a very strong contender for current and upcoming nodes.

The recent SOI Industry Consortium announcement indicated that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.

28nm: FD-SOI saves power, boosts performance

The Consortium benchmarked 28nm bulk vs. 28nm FD-SOI, so they could make comparisons in silicon of representative IP blocks, such as ARM cores and memory controllers. Here are some of the potential implications of what they’re saying.

• Peak performance is comparable with the much leakier ‘General Purpose’ technology flavors, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology flavors achieve.

FD-SOI peak performance is comparable to that of GP, and significantly better than LP (low power) technologies.

The dynamic power gap, however, gets better and better as you can reduce the power supply voltage (i.e. when you’re not shooting for extreme operating frequency) — because the drop in performance when the supply voltage Vdd is lowered is much less marked with a fully-depleted technology.

The trick is, 1) not all portions of an SOC need highest possible performance and 2) even those that do need that performance only a fraction of the time — when running very demanding scenarios.  So when you consider the dynamic power at chip level across use cases, then your overall dynamic power is dramatically better.

This also means, if you have a chip in bulk technology (LP or G)  that runs fine in terms of performance but you’d like to cut its total power, then planar FD-SOI is a great solution.

• The feasibility of running all digital device designs, including SRAMs, at very low Vdd (e.g., 0.6 volt).

One of the great problems of traditional bulk CMOS is that SRAM memories quickly become unstable if their Vdd is reduced.  Being unable to reduce Vdd, you cannot lower their power consumption even when you don’t need maximum access speed from them. By contrast, fully-depleted technologies enable you to operate both logic and SRAM at reduced Vdd.

• The opportunity for substantial power savings of up to 40 percent by using a lower Vdd to reach the same target frequency.

AND

• Much better performance than bulk CMOS when the power supply (Vdd) is lowered. At 0.6V, critical paths on 28nm FD-SOI circuits were more than 50 percent faster than the General Purpose technology and more than twice as fast as Low Power technology;

With respect to dynamic power consumption (the power lost in switching), it’s proportional to the square of Vdd. So if you reduce Vdd and still hit the target frequency, you get a big savings in dynamic power consumption.

Leakage power – AKA static power – is the power lost when sub-threshold currents wander away even when the  transistor is off.  It’s the major cause of wasted power in standby mode.  The Consortium study found that FD-SOI does better than both G and LP bulk technologies at 28nm in terms of leaky transistors.

About the study

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study.  The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this blog. Look for Part 3 of this blog series on the SOI Consortium results soon.

By Adele Hars, Editor-in-Chief, Advanced Substrate News

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking of planar FD-SOI.

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Chipmakers constantly have to manage risk.  Generally it is sensible not to try to engage in more than one major change at a time – geometry shrinks already introduce enough headaches.  So planar FD-SOI devices, which use proven, well-understood design and manufacturing techniques should be particularly appealing for both current and upcoming nodes.

Horacio Mendez, executive director of the SOI Industry Consortium noted that FD-SOI  also represents a low risk in terms of manufacturing for upcoming nodes.

“FD-SOI’s ability to accommodate planar architectures presents much lower manufacturing risk than FinFET,” he said. “This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers.”

For many if not most designers, extending the life of existing planar bulk CMOS designs will make good sense.  With a planar FD-SOI solution, these existing designs and related IP can be migrated in a comparatively straightforward way, producing chips that benefit from the intrinsic advantages of fully depleted wafer technology with minimal risk and lower cost.

(There was an excellent piece in ASN from ARM SOI guru Jean-Luc Pelloie on the logistics and ease of porting from bulk to FD-SOI a few months ago – click here to read it.)

The SOI Consortium also points out that FD-SOI is compatible with all power-reduction techniques used by IC designers – and can even boost the efficiency of some. Furthermore, FD-SOI can accommodate some design tweaks (not available with FinFET designs), such as leveraging dynamic back-bias to increase performance or reduce leakage power in some applications.

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About the study:

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Next –  Part 2 of this blog series on the SOI Consortium study looks at FD-SOI from a power & performance perspective.