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GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

Monday, October 5th, 2015

By Adele HARS

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP

Wednesday, July 17th, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die cost by 30%, while FD-SOI only increases die cost by 10%. (Both HPP and FD-SOI are HKMG/GateFirst).

Moving to 20nm, the graph indicates that FD-SOI gets an additional 25% performance increase: that’s terrific. This slide doesn’t give a performance increase figure for 20LPM, but it’s clearly way below 20nm FD-SOI.

Now there are no actual figures given for die cost at 20nm, but the position on the graph indicates that the shrink to 20nm on FD-SOI costs substantially less than the cost for shrinking on bulk.   Later in the presentation, he indicated that a big part of the savings is in masks – FD-SOI requiring 10 fewer masks than bulk.

Interesting to note the position of 14XM, which is a bulk FinFET. Again, no actual figures are given, but die cost is substantially higher. However the relative performance increase does not appear to be very significant.

The presentation was made during the FD-SOI Workshop following VLSI in Kyoto, Japan. It is available from the SOI Consortium website.

Other presentations

Looking ahead to 14nm FD-SOI for high performance, ST’s  Laurent Le Pailleur showed this interesting slide in his Kyoto Workshop presentation, 28nm FD-SOI Industrial Solution: Overview of Silicon Proven Key Benefits – again, lots of masks saved:

There are other presentations from the Workshop available on the Consortium website, including a terrific short course by David Jacquet of ST entitled Architectural choices & design-implementation methodologies for exploiting extended FD-SOI DVFS & body-bias capabilities.

For those wanting to know more about FinFETs on SOI, Terry Hook of IBM expanded on his excellent ASN article in a presentation entitled Elements for the Next Generation FinFET CMOS Technology. In particular, there are lots of clear explanations about why SOI makes a difference, and the role of wafer-level strain (aka “strained silicon directly on insulator” – which IBM calls SSDOI)  wafers by Soitec.

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VLSI Kyoto – The SOI Papers

Wednesday, June 19th, 2013

By Adele Hars
There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013).

By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all be available on the IEEEXplore website in early July, say the organizers.

Here’s a quick review of the highlights.

PAPERS IN THE JUMBO-JOINT FOCUS SESSIONS

Cross-sectional and plain view of FDSOI SRAM cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage(0.197µm2).

JJ2-3: FDSOI Process/Design full solutions for Ultra Low Leakage, High Speed and Low Voltage SRAMs, R. Ranica et al., STMicroelectronics & CEA-LETI

In this paper from STMicroelectronics and CEA-LETI, six Transistor SRAM (6T- SRAM) cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage (0.197µm2) purposes are fabricated with 28 nm node FDSOI technology for the first time. Starting from a direct porting of bulk planar CMOS design, the improvement in read current Iread has been confirmed up to +50% (@Vdd=1.0V) & +200% (@ Vdd=0.6 V), respectively, compared with 28 nm Low-Power (LP) CMOS technology.Additionally, -100mV minimum operating voltage ( Vmin) reduction has been demonstrated with 28 nm FDSOI technology. Alternative flip-well and single well architecture provides further speed and  Vminimprovement, down to 0.42V on 1Mb 0.197µm2 . Ultimate stand-by leakage below 1pA on 0.120 µm2bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.

JJ1-8: First Demonstration of a Full 28nm High-k/Metal Gate Circuit Transfer from Bulk to UTBB FDSOI Technology Through Hybrid Integration, D. Golanskiet al, ST Microelectronics and CEA-LETI

For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame of our hybrid technology. Competitive ESD performance for the same footprint is achieved through hybrid MOSFETS snap-back voltage reduction, obtained by implant engineering. In addition, we demonstrate that the performance of Silicon Controlled Rectifier (SCR) and ESD diodes are matched vs Bulk technology while maintaining the performance of FDSOI devices and without any additional masks.

JJ1-9: 2.6GHz Ultra-Wide Voltage Range Energy Efficient Dual A9 in 28nm UTBB FD-SOI, D. Jacquet et al. STMicroelectronics

This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to 1.2V, and forward body bias (FBB) techniques up to 1.3V bias voltage, thus enabling an extremely energy efficient implementation.

(Note: ST has indicated that 2.6GHz voltage range in the title dates from the time the paper was submitted earlier this year; the actual presentation will show a more extended range.)

JJ2-1 (Invited): Fully-Depleted Planar Technologies and Static RAM, T. Hook et al, IBM, STMicroelectronics, LETI

Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described.Thick- and thin-Bottom Oxide (BOX) variants are discussed.

JJ2-4: Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias, Y. Yamamoto et al, Low-power Electronics Association & Project (LEAP), The University of Tokyo

We demonstrated record 0.37 V minimum operation voltage (Vmin) of 2Mbit Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to small variability of SOTB (AVT~1.2-1.3 mVμm) and adaptive body biasing (ABB), Vmin was lowered down to ~0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.

(Note: SOTB is a flavor of planar FD-SOI.)

IN THE CIRCUITS SYMPOSIA

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm. (b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

T2-2: High Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant- Free Process and Aggressively-Scaled Fin and Gate Dimensions, P. Hasemi et al., IBM & GlobalFoundries.

The adoption of advanced high-mobility Silicon Germanium (SiGe) channel materials with aggressively scaled Tri-gate pFETs on insulator is reported for the first time. SiGe is widely known as a suitable channel material for p-type MOS device, thanks to its higher hole mobility than that in conventional silicon material. In this paper, IBM and GlobalFoundries report a SiGe channel Tri-gate pFET with aggressively scaled Fin width (Wfin) and Gate length(Lg) dimensions, which is fabricated using SiGe on insulator substrate. Excellent electrostatic control down to Lg= 18 nm and Wfin< 18 nm has been reported. Using an optimized implant-free raised source/drain process, on-current Ion = 1.1 mA/µm at off-leakage current Ioff = 100 nA/µm and supply voltage Vdd= 1.0 V has been achieved.

15-4: A 28GHz Hybrid PLL in 32nm SOI CMOS, M. Ferriss et al, IBM

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140μmx160μm 32μm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply.

21-1: A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32 nm Digital SOI CMOS, L. Kull et al, IBM, EPFL

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time skew minimization and per-channel gain control based on low-power reference voltage buffers. Gain control of each sub-ADC is based on a fine-grain, robust R-3R ladder. The sub-ADC stacks the capacitive SAR DAC with the reference capacitor to reduce the area and enhance the settling speed. The speed and area optimized sub-ADC as well as a short tracking window of 1/8 period enable a low input capacitance and therefore render an input buffer unnecessary. The ADC achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2in 32nm CMOS SOI technology.

21-3: An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI, V.H.-C. Chen and L. Pileggi, Carnegie Mellon University

This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FoM of 59.4fJ/conv-step.

IN THE TECHNOLOGY SYMPOSIA

5-3: Optimal Device Architecture and Hetero-Integration Scheme for III-V CMOS, Z. Yuan et al, Stanford University, Applied Materials, Sematech, Texas State University

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional FinFETs. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

10-1: Benefits of Segmented Si/SiGe p-Channel MOSFETs for Analog/RF Applications, N. Xu et al, University of California, Applied Materials, Soitec

Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future System-on-Chip applications.

14.5: 64nm Pitch Interconnects: Optimized for Designability, Manufacturability and Extendibility, C. Goldberg et al, STMicroelectronics, Samsung Electronics, GlobalFoundries, IBM

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been plugged in to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.

15-1: Innovative Through-Si 3D Lithography for Ultimate Self-Aligned Planar Double-Gate and Gate-All-Around Nanowire Transistors, R. Coquand et al,STMicroelectronics, CEA-LETI, IMEP-LAHC

This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2-Poly-Si gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (ION of 1mA per μm at VT+0.7V) with excellent electrostatics (SS down to 62mV per dec and DIBL below 10mV per V at LG 80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of lowpower SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.

15-3: Scaling of Ω-Gate SOI Nanowire N- and P-FET Down to 10nm Gate Length: Size- and Orientation-Dependent Strain Effects, S. Barraud et al, CEA-LETI, CEA-INAC, STMicroelectronics, IMEP-LAHC

High-performance strained Silicon-On-Insulator nanowires with gate width and length scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (LG=10nm) with an outstanding ION current and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement is achieved using in-situ etching and selective epitaxial growth of boron-doped SiGe for the formation of recessed Sources/ Drains (S/D). We show an ION improvement up to +100% induced by recessed SiGe S/D for LG=13nm P-FET NW. Finally, size- and orientation-dependent strain impact on short channel performances is discussed. <110> Si NWs provide the best opportunities for strain engineering.

17-2 (Late News): Experimental Analysis and Modeling of Self Heating Effect in Dielectric Isolated Planar and Fin Devices, S. Lee et al, IBM

Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design. A quantitative comparison to 45nm planar SOI shows that while the scaled FinFET on dielectric devices show higher normalized thermal resistance, as expected from device scaling, the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits, hence resulting in negligible self heating effect. For cases where the self heating becomes a factor, e.g., in high-speed I/O circuits, the same design methods can be applied for both planar and FinFET devices on dielectric isolation.

—Adele Hars is the editor-in-chief of Advanced Substrate News.

GF’S Two Flavors Of FD-SOI

Wednesday, April 17th, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture.

Subi Kengeri, VP Advanced Technology Architecture, GlobalFoundries

What do you see as the FD-SOI benefits for chip designers?

  • Lower SRAM Vmin for retention and lower operating Vmin for Logic
  • Wider range of Voltage operation for performance/power trade-off
  • Total dielectric isolation equates to lower capacitances, lower leakage, and latch-up immunity
  • Ultra-thin silicon film provides excellent electrostatic control and optimum transistor performance
  • Back-bias control gives an additional speed boost
  • Simple planar process using same front end and back end as our 28SLP process, which means fewer process steps and fewer masks, helping to absorb the additional substrate cost

What are your plans for making FD-SOI available to your customers?

We are the manufacturing partner for ST’s FD-SOI technology. We also are planning to offer the technology to other customers who may be interested, but we have not announced details yet. We are the only pure-play foundry with deep experience in both bulk and SOI technologies, which allows us to offer a broader range of technologies at advanced nodes.

GlobalFoundries’ Fab 8 in upstate NY

Can you elaborate on the “maximum” version of FD-SOI — tuned for specific applications — what sorts of things would those be?

Examples of features in the Maximum version of FD-SOI:
a. Back-bias capability on logic for higher performance
b. Denser SRAM by taking advantage of lesser variability of Fully depleted device
c. Base Vts tuned for specific applications (performance vs power trade-off)

And the “minimum” version — a simple and “out of the box” FD-SOI technology — who/what is this for?

a. No Back-bias supported
b. All SRAMs are foot-print compatible to 28SLP
c. Fully depleted device offers better Vmin and power advantages: Optimized for Mobile Applications

Are there any special logistics in terms of the PDK, IP, etc?

a. PDKs are similar to bulk CMOS, except the models will support a 4-terminal device for Back-bias
b. In the base version (termed as minimum version above), IP’s Physicals are fully compatible with bulk CMOS, but would require electrical re-characterization to take advantage of improved FD-SOI device characteristics
c. In the extended version (termed maximum version above), IPs will be designed to take advantage of Back-bias for better performance/power trade-offs in specific applications

What is the next node, and when will that roll out?

See slide 8 of [this] presentation:

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SOI Highlights at Common Platform Tech Forum

Tuesday, February 19th, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here to register and watch it yourself).

The Common Platform Alliance is IBM, Samsung and GlobalFoundries, operating, as IBM’s Dr. Gary Patton points out, as a “virtual IDM”.

Here’s a round-up of the SOI-based highlights.

DR. GARY PATTON, VICE PRESIDENT OF SEMICONDUCTOR RESEARCH & DEVELOPMENT CENTER, IBM

In his keynote address, Gary covered the following SOI-based innovations:

Flexible computing with FD-SOI. (Courtesy: IBM, Common Platform Technology Forum 2013)

  • FinFETs: As ASN readers know, IBM is driving FinFETs very hard. With ARM & Cadence, they taped out their first 14nm FinFET processor last fall (on SOI). Gary’s talk gave an overview of the evolution of device structures, including PD-SOI (the basis for IBM’s Watson supercomputer), FD-SOI, FinFETs and future structures and materials.
  • Wearable electronics & folding displays – IBM has developed a new, low-cost technique that starts with the FD-SOI technology developed with ST and Leti, for manufacturing silicon-based electronics on a flexible, plastic substrate. Gary showed a sample, and said that “research suggests that flexible, affordable electronics can be made with conventional processes at room temperature.”
  • Silicon nanophotonics – most all of the industry’s nanophotonics work is on SOI, and IBM is no exception here.  As Gary notes, “…the key innovation isn’t just the technology…it’s the fact that it’s commercial and scalable…”.
  • Carbon nanotubes breakthrough – IBM has attained 10,000 working nanotube transistors on a single device using standard semiconductor processes.  As we noted in ASN when this news broke last fall, IBM researchers fabricated trenches made of hafnium oxide onto SOI wafers, which allows the self-assembly by the carbon nanotubes into neat rows rather than a spaghetti-like tangle.

As seen here, carbon nanotubes start on an SOI wafer. (Courtesy:IBM, Common Platform Technology Platform 2013)

MIKE NOONEN, EXECUTIVE VP, GLOBAL SALES, MARKETING, QUALITY & DESIGN, GLOBALFOUNDRIES.

In Mike’s keynote on particularly innovative customers, he covered ST’s FD-SOI technology.  Here are the main points he made about it:

  • STMicroelectronics has been a partner in the Common Platform.
  • FD-SOI leverages 80% FEOL of the 28nm SLP; the BEOL is identical to 28nm LP.
  • “You can really dial-in optimal transistor performance,” he said.  The thin silicon channel introduces “interesting and exciting capabilities”, including:
    - lower leakage, lower capacitance, enhanced latch-up immunity, electrostatic control;
    - speed boost through back biasing;
  • This technology is a simpler planar process:
    - reduced masks offsets cost;
    - considerable IP reuse.
  • With a nod to Soitec, the world-leader in SOI wafers, he said, “Soitec has been a really enthusiastic evangelist of this technology, and I really want to acknowledge their efforts in making Fully-Depleted over SOI something that the industry has become very excited about.”  He added that they’re joined by MEMC and SEH as SOI substrate suppliers.
  • Regarding the roll-out, he concluded, “A PDK of this technology is available this quarter, and GlobalFoundries has partnered with ST for volume manufacturing and will be entering risk production in the 4th quarter of 2013, with volume production in the first half of 2014.”

GlobalFoundries’ keynote highlights FD-SOI. (Courtesy: GlobalFoundries, STMicroelectronics, Common Platform Technology Forum 2013)

HANDEL JONES, OWNER & CEO, INTERNATIONAL BUSINESS STRATEGIES

In a “fireside chat” with Brian Fuller, Silicon Valley Bureau Chief, EETimes, Handel Jones touched on a number of SOI-related topics.  (In case you missed it, Handel recently wrote an excellent article for ASN on FD-SOI vs. Bulk & FinFET economics.) In addition to his general discourse on the impact of design & process issues on cost/gate, the importance of the ecosystem, and general industry outlook, here are some of Handel’s SOI-related observations during the forum chat:

  • RF: he is particularly impressed with IBM’s work on RF, which he says is “…doing extremely well.”  As you may have seen previously in ASN, IBM’s CMOS 7RF SOI technology, which the company says offers significant cost advantages to designers of mobile handsets, has been on SOI for over five years.
  • FD-SOI: When asked about any single, major disruption on the horizon, he noted that designing with FinFETs for mixed signal is tough, so there may be a delay there.  However, FD-SOI looks very positive, he says. He sees FD-SOI offering lower power, lower cost/gate, re-usable IP and scalability to 14nm.

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ST-Ericsson 28nm FD-SOI/ARM Chip Hits 2.8GHz at CES

Tuesday, January 22nd, 2013

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013.

And it’s a game changer – for users, for designers, for foundries, and for bean counters.  Here’s why.

The NovaThor L8580 integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

ST-Ericsson’s NovaThor(TM) L8580 on ST’s 28nm FD-SOI features a 2.5Ghz eQuad(TM) app processor with ultra-low power consumption. (Courtesy: ST-Ericsson)

In the eQuad CPU architecture, each processor core can operate as a high-performance core or a very-low-power core, depending on what’s needed at the moment. Since all the eQuad cores can adapt to the needs of the user at any given time, there’s no need for the dedicated low-power cores found in other multi-core CPU architectures. Remember, the 2.5GHz cores in the L8580 are the mobile industry’s fastest, or conversely, at 0.6V in low-power mode, the industry’s most battery-friendly. With all 2.5GHz cores working together, expect blazing high-performance when you’re doing something like browsing the web. But when phone’s your pocket, those cores will take barely a sip of power.

The NovaThor L8580 is essentially a straight port from 28nm bulk to 28nm FD-SOI of the (very successful) NovaThor L8540, with just a bit of tweaking to fully leverage cool things you can do with FD-SOI, like biasing to increase performance and conserve power.

For the folks designing smartphones and tablets (and ultimately for the end-user), that port to FD-SOI gets the NovaThor L8580:

  • CPUs running 35% faster and GPU and multimedia accelerators running 20% faster. In terms of multimedia performance, they’re supporting 1080p video encoding and playback at up to 60 frames per second, 1080p 3D camcorder functionality, displays up to WUXGA (1920×1200) at 60 frames per second and cameras up to 20 megapixels. (Hence their use of the descriptive “extraordinary”.)
  • 25% less power consumption than rival architectures when running at high-performance  levels – think Cooler Operation.
  • A low-power mode can deliver up to 5000 DMIPS at 0.6V – more than enough computing power for the majority of applications in everyday use. A key point here is that it enables stable SRAM operation at 0.6V – have you heard of anyone matching this? The result is that this low-power mode consumes 50% less power to deliver the same performance compared with alternative solutions in bulk CMOS.

It all adds up to big battery savings – this is the extra day CEO Didier Lamouche promised us in Barcelona last year when they announced this chip.

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ST-Ericsson has posted an amazing video, filmed live at CES 13. In the first part of the demo (re: high-perf), on a Samsung Galaxy S3, they’ve got the Sky Castle 3D Graphics Demo launching twice as fast on FD-SOI as the bulk equivalent, and hitting 2.8GHz! And in the second demo (re: low power), they’re hitting 1GHz using just 0.636V, which would take 1.1V on bulk.

Design Highlights

For the ST-E designers, most of the IP blocks were directly re-used from the bulk design, so the porting to FD-SOI was extremely simple and fast.

For the manufacturing folks over at STMicroelectronics (and starting this year, at GloFo), FD-SOI is a planar technology that re-uses 90% of the process steps used in 28nm bulk. The overall manufacturing process in FD-SOI is 12% less complex, so they’ve got lower cycle time and reduced manufacturing costs (bean counters take note, please). They also point out that the manufacturing tools for FD-SOI are much simpler than those required for FinFETs.

Wondering what’s next? The 14nm FD-SOI node is already in development, the ARM Cortex-A15‘s  on the radar, and the FD-SOI roadmap is already defined up the 10nm node.

With FD-SOI, you can do much more with body-biasing (aka back-biasing) than you can in bulk (which suffers from too much leakage). Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel, so it effectively acts like a vertical double gate transistor. This facilitates the flow of electrons, leading to a higher voltage in the body, and faster switching of the transistor. (Image courtesy ST-Ericsson)

With FD-SOI, you can hit higher speeds with lower operating voltages. This is because the buried oxide layer prevents electrons from leaking away as they travel through the channel from the source to the drain (this sort of leakage is a major source of power consumption in 28nm bulk, which depends on doping to handle leakage). Interestingly, this graph shows ST-E going down to 0.5V – which is incredibly impressive. (Image courtesy of ST-Ericsson)

(Image courtesy ST-Ericsson)

(Image courtesy ST-Ericsson)

As the (now award-winning) folks over at ST and Leti described for us a few years ago, designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.  The ST-E designers use this feature to apply different voltages independently to the top and the buried gates of the FD-SOI transistor, which effectively changes its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high-performance transistor to those of a very low-power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power. (You can’t do this with FinFETs, btw.)

Just Posted: FD-SOI video & white paper

Just as this blog was going online, ST-Ericsson posted an excellent, in-depth white paper; and in partnership with STMicroelectroics, a YouTube video detailing the how’s and why’s of FD-SOI.Here are the links — you really don’t want to miss these:

Multiprocessing in Mobile Platforms: the Marketing and the Reality
In this white paper, ST-Ericsson’s Marco Cornero and Andreas Anyuru “…illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the upcoming ST-Ericsson products.”

An Introduction to FD-SOI
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STMicroelectronics and ST-Ericsson have teamed up on this excellent video, which garnered 1250 views within the first four days of its posting on YouTube. The animations and comparisons highlight why FD-SOI is so fast, and so cool.

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ST’s FD-SOI Tech Available to All Through GF

Monday, October 8th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics (Photo credit: Artechnic)

Advanced Substrate News (ASN): You taped out ST-Ericsson’s 28nm FD-SOI NovaThor in the beginning of September. Did that go as you expected?

Jean-Marc Chery, STMicroelectronics (JMC): 28nm FD-SOI is a pretty exciting technology, allowing better design optimization (for higher speed and power efficiency) than traditional bulk technologies, still reusing most of manufacturing bricks of planar 28nm LP technology and the same design flow and methodology.

Adoption of 28nm FD-SOI for ST-Ericsson’s NovaThor has not introduced any major difficulty in its design, and the FD-SOI version has been taped out shortly after the Low-Power bulk version. Of course special care has been dedicated to further optimize power, exploiting FD-SOI exceptional flexibility and low-power capabilities.

On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.

ASN: Can you talk about the results you expect to see or have seen in the chip? Is there anything about it, or perhaps about the ARM core in particular, that makes it especially well-suited to FD-SOI? Is there anything about the transistor back-biasing capability (which enables significant performance enhancements and power optimization) in the design that makes it challenging to manufacture?

JMC: The wide supply range (ranging from 1.2V down to 0.6V) with excellent performance, and extended back-biasing capability (allowing dynamic modulation of the transistor threshold voltage) offered by 28nm FD-SOI technology have allowed us to exploit the ARM implementation to offer an improved maximum frequency and reach an overall power reduction for the various operating modes of the SoC.

About back biasing, this is a standard feature of FD-SOI technology with no particular challenges for manufacturing. Of course, its dynamic usage to optimize operating points for power (or speed) requires an appropriate device architecture to fully benefit from it.

ASN: In the press, STMicroelectronics has indicated that the 28nm FD-SOI has better power and performance than the industry’s first-gen bulk 22nm FinFETs. Would you say that your choice of FD-SOI puts you in a position of strength, in that you’ll have the mobile industry’s leading technology for 28nm and a choice of mature technologies at 14nm?

JMC: 28nm FD-SOI technology is a unique offer in the SOC industry, allowing the introduction of a fully-depleted technology with a low-cost solution and in a timely manner.

28nm FD-SOI is a planar technology derived from 28nm LP bulk technology, with the same design rules and allowing direct layout reuse (or simplified porting) of basic building blocks and IPs, benefiting from inheriting their maturity level. Also on the manufacturing side, 28nm FD-SOI technology uses the same equipment as Low Power bulk CMOS in a simplified process flow. In ST/Crolles facility we are reaching yield levels comparable to 28nm LP bulk ones, proving that FD-SOI process does not introduce major yield detractors.

A smooth library and IP migration flow coupled with rapid availability for manufacturing is driving the success of this 28nm technology.

Looking at the technology roadmap, the same incremental step for the 14nm node is under development and is on track.

The STMicroelectronics fab in Crolles, France. (Photo credit: Artechnic)

ASN: The plan was to start production in your fab in Crolles, then shift to GlobalFoundries for high-volume production in 2013 — is this still the schedule? From a manufacturing standpoint, what does it take to get a fab ready for FD-SOI production (does it take much longer than a typical bulk scaling transition)? Are there any special tools or other preparations needed?

JMC: For manufacturing, 28nm FD-SOI technology uses the same toolset as for 28nm LP bulk. Process development is complete, and ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other.

Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013.

The ST Crolles fab is highly automated, and already runs a broad mix of products in addition to the new FD-SOI chips. The accumulated assets the company has invested in this fab will increase capacity to 4500 wafers/week by the end of 2014. (Photo credit: Artechnic)

ASN: Let’s talk about the Crolles fab for a minute. Although it may be considered small compared to the big pure-play foundries, some aspects you share with the big foundries – like a large mix of product and advanced automation, right?

JMC: Crolles’ technology mix encompasses Advanced CMOS 28/40 nm, Imaging Sensors, embedded Non Volatile Memories starting at 55nm for Microcontroller and Analog on CMOS 110nm. This mix optimizes very well the accumulated assets we have invested in this Fab toward 4500 wafers week capacity over the next two years.

ASN: How do you see the impact of STMicroelectronics’s decision on the industry? Do you expect others to follow? Will other companies be able to leverage your technology at your foundry partners?

JMC: We would like very much for others to follow us. Through GlobalFoundries, ST is making its FD-SOI technology available to anyone in the microelectronics industry. The ST wide set of silicon-proven 28nm foundation libraries and IPs, encompassing not only basic libraries (std-cells, srams, I/Os) but also complex AMS IPs, is also available to be licensed to those customers aiming for quick access to the technology.

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SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE
;1-4 OCT, NAPA

Tuesday, September 25th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

http://www.advancedsubstratenews.com/wp-content/uploads/2012/09/SOIConf12front_small-610x405.jpg

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California. (Photo Credit: Rex Gelert)

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(You can get the pdf of the full program & registration information from the website.)

THE PAPERS

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

  1. Plenary: talks by Soitec and ARM
  2. Fully-Depleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
  3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
  4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
  5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
  6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
  7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
  8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
  9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
  10. Hot Topics: Fully-Depleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
  11. Late News: tbd, of course…

THE COURSES & PANEL

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively, favorite event. This year’s invited distinguished experts — Scott Luning (GF), Ali Khakifirooz (IBM), Yang Du (Qualcomm). and moderator Sorin Cristoloveanu (Grenoble Institute of Technology) – will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

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Roundup: FD-SOI, Ecosystem Shine at Semicon West

Tuesday, August 7th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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SOI in general and FD-SOI in particular were hot topics at this year’s Semicon West in San Francisco. A panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry was among the highlights.  It featured an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

  • ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
  • GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
  • IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
  • SOI Industry Consortium: Horacio Mendez – Executive Director
  • Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
  • STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
  • UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI figured prominently in a panel on mobile challenges held during Semicon West '12. Left to right: C. Hu (UCBerkeley); R. Moore (ARM); H. Mendez (SOI Consortium); G. Patton (IBM); P. Magarshack (ST); S. Kengeri (GF); S. Longoria (Soitec)

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs (where in the past it was CPUs) and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out products based on ultra-thin layers of both SOI and insulator, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm this summer.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FD-SOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show for the SOI ecosystem, full of energy and renewed enthusiasm.

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GloFo to Fab 28/20nm FD-SOI for ST; ST Tech Open to GF Customers

Friday, June 15th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Two big pieces of news have recently been announced by STMicroelectronics:

  1. to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices;
  2. ST will open access to its FD-SOI technology to GlobalFoundries’ other customers.

The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Here are other key points from the press release:

  • The 28nm FD-SOI generation, currently in the industrialization phase, is scheduled to be available for prototyping by July 2012.
  • The next node, the 20nm FD-SOI generation, is currently under development and is scheduled to be ready for prototyping by Q3 2013.

What they’re saying:

Joel Hartmann, STMicroelectronics Corporate VP, Front End Manufacturing and Process R&D, Digital Sector: “FD-SOI is ideally suited for wireless and tablet applications, where it provides fully-depleted transistor benefits using conventional planar technology, and this arrangement with GLOBALFOUNDRIES ensures our customers will have a secure source of supply.”

Philippe Magarshack, STMicroelectronics Corporate VP, Design Enablement and Services: “Porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI is straightforward, and designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to Bulk, due to the absence of MOS-history-effect. In addition, FD-SOI can be used for either extreme performance or very low leakage on the same silicon, by biasing dynamically the substrate of the circuit. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.”

Gregg Bartlett, Chief Technology Officer of GLOBALFOUNDRIES: “We have a longstanding partnership with ST spanning joint R&D and manufacturing, as well as an unmatched heritage of expertise in SOI technology. We’re pleased to be working with ST to bring this next generation of SOI technology to market and enable continued momentum in the mobile revolution.”

While it might seem like all this is happening very fast, ST has been championing FD-SOI technology for about a decade. In fact, one of the company’s top SOI gurus, Advanced Devices Program Director Thomas Skotnicki, first wrote about it for us at Advanced Substrate News back in 2006. And we’ve been covering it regularly ever since.

For an in-depth look at ST’s FD-SOI design and manufacturing strategy and benchmarking results, be sure to check out their white paper. By the way, designers take note: they also indicate in the white paper that the 28nm FD-SOI Process Design Kit (PDK) is available now, targeting risk production by mid-2012. Evaluation SPICE models are now available for the 20nm node, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

For easy access to the dozens of useful and insightful FD-SOI related articles by contributors on the leading-edge that we’ve published over the years, just hit the FD-SOI tag on the ASN website.

Seems like a new door has opened now, doesn’t it?

Fab 8, located in Luther Forest Technology Campus, Saratoga County, New York, USA is GlobalFoundries' new 300 mm Fab dedicated to advanced technologies. Maximum Full Capacity is 60,000 300mm wafers/month. GloFo also runs high-volume SOI at its fabs in Dresden and Singapore (source: Wikipedia).

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