Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.

SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.

With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.

As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”

SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”

Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.

SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.

With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”

As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”

BEYOND LOGIC

The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.

The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers.  What’s more, SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.

So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights.

STMicroelectronics

In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line based on planar FD-SOI at the 28nm node this year. Prototypes will be ready in June.

The objective, he said, is “…to have a compelling technology offer for the mobile application processor speed race.”

And compelling it is: their 28nm FD-SOI technology performances is 61% higher than comparable bulk technology at 1V. It gets even more interesting at lower Vdd – boasting a 550% improvement at 0.6V.

Check out the presentation – it’s got excellent descriptions, detailed roadmaps (look for products on 20nm FD-SOI in 2014), and clear comparisons. Topics include:

• 28FDSOI positioning vs. bulk technologies
• Design methodology and EDA flow
• From spice models to product: migration methodology from Bulk to FDSOI
• Biasing techniques on FDSOI
• FDSOI ST design environment
• 20FDSOI development track

ARM

In FD-SOI Design Portability, Betina Hold, Senior Principal for Silicon R&D at ARM in San Jose emphasized the ease of porting existing designs from bulk to FD-SOI.

FD-SOI, she concluded, is perfect for high-performance, low-power mobile apps.

Here are the main points she made:

(You can also read ARM’s perspective on the ease of porting from bulk to FD-SOI in a recent ASN article by the company’s Director of SOI Technology, Jean-Luc Pelloie.)

IBM

There were two presentations from IBM, addressing the two major flavors of fully-depleted architectures on SOI: planar FD-SOI, and FinFETs on SOI.

The presentation entitled Recent Advances in FDSOI given by Bruce Doris, Manager of Device Integration at IBM Research, reviewed various device structures. He presented new data indicating that FD-SOI performance is competitive for high performance and at a much shorter gate lengths (Lg), and will scale well beyond 20nm.

FINFET on SOI presented by Terence Hook, Senior Technical Staff Member at IBM, compared with both clarity and depth the characteristics and manufacturability of FinFETs on SOI and bulk with other SOI and bulk structures.

Leti

In a very in-depth presentation, FDSOI strain options FDSOI for 20nm and below, Olivier Faynot, who leads the Innovative Devices Lab at CEA-Leti, demonstrated how most of the existing techniques used on bulk technology are compatible with FDSOI. However, he emphasized that FDSOI devices already meet high performance requirements, especially at the circuit level. A unique feature of FDSOI for future nodes, he noted, is that strained SOI wafers (sSOI – wherein the top layer of silicon is strained at the wafer level) are particularly effective in giving NMOS a boost  (Ion NFET 1.4mA/µm – PFET 1.2 mA/µm @ Ioff 100nA/µm).

Soitec

Enabling Substrate Technology for a Large Volume FD Standard, presented by Christine Pelissier, Director of Business Operations at SOI wafer manufacturer Soitec, gave a broad view of the both the technological and volume supply requirements for the wafers. Soitec is now manufacturing wafers for FDSOI in which the top silicon is controlled to within +/-5 angstroms.

She looked both at the wafers used in FDSOI as well as the partially depleted (PD) SOI wafers which have been in high-volume production for over a decade. She then went on to explain the key features in wafers for planar FDSOI (which Soitec refers to as FD2D) and in wafers for SOI-based FinFETs (FD3D).

Other highlights

Two presentations are not available online. Brian Chen of Agilent (Accelicon) presented 20nm ETUTBB-FDSOI Rev3 Models. (Note that 20nm FD-SOI logic evaluation model cards are now available through SOI Consortium in cooperation with Accelicon/Agilent. An NDA is required.)

Professor Borivoje Nikolic from UC Berkeley presented Microprocessor Design in FD-SOI. This showed their design of a Planar FDSOI microprocessor that will be taped out later this year.

In all, this 6th workshop acknowledged the reality of Planar FDSOI technology starting with the 28nm node. There were plenty of relevant questions and discussions, confirming the promise FDSOI holds as a cost-effective and reliable solution.

As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve been offering these workshops for over two years,” he said. “The community has taken Fully Depleted SOI from a technical advantage in the lab to a technical advantage on mobile products (as presented by ST). The cost, power, performance and manufacturability of FD SOI is a significant driving force.”

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Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)

The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop.

Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.

It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.

The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.

Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.

The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)

This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.

Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.

The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.

Here’s a preview of program – you won’t want to miss it.

In a recent and excellent article in ASN by Thomas Skotnicki, Director of the Advanced Devices Program at STMicro, he explains in a very clear and accessible way why FD-SOI with ultra-thin Body & Box (UTBB) is a better solution for mobile, multimedia SOCs than FinFETs — starting at the 28nm node and running clearly through 8nm.  It is based on the paper he presented at the 2011 IEEE SOI Conference.

In case you missed it in Advanced Substrate News, here it is again.

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ST: FD-SOI for Competitive SOCs at 28nm and Beyond

By Thomas SKOTNICKI, Advanced Devices Program Director, STMicroelectronics

The multi-functional system-on-chips (SOC) needed at the heart of the next generations of wireless, high-performance, low-power multimedia devices have very different needs than the mono-functional processors of the past. Traditionally, the trade-off for computers and servers has been accepting high operational voltages (Vdd) and high stand-by leakage in return for high-performance. This is obviously not an acceptable trade-off for mobile internet devices.

In a mobile world, high-performance must go hand-in-hand with low-operation Vdd and low stand-by leakage. That requires different technologies. As we approach the 20/22nm node and beyond, traditional planar-bulk technologies cannot meet these requirements. The choice comes down to either a planar fully-depleted (FD) SOI solution or a FinFET solution. At STMicroelectronics, we call our flavor of planar FD-SOI UTBB, for ultra-thin body & box. As such, it leverages SOI wafers with both ultra-thin top silicon and ultra-thin buried oxide (BOX). Where more practical, we use a hybrid SOI/bulk configuration, wherein certain devices are placed in the bulk silicon that has been exposed by etching back the insulating BOX layer.

The results we’ve obtained make UTBB a compelling option.

Designing a good SOC involves using the right blend of low-, standard- and high-threshold-voltage (Vth) devices according to the target application and how it’s being used at any given time. Our FD-SOI technology can handle multiple Vth devices and I/Os through a cost effective approach, solving challenges for low-power operation (LOP), low-standby power (LSTP) and analog and high-performance (HP) needs.

UTBB at 28nm

ST’s UTTB technology may be a good candidate even for the 28nm node, as it would provide a boost in speed before 20nm bulk technology is ready. Therefore, we have explored an industrial solution for its implementation.

Our objectives that we met for FD-SOI at the 28nm node were as follows:

• Demonstrate with respect to 28 LP Bulk :
  • + 30% Performance at same Vdd (1V)
  • or 40% lower power consumption for at least the same performance
• Demonstrate feasibility of “easy” porting from Bulk to FD-SOI
• Demonstrate manufacturability (including SRAM yield) of FD-SOI/UTBB (with 7nm top silicon thickness and 25nm buried oxide thickness)

With respect to porting the design, the goal of “easy” porting means:

• the design only needs recharacterisation of critical paths
• FD-SOI masks are redefined from Bulk by CAD2MASK.
• Spice models are available for all devices

The process flow is derived from 28LP Bulk of the ISDA Alliance: Metal Gate First and no stressors. Out of 15 major process modules in the Front-End of Line, only 3 are specific to the FD-SOI process. The number of masks is similar to 28 LP Bulk (actually with a saving of 2 or 3, which could be used for analog adjustments in Hybrid bulk/SOI parts if needed).

More than 25 implant steps are saved vs. 28nm LP Bulk for two Vths. This eliminates 15% of the process steps and results in a process cost saving of 10%. So as long as the SOI substrate cost overhead is less than 10% of the bulk process cost, the FD-SOI process is more cost-effective than the bulk LP process.

It is worth noting that the relative impact of the substrate cost will be more favorable to FD-SOI at subsequent nodes, since the process becomes more complex on bulk and adds more metal levels.

DIBL: the SOC performance metric

The drive current, Ion, has long been the key metric for speed in high-performance microprocessors. But, especially for multimedia SOCs, the effective current Ieff is a much better metric and is heavily dependent on DIBL (Drain Induced Barrier Lowering). The lower DIBL of UTBB transistors reflects their superior electrostatic control and leads to higher performance. The influence of DIBL on maximum operating frequency is more pronounced for higher Vths and/or lower Vdd, which explains why this parameter is crucial for low-power multimedia SOCs – which use higher Vths than high-performance microprocessor chips.

Vth adjustment and Performance Results

The means to adjust Vth constitute a fundamental difference between bulk and FD-SOI devices.

On short devices in bulk, Vth is controlled primarily by channel doping. Vths for logic and SRAM can be adjusted independently.

In FD-SOI, however, Vth is controlled primarily by the gate stack on short and long devices in both logic and SRAM. By also playing upon channel length and ground plane implant below the BOX, we are able to obtain all the Vths we need for our 28nm FD-SOI technology. According to its type (n or p), the ground plane (GP) can shift Vth up by more than 50mV (in the case of our 25nm BOX). GP implants also suppress the depletion depth below the BOX for better DIBL, and improve the effect of body biasing.

Body bias is a powerful performance booster usable at different Vdd points — at low voltages, for example, speed is increased by 30%. The Ion/Ioff trade-off is not hurt (body-biasing simply shifts the operating point along the technology’s Ion/Ioff curve), even for body bias voltages up to 2V. This flexibility is not available with FinFET, and while body bias is possible with planar bulk, at 28nm it is of limited practicality and effectiveness.

We then compared the 28nm FD-SOI to a 28nm bulk low-power-oriented ‘LP’ process and to different performance-oriented ‘G’-type processes, on a DDR3 Memory Controller.

The results indicated FD-SOI had:

• comparable performance to the “G”-type processes at high Vdd, with additional room for overdrive (and without the complexity of ‘G’-type processes)
• overall best performance across all practical Vdd values
• a competitive advantage at low Vdd, with over 40% performance advantage over ‘G’ at 0.6V power supply
• best power efficiency

Additional benchmarking on an ARM Cortex-A9 is confirming these results.

20nm goals

We want to propose a differentiated technology at 20nm node providing a 20% boost in performance versus 20LPM at the same Vdd. We also want it to be competitive versus a potential Trigate SOC at 22nm.

Under our 20nm UTBB FD-SOI scheme, performance will be boosted by dynamic control of a Full-Forward Body Bias (F-FBB) architecture. Vth modulation sources will include gate stack, ground-plane, counter-doping, body-bias and L poly-bias.

We have now compared our FD-SOI with bulk and FinFETs at 20nm, with impressive results. While FinFETs and UTBB FD-SOI very much resemble one another (in fact, a UTBB device looks rather like a FinFET tipped on its side), with FD-SOI we are seeing:

• a large gain in performance: 42% at 0.9V and 98% at 0.7V
• best performance
• G-like performance on an LP process
• best power efficiency

(Courtesy: STMicroelectronics, IEEE SOI Conference 2011)

Work by Leti and by IBM and partners also shows excellent SRAM transistor matching. UTBB was also found to have much lower threshold voltage variability, thanks in large part to the undoped channel. This in turn enables smaller SRAM cells and/or lower minimum voltages (Vmin) – a gain of 150mV, which translates into significantly lower power consumption. We have determined that the SRAM remains fully functional as low as Vdd=0.4V.

14nm to 8nm

An FD-SOI roadmap through 14nm indicates an orderly and logical progression. Leti has shown that further thinning of the insulating BOX layer enables FD-SOI scalability down to 8 nm with top silicon thickness (TSi) no thinner than ~ 6-7nm (post-processing).

Soitec’s Xtreme SOI wafers with ultra-thin BOX (25nm) is ramping to volume this year, targeting the 28nm node. With SEH and a third supplier on tap, the supply chain is in place.

Straightforward Move to 28nm

ST has been working on FD-SOI for over 10 years. We have research programs or partnerships on 3 sites : Crolles, Leti, and IBM Albany NanoTech. We have collaborated with Soitec for wafer supply.

The key technology elements for UTBB have been demonstrated.

The move from R&D to an industrial process of 28nm FD-SOI technology is for us (and for our partners) an efficient and straightforward response to the world-wide competition. The extension of FD-SOI towards the 20nm and 14nm nodes is also in preparation with new boosters to further increase the performance growth rate.

UTBB FD-SOI promises to give STMicroelectronics a significant edge in both the near term and for years to come.

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This article was adapted from “Competitive SOC with UTBB SOI”, T. Skotnicki et al, presented at the 2011 IEEE SOI Conference.  It was first posted in Advanced Substrate New on November 18, 2011.