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The Ever-Expanding 28nm FD-SOI Ecosystem (Samsung Interview, Part 3 of 3)

Thursday, December 24th, 2015

By Adele HARS

For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)

ASN: Let’s talk a little more about IP availability.

Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.

Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.Samsung_28FDSOI_IP_reuse_14

ASN: In terms of the ecosystem, what remains to be done?

KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.

AF: Especially as you have good support for RF/analog functionality. So, this ecosystem becomes quite important.Samsung_28FDSOI_enablement_11

KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.

As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.

ASN: Any closing thoughts?

KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.

Samsung_28FDSOI_future_15

~ ~ ~

This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).

When to Choose 28nm FD-SOI And Why (Samsung Interview Part 2 of 3)

Tuesday, December 22nd, 2015

By Adele HARS

For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)

ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?

Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.

Samsung_28FDSOI_lowpower_knobs_13

Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.

Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.

ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?

KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.

Samsung_28FDSOI_Vdd_9

Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.

KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.Samsung_28FDSOI_PPA_7

ASN: Can designers get started today?

KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.

Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.

There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.

ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.

KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.

Samsung_28FDSOI_bodybias_8

FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.

There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.

AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.

ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?

KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.

Samsung_28FDSOI_apps_6

AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.

KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).

Yes, 28nm FD-SOI Silicon Is Running (Samsung Interview, Part 1 of 3)

Saturday, December 19th, 2015

By Adele HARS

ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.

ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?

Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.

What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.

Samsung_28FDSOI_PDKS_12

Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship

KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.

We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.

ASN: Do you have other customers lined up?

KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.

ASN: What about technology readiness and maturity?

KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.

Samsung_28FDSOI_process_costThis slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.

ASN: When will we see the first high-volume FD-SOI chips? Next year?

KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.

AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.

KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.

[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]

Samsung_28FDSOI_wafersAF: ST is our first partner for high-volume production. We started working together very early, so they have a time-to-market advantage.

KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.

Interview (Part 2 of 2): Leti Is A Catalyst For The FD-SOI Ecosystem, CEO Marie Semeria Explains Where They’re Headed

Thursday, December 17th, 2015

By Adele HARS

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

Leti_MobileCR_JAYET_CEALeti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

CEA002051_JAYET_CEALeti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

Interview: Leti Is The Moving Force Behind FD-SOI. CEO Marie Semeria Explains The Strategy (Part 1 of 2)

Tuesday, December 8th, 2015

By Adele HARS

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?

MarieSemeria_LetiCEO_©PIERREJAYETMarie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.

Minatec_aerial_loresLeti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

~ ~ ~

Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.


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