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Archive for October, 2015

RF-SOI vs FD-SOI with RF – What’s the Difference?

Wednesday, October 28th, 2015

By Adele HARS

Is RF-SOI the same thing as RF on FD-SOI? No, it’s not. However, the runaway success of RF-SOI and the growing list of recent announcements related to FD-SOI with integrated RF has lead to some confusion in the press and social media. The two are different technologies, addressing different markets, and built on two very different types of SOI wafers. The use of one technology or the other depends on the requirements of the targeted RF application.

For the non-technical reader, here is a bit of basic background. At the most simplistic level – RF: radio frequency – is part of the analog family, and as such is all about waves. And when you talk about waves, you talk about losses over distance (attenuation), speed, wavelength and frequency – which is why the RF design has a rep of being something of a black art. The distance to cover, the power envelope and the amount of data to carry over that distance (and of course, the cost) determine the chip solutions. An important part of the RF chip solution is the choice of the wafer substrate itself.

So here’s a quick primer to help sort out what’s what. Please bear in mind, though, that this is a fast-evolving world, so what you’re about to read is not a definitive and forever what’s what – but more of a general (and simplified) “this is how it is currently shaking out”.

RF-SOI – Talk to the Tower

When it comes to using your mobile device for data transmission over a 2G, 3G, 4G/LTE/LTE-A (and next, 5G) network, you still need dedicated RF front-end modules (FEMs). FEMs handle the back-and-forth of signals between the transceiver and the antenna. They contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. Traditionally, they were built on gallium arsenide substrates. But more and more, the multiple chips in FEM chipsets are being reduced to single SOCs built on a special class of high-resistivity SOI wafers. This is the realm of RF-SOI. The wafers for RF-SOI are designed specifically to handle the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances.

eSI_SoitecUCLwaferSoitec premiered a radically new and immensely successful generation of RF-SOI substrates in 2013: the enhanced Signal Integrity™(eSI) family, which introduced the concept of the “trap-rich” layer developed at UCL. (Image courtesy of Soitec)

The latest standards (LTE-A and 5G) raise the stakes ever higher, requiring mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

For RF designers, that means choosing substrates that favor low RF loss and high RF linearity. A couple of years ago, SOI leader Soitec, in partnership with UCL, brought breakthrough RF-SOI wafer technology to the market (read about that here). Now, a few generations later, Soitec estimates that one billion RF devices are produced each quarter using their advanced and enhanced Signal Integrity™(eSI)wafers for RF. In fact it would be nigh near impossible to find a smartphone that doesn’t have an RF FEM based on  RF-SOI wafer technology.

Here at ASN, we’ve covered many of the leaders in RF-SOI FEMs over the last few years. Click on any of these names to get an idea of what they’re doing: IBM (now part of GlobalFoundries), PeregrineSkyWorksTowerJazzSTQorvoSony, QualcommGraceToshiba and MagnaChip. To learn more about the latest developments in wafer technology for RF-SOI, click here. With demand soaring, Soitec’s most advanced RF-SOI wafers are now also being produced by Simgui in China – read about that here.

In fact, the cover story and technical features of the October 2015 issue of the prestigious Microwave Journal is dedicated to RF-SOI – click here to read it.

So in terms of terminology, that’s “RF-SOI”. Now let’s look at how RF on FD-SOI is different.

RF in FD-SOI – for digital integration

When we talk about RF in FD-SOI, we’re typically talking about some RF functionality being integrated into SOCs that are essentially digital processors. True, you can integrate RF functionality into an SOC built on planar bulk (it’s generally agreed to be a nightmare in bulk FinFETs, though). But you can integrate RF into your digital SOC much more easily, efficiently and with less power if you do it in FD-SOI.

RF/analog has a (well-deserved) rep of being the most challenging part of chip design. Analog/RF devices are super sensitive to voltage variations. The digital parts of a chip, which have strong, sudden signal switching, can raise havoc with nearby analog/RF blocks. This means that the analog/RF designers have to care acutely about gain, matching, variability, noise, power dissipation, and resistance. They use all kinds of specialized techniques: FD-SOI makes their job a lot easier (good explanation in slide 8 here). What’s more, FD-SOI’s analog performance far exceeds bulk.

What sort of chips are we talking about? For now, we’re talking about processors for mobile devices, for IoT, for automotive, for consumer electronics. When we say “RF in an FD-SOI SOC”, we’re currently talking about chips that are connecting over a relatively short distance to a nearby box or device (<100m for local WiFi, or a few meters for Bluetooth or Zigbee, for example).

ST’s new set-top-box processors on 28nm FD-SOI (read about them here) are a great example. They are the first on the market integrating 4×4 802.11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This means the set-top boxes can reliably serve lots of HD video via WiFi to multiple users throughout the house (hopefully ending the cry: “Who’s hogging all the Wifi?!?”). ST credits their 28nm FD-SOI silicon technology with providing that highly-efficient RF, state-of-the-art WiFi performance and robustness required for reliable video delivery inside the home.

For RF on FD-SOI – as in other FD-SOI apps – designers use SOI wafers with ultra-thin silicon, ultra-thin insulating BOX and phenomenal top silicon thickness uniformity. These wafers are not the special high-resistivity wafers used in RF-SOI. Rather, they are the latest generations of the same (amazing!) FD-SOI wafers that Soitec introduced in 2010. (For an excellent, in-depth interview with the Soitec FD-SOI wafer guru on the supply chain and the most recent developments, click here.)

TopSiLoss_FDSOIThe top silicon uniformity of Soitec’s “FD-2D” wafers for FD-SOI is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. The BOX thickness is 10nm to 25nm, depending on the customer’s approach.

This is the type of wafers that GloFo, ST, Samsung, Freescale, Sony, several other companies in Japan and many more around the world are using when they say they’re doing RF on FD-SOI. Bear in mind that this level of SOC integration is fairly new (Samsung and TSMC just announced RF integration into SOCs for the first time in 2014 on 28bulk). But using FD-SOI technology and the corresponding ultra-thin SOI wafer substrates makes life much easier for the RF folks on the design teams, gets far better performance and far lower power at a much more attractive cost.

Further ahead, FD-SOI is also a candidate for transceivers and baseband/modem SOCs, which require high-performance digital and analog/RF integration. But even with transceivers on FD-SOI, you’ll still need the FEM on RF-SOI to handle the interface.

So, that’s the current difference between RF-SOI and RF on FD-SOI.

Hope that helps to clear things up?

Advanced Substrates for 3D and Other New Markets Drive New Fab Inspection Equipment: Interview with Altatech GM

Tuesday, October 6th, 2015

By Adele HARS

New approaches in chipmaking and fast-evolving specialty markets are driving the need for new equipment on the fab floor. 3D chips (be they stacked or bonded), MEMS, lighting, power – they’re all leveraging wafer substrates in new ways. Altatech, the equipment division of SOI-wafer leader Soitec, has just announced new inspection equipment for foundry and IDM customers fabbing 3D and other chips. ASN talks to Jean-Luc Delcarri, Altatech general manager, about the company and its recent announcements.

Advanced Substrate News (ASN): Can you tell us briefly about the company and the markets it serves?

mgmt_jldelcarriJean-Luc Delcarri, Altatech general manager

Jean-Luc Delcarri (JLD): Altatech makes specialty equipment for the fab floor. We have two main areas of deep expertise: one is in defect inspection, and the other is in CVD* technologies for semiconductor, LEDs, MEMS and photovoltaic devices. I founded the company in 2004, and then in 2012 we became a subsidiary of SOI wafer leader, Soitec.

ASN: At Semicon Europa 2015, you announced “…a new, high-speed inspection system for ultra-thin, transparent and bonded substrates inspection for 3D applications in power, MEMS and mobile technologies.” What’s driving that market?

JLP: Yes, at Semicon we announced the Eclipse TS, which is a unique, high-reliability and easy-to-implement inspection system solution that’s now ready for mass production.

You’ve got the need for these advanced substrates that’s being driven by really rapidly growing markets in automotive, industrial power and mobile electronics. We’ve been working quietly on this tool for years, and now the Eclipse TS has been qualified for volume manufacturing at a leading-edge semiconductor manufacturer, so we’re really excited about it.

AltatechEclipseTSInspectionSystem2015Altatech’s Eclipse TS, a high-speed inspection system for ultra-thin substrates in 3D applications.

ASN: What makes the Eclipse TS different from other inspection sytems?

JLP: When you’re looking for defects on these advanced wafer solutions, you have to do much more than scan the top: you need to inspect the front side, the back side and the edge of very thin wafers – and you have to do it without touching them. Our ability to do all this makes us totally unique on the market: we have built this tool on a strong IP portfolio.

So with the Eclipse TS, you have a high-speed inspection system that can measure very thin and stacked wafers down to 50 microns, as well as Taiko rings, stacked substrates and silicon-on-glass wafers. Plus we can do the front-side, back-side and edge inspection in one pass with no back-side contact.

In today’s 3D technologies, substrates undergo grinding, stacking and gluing, so you can end up with wafers with a very high bow, or  wafers with a warp of up to 6 mm. We can handle those wafers. In fact, the Eclipse system can monitor these sorts of processes. The inspection occurs without any contact on the active surface, and at a throughout of more than 90 wafers per hour for 300-mm substrates.

We’re of course compliant with the latest automation standards, so the system can be fully integrated into the line, and provide comprehensive reporting for defects classification and yield maps.

Our full Altatech Eclipse series covers advanced metrology and holistic inspection systems. That means we can detect, count and bin defects during the wafer manufacturing process as well as do continuous outgoing wafer-quality inspection. So the quality of both the wafer-surface and edge is ensured. We also have proprietary Eclipse sub-modules that detect specific sorts of particles and defects of interest for both patterned or unpatterned wafers.

All that puts Altatech in a leading position in what is a very large market opportunity.

AltatechAltaCVD3DMemoryCell2015Altatech’s AltaCVD 3D Memory Cell deposits the ultra-thin semiconductor films used in high-density, low-power memory chips 10 times faster than conventional ALD systems.

ASN: You also make CVD – deposition – equipment. Can you tell us a little about that, and what’s driving those markets?

JLP: Sure. Last year we introduced the AltaCVD 3D Memory Cell™, which is the newest member of our AltaCVD product line. This is used for depositing ultra-thin semiconductor films when you’re manufacturing the high-density, low-power memory chips used throughout mobile electronics. Our new system does atomic-layer deposition 10 times faster than conventional ALD** systems, which is of course huge when you’re manufacturing advanced memories where you need to run in very high-volume production with extreme cost efficiency.

In the new 3D device architectures for mobile apps, our customers are looking to really increase memory capacity and boost performance. And to do this, they need very advanced material deposition to create atomic-layer films with high uniformity – you really are at the atomic level of control here. The AltaCVD 3D Memory Cell deposits layers of chalcogenide*** materials by using a combination of precursors, which is very leading edge.

So with our tool you can use conventional gaseous or solid precursors, but we also have a patented pulsed technology, which means you can also use advanced CVD precursors that are available only in liquid form. This is remarkable versatility: it allows us to achieve exceptional step coverage over features with very high aspect ratios – that’s a key performance requirement when you’re talking about vertical integration high-density memory circuits.

You can also use it for advanced pre-treatment of semiconductor surfaces (which improves circuit functionality), as well as post-treatment of surfaces (which enhances electrical performance).

Because it’s used in everything from research to high-volume manufacturing, it can process 200-mm or 300-mm substrates, and uses a single-wafer, multi-chamber architecture. One of our key customers demonstrated it last year. We’re now selling production units, and we’re pleased to say it’s been very successful.

ASN: Do you have other products in the pipeline?

JLP: Next up we have a new solution for high aspect ratio 3D copper deposition. The system, which is called RUBY, can deposit a barrier layer of titanium nitride or tantalum nitride with almost 100% step coverage on an aspect ratio higher than 10:1. This is followed by deposition of a copper seed layer with similar performance. Combined with a proprietary copper cleaning process, it will be able to meet the growing challenge of copper metallization in MEMS and semiconductor 3D integration. We’ll release it as soon as we’ve completed our product milestones for reliability and performance.

ASN: Where do you see the highest-growth areas?

JLP: We’ve developed the right technology for the right time in a number of key markets, so we’re really well-positioned to answer the needs of a number of high-growth markets. The move to 450mm wafers is something we’re ready for, which will probably happen first in advanced memories. But in the meantime we also see significant activity in MEMS, RF, high power and LEDs. We’re winning customers in China who are looking to be leaders in these markets. All in all, much of the future of the phone in your pocket depends on what we can help our customers do in high-volume and cost-effectively on the fab floor – so it’s a very exciting time to be in this business.

~ ~ ~

*CVD=chemical vapor deposition

**ALD=atomic layer deposition

*** chalcogenides include sulphides, selenides, and tellurides

GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

Monday, October 5th, 2015

By Adele HARS

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.


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