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The SOI Papers at VLSI 2014 (Part Two)

Wednesday, July 30th, 2014

By Adele HARS

Last week, we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.)

This post here gives you the abstracts of all the other papers we couldn’t fit into Part 1.  (Note that as of this posting date, the papers are not yet available on the IEEE Xplore site – but they should be shortly.)

There are in fact two symposia under the VLSI umbrella: one on technology and one on circuits. We’ll cover both here. Read on!

(More!) SOI Highlights from the Symposium on VLSI Technology

4.2: III-V Single Structure CMOS by Using Ultrathin Body InAs/GaSb-OI Channels on Si, M. Yokoyama et al. (U. Tokyo, NTT)

The authors propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). They experimentally demonstrate both n-and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.

4.4:  High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si, S. Kim et al. (U. Tokyo, IntelliEPI)

The authors present the first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by a direct wafer bonding (DWB) process using InGaAs channels grown on Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs have exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement factor of 3× against Si MOSFETs.

6.1: Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14nm and Beyond, T. Ando et al. (IBM)

The authors demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate technology with a 14nm design rule. The SIGMA stack uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100x PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched gate resistance due to absence of high resistivity WF-setting metal and more room for W in the gate trench. This gate stack solution opens up pathways for aggressive Lg scaling toward the 14nm node and beyond.

8.1: First Demonstration of Strained SiGe Nanowires TFETs with ION Beyond 700μA/μm, A. Villalonet al. (CEA-LETI, U.Udine, IMEP-LAHC, Soitec)

The authors presented for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. They analyzed the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices were also investigated, showing a 1/W3 dependence of ON current ION per wire. The fabricated devices exhibit higher Ion than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

8.2: Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs, T. Mori et al. (AIST)

The authors proposed a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. They  demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.

9.1: Ge CMOS: Breakthroughs of nFETs (I max=714 mA/mm, gmax=590 mS/mm) by Recessed Channel and S/D, H. Wu et al. (Purdue U.)

The authors report on a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted sub-100 nm region down to 25 nm for the first time. Considering the Fermi level pining near the valence band edge of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the accumulation-mode (JAM) Ge nFET is proposed.

13.4: Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing, T. Matsukawa et al. (AIST)

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain cur-rent (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

13.6: Demonstration of Ultimate CMOS based on 3D Stacked InGaAs-OI/SGOI Wire Channel MOSFETs with Independent Back Gate (Late News), T. Irisawa et al. (GNC-AIST)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

17.3: Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era (Invited), S. Kamohara et al. (Low-power Electronics Association & Project, U. Electro-Communications, Keio U, Shibaura IT, Kyoto IT, U.Tokyo)

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, the authors describe their recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other lcircuits. Their 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

18.1: Direct Measurement of the Dynamic Variability of 0.120μm2 SRAM Cells in 28nm FD-SOI Technology, J. El Husseini et al. (CEA-Leti, STMicroelectronics)

The authors presented a new characterization technique successfully used to measure the dynamic variability of SRAMs at the bitcell level. This effective method easily replaces heavy simulations based on measures at transistors level. (It’s worth noting that this could save characterization/modeling costs and improve the accuracy of modeling.)  Moreover, an analytical model was proposed to explain the SRAM cell variability results. Using this model, the read failure probability after 10 years of working at operating conditions is estimated and is shown to be barely impacted by this BTI-induced variability in this FD-SOI technology.

18.2: Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell, A. Ueda et al. (U. Tokyo)

A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated.  In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with Vth self-adjusting nFETs and pFETs.

18.3: Systematic Study of RTN in Nanowire Transistor and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability, K. Ota et al. (Toshiba)

The authors experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various NW widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture and emission are independent of NW size, while threshold voltage fluctuation by RTN was inversely proportional to the one-half power of circumference corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, threshold voltage fluctuation is enhanced by HCI and NBTI and increase of threshold voltage fluctuation becomes severer in narrower W.

SOI Highlights from the Symposium on VLSI Circuits

C19.4: A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. E. Olieman et al. (U.Twente)

The authors presented an innovative nine-bit interleaved DAC (digital-to-analog converter) implemented in a 28nm FD-SOI technology. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage.

UTwenteC194VLSI14lowres(Courtesy: VLSI Symposia)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2. From A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist, E. Olieman et al. (University of Twente)

C6.4: A Monolithically-Integrated Optical Transmitter and Receiver in a Zero-Change 45nm SOI Process, M. Georgas et al . (MIT, U.Colorado/Boulder)

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

The SOI Papers at VLSI 2014: Breakthroughs in 14nm FDSOI; 10nm SOI FinFETs

Monday, July 14th, 2014

By Adele HARS

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four papers in the Highlights Sessions covered SOI devices for the 10 and 14nm nodes.

There were so many great SOI-based papers that we’re going to cover this conference in two posts.  This post covers the three big 14nm FD-SOI and 10nm FinFET papers. Summaries and abstracts of all the others will be covered in Part 2.  (Note that as of this posting, the papers are not yet posted on the IEEE Xplore site – but they should be shortly.)

Read on!

Top SOI Highlights from the Symposium on VLSI Technology

2.3: 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications. O. Weber et al. (STMicroelectronics, CEA-LETI, IBM)

This is the big paper we’ve been waiting for – the one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs. We still don’t have a side-by-side FD-SOI v. bulk FinFET comparison, as there is scant data at comparable leakage on bulk FinFETs at 14nm publicly available with which to compare. But based on what they’ve been seeing and some extrapolation, the FD-SOI  technology developers see the figures presented in this paper as a big win.  We’ve already seen hints of this in a recent ASN piece (click here to see that one) showing 14nm FD-SOI matching 14nm bulk for performance and coming in at a much lower cost.  Now in terms of performance, here’s the VLSI paper detailing the FD-SOI side of the story.

The authors confirm a scaling path for FD-SOI technology down to 14nm, using strain-engineered FD-SOI transistors. Compared to 28-nm FDSOI, this work provides an 0.55x area reduction from scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back-bias, an additional 40% dynamic power reduction for ring oscillators is experimentally demonstrated. Moreover, a full single-port SRAM is described, including a 0.081 μm2 high-density bitcell and two 0.090 μm2 bitcell designs used to address high-performance and low-leakage/low Vmin requirements.

(Courtesy: VLSI Symposia)

TEM of an FD-SOI nMOS transistor, showing gate-to-drain capacitance components and experimental values. From 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications (O. Weber et al., STMicroelectronics, CEA-LETI & IBM)

2.2: A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI.  K.-I. Seo et al.  (Samsung, IBM, ST, GF, UMC)

This paper covers the first-ever demonstration of FinFET technology suitable for 10-nm CMOS manufacturing. Targeting low-power and high-performance, it offers the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported on both bulk and SOI substrates. A 0.053 μm2 SRAM bit-cell – and this part was on SOI –  was reported with a low corresponding static noise margin of 140 mV at 0.75 V.  The team developed intensive multi-patterning technology and various self-aligned processes with 193i lithography to overcome optical patterning limits. A multi-workfunction gate stack provides Vt tunability without the variability degradation channel dopants induce.

(Courtesy: VLSI Symposia)

Projected scaling trend, featuring the tightest contacted poly pitch (CPP=64 nm) and metallization pitch (Mx=48 nm) ever reported, on both bulk and SOI substrates. From A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, by K.-I. Seo et al.  (Samsung, IBM, ST GF, UMC)

2.4: Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

The authors demonstrated high performance (HP) s-SiGe pMOS pMOSsfinFETs with Ion/Ieff of ~1.05/0.52mA/μm and ~1.3/0.71mA/μm at Ioff=100nA/μm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ~30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. They also demonstrate the most aggressively scaled s-SiGe finFET reported to date, with WFIN~8nm and L G~15nm, while maintaining high current drive and low leakage. With their very low GIDL-limited ID, min and more manufacturing-friendly process compared to high-Ge content SiGe devices, as well as impressive Ion~0.42mA/μm at Ioff =100nA/μm and gm, int as high as 2.4mS/μm at VDD=0.5V, s-SiGe FinFETs are strong candidates for future HP and low-power applications.

(Courtesy: VLSI Symposia)

TEM images of the most aggressively scaled SiGe FinFET reported to date with a fin width of ~8nm and gate length of ~15nm. From Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

Rump Sessions

There were also two rump sessions held during the conference, which were co-chaired by Soitec CTO Carlos Mazure. The SOI ecosystem was well-represented, the rooms were packed and the debate lively.

Rump Session 1: Who gives up on scaling first: device and process technology engineers, circuit designers, or company executives?  Which scaling ends first – memory, or logic? Panelists: M. Bohr, Intel; M. Cao, TSMC; J. Chen, Nvidia; S-H Lee, Hynix; T-J King Liu, UC Berkeley; K. Nii, Renesas: R. Shrivastava, Sandisk; H. Jaouen, STMicroelectronics; E. Terzioglu, Qualcomm

The take-away here is that the majority of panelists and attendees see company executives giving up on scaling in the face of rising costs.

Rump Session 2: 450 mm, EUV, III-V, 3D; All in 7nm? Are you serious?!  Panelists:  W. Arnold, ASML;
 R. Gottscho, Lam Research; K. Hasserjian, AMAT; S. Iyer, IBM;
 C. Maleville, Soitec; A. Steegen, IMEC

The general consensus was that 3D integration is needed and will be adopted at the 7nm node due to delays and the high cost of the EUV and III-V, and the lack of 450mm wafer supply and support.


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