Part of the  

Solid State Technology

  Network

About  |  Contact

Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI

By Adele HARS

The Synopsys’ Galaxy Design Platform has been extended to support the Samsung-STMicroelectronics strategic agreement on 28nm FD-SOI (see press release here).

They’ve covered all the bases, so that designers going to Samsung’s foundry services for ST’s 28nm FD-SOI can hit the ground running. Samsung’s vice president of foundry marketing, Dr. Shawn Han, says, “28nm FD-SOI is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20-nm. Our close collaboration with Synopsys and ST will enable designers to reduce risk, accelerate time-to-market, minimize power and maximize performance to expand 28nm FD-SOI adoption.”

Synopsys has collaborated closely with ST on FD-SOI for several years now – Galaxy is already successfully silicon-proven in several 28nm FD-SOI SoCs with multi-core processors, says the company. And just a few weeks ago, Synopsys announced that ST had standardized on Synopsys’ IC Compiler place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization (see that press release here).

Synopsys says that the Galaxy Design Platform enables designers to take full advantage of FD-SOI’s low power and high performance. “Because the Galaxy Design Platform is silicon-proven on ST’s 28nm FD-SOI process with multiple tapeouts of low power designs running in the gigahertz frequency range, customers can adopt this technology with confidence,” said Antun Domic, executive vice president and general manager, Design Group at Synopsys. “Combined with the Lynx Design System and DesignWare IP, the Galaxy Design Platform enables engineers to derive maximum benefit from the FD-SOI process and our continued collaboration with ST and Samsung will ensure ease of adoption of FD-SOI for SoC design.”

The Galaxy Design Platform is a suite of design tools that work in an integrated way for design on both the digital and analog sides. It enables concurrent area, power and timing optimizations to enable engineers to optimize their designs for the ST 28nm FD-SOI process. Synopsys says the advanced design enablement features like the IC Compiler tool’s concurrent clock and data optimization, layer-aware optimization, physical datapath and comprehensive support for hierarchical and low-power design features can also be directly accessed by Lynx users for high-performance and low-power CPU and GPU design.

The Lynx Design System is an automation environment for chip designers. Lynx incorporates the full Galaxy Platform for both digital and analog implementation and for comprehensive design analysis. With technology portability and designer productivity as goals, the Galaxy flow in Lynx is architected technology independent. The accompanying technology plug-in structure enables design teams to quickly setup and implement on new technology nodes. Additionally, the automation architecture in Lynx enables the inclusion of third-party developed scripts and tools. Synopsys collaborates with the foundries to encapsulate technology-specific scripts and settings in the plug-in accelerating project setup and design time.

FD-SOI SPECIFICS

Specifically for ST 28FDSOI, Synopsys collaborated with ST on the development of an ICC-Kit supporting UPF (Unified Power Format) and back-bias connections. Synopsys also implemented and validated a Lynx technology plug-in, integrating technology specific settings and scripts from the ICC-Kit into Lynx. The resulting combination significantly reduces designer overhead and implementation time for SOI nodes like ST 28FDSOI. Designers still need to add constraints and optimizations for their specific design, including the UPF files that specify the power intent. IC Compiler will connect the well ties and voltage converters in a manner consistent with the power-intent specified in the UPF Files (using scripts from the ICC-Kit).

All this should enable broader market adoption of ST’s 28nm FD-SOI technology for SoC design. “The close collaboration between ST design teams and Synopsys led to advanced silicon-proven design enablement solutions that fully leverage the performance and power promise of FD-SOI technology and provide the foundation needed to meet tight time to market windows,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics.

So there’s no need to wait. The Synopsys Galaxy Design Platform and Lynx Design System with support for ST and Samsung 28-nm FD-SOI process technology are available now from Synopsys. The 28-nm FD-SOI-enabled PDK, standard cells and memories for early design are available now from Samsung.

There’s no more doubt about it: for FD-SOI, it’s full speed ahead!

Note: Many thanks to Synopsys for help on the technical details in this piece.

4 Responses to “Synopsys Design Flow Support for Samsung-ST 28nm FD-SOI”

  1. Sang Kim Says:

    Sang Kim

    28nm bulk technology is in mass production for several years by major semiconductor companies, but 28nm FD-SOI technology is not manufactured by major semiconductor companies yet except possibly by ST and Samsung soon. In my opinion even if 28nm FD-SOI were manufactured today, it wouldn’t be superior to 28nm bulk in terms of transistor performance and manufacturing costs. 28nm FD-SOI with possibly 7nm SOI thickness will provide low power but not necessarily high performance because of the mobility degradation due to scattering of charge carriers at the top gate oxide surface and SOI surface at the bottom in the 7nm thin SOI channel. Also, the SOI wafers will cost significantly higher than bulk Si wafers. Major issue with FD-SOI is its scalerbility. For 22nm FD-SOI requires possibly only 4-5nm SOI channel thickness, resulting in more mobility degradation, thus adversely affecting transistor performance. Furthermore, how the number of electrons in the 5nm thin SOI channel can be controlled by the back bias is not clarified. The back bias could also further degrade the carrier mobility in the 5nm thin SOI channel. It appears that FD-SOI is not scaleable.

  2. Adele Hars Says:

    Sang Kim, all of the issues you bring up about FD-SOI have been addressed. It is demonstrated to be far superior to 28nm bulk in terms of both cost and performance. The wafer cost is absorbed by savings in manufacturing steps. Back bias works extremely well. It is scalable to the 10nm node.

  3. xavier c. Says:

    Sang Kim’s opinion, as any opinion, is respectable.
    However if we look at facts, taking a very pragmatic point of view:
    - the concerns over 28nm FD-SOI manufacturing are clearly not shared by people like ST or Samsung …and the latter can hardly be suspected of taking manufacturing cost and efficiency lightly.
    More generally, why would Samsung have signed up for FD-SOI if they had any doubt on its manufacturability, cost, performance and power efficiency – specially as they already have 2 flavors of 28nm bulk in store ?
    - if we look specifically at performance – factoring in any potential degradation source, be it any mobility drop or whatever else:
    first, of course, there was some time ago the impressive demo of a NovaThor L8580 Apps Processor at over 2.5GHz (even up to 3GHz but let’s be conservative), but more recently, there were quite explicit statements in slides shown on Samsung’s booth at DAC that read: “20nm performance at 28nm cost”. Pretty good then.
    - sure, an SOI starting wafer is more expensive than a traditional bulk silicon wafer. However, it’s more interesting to look at final wafer cost — and then the former statement is clear: cost on par with 28nm bulk for much better results. Which confirms the findings from several different studies published earlier.
    - finally, regarding scalability, it does not look like Sang’s opinion is confirmed by the results published by people who actually work on next generation FD-SOI — on the contrary. Excellent results have been published, for example at VLSI2014 or IEDM2013 (very competitive results with 6nm channel thickness and 20nm gate length, i.e. over 30% shorter gate length than 16nm-node FinFET).

  4. Sang Kim Says:

    I posted my comments here on 6/16/14, but removed for unknown reasons without explanation. That is why I posted elsewhere. This is not the first time happened to me here. I don’t understand why my comments are posted here today. I would appreciate that my comments be removed here.

    Sang

Leave a Reply


Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.