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Interview with: Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain

Christophe Maleville has been Senior Vice President of Soitec’s Microelectronics BU since 2010. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as Vice President, SOI Products Platform at Soitec, working closely with key customers worldwide. He has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from the Grenoble Institute of Technology and obtained an Executive MBA from INSEAD.

Advanced Substrate News (ASN): With the recent news that Samsung has joined the ranks of foundries offering high-volume 28nm FD-SOI, can you tell us why customers are turning to FD-SOI?

Christophe Maleville (CM):   The short answer is that they consider FD-SOI provides a much better combination of power consumption, performance and cost than any alternative for the technology node they target.

At 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node. And for some products at least, using this enhanced 28nm is actually a better choice than going to the next node.
Then 20nm FD-SOI (also called 14FD) will provide the kind of performance and energy efficiency promised by 16nm/14nm FinFET, at a lower cost than even 20nm planar bulk CMOS.

ASN: Who are the wafer suppliers and what kind of capacity is there?

CM:  There are three major suppliers serving the FD-SOI market:  Soitec, Shin-Etsu Handatoi (SEH) and SunEdison (formerly MEMC).  SEH is the world’s biggest producer of silicon wafers. Soitec is the world leader in SOI wafer manufacturing. SunEdison has been supplying SOI wafers for over a decade.  SEH and Soitec use Soitec’s Smart CutTM manufacturing technology.  However, each company fine-tunes the technology to meet to its customers’ specifications.
For our part, I can add that Soitec has two distinct production sites. We source the raw bulk base and donor wafers (from which the FD-SOI wafers are fabricated under our FD-2D product name) from a diverse group of suppliers, which enables us to optimize the quality of our wafers, combining the best wafers for donor and handle. We are converting capacity at our plants in France and Singapore to meet expected FD-SOI demand.

The industry’s current installed capacity is in the range of one million 300mm SOI wafers/year. However, the wafer suppliers are ready to expand capacity to meet market demand, so we could easily reach two million in well under a year, and continue ramping rapidly from there. It’s perhaps worth understanding that the equipment and materials needed to manufacture SOI wafers are standard industry hardware and materials – there are no exotic parts to the manufacturing equipment nor rare materials that could cause bottlenecks in the processes we use to manufacture the SOI wafers.

ASN:  FD-SOI wafers are known to have very stringent requirements. Can you review those here?

CM: SOI wafers are subject to many of the same criteria as other advanced wafers, such as flatness and defectivity.  The additional parameters for FD-SOI wafers, which require tight control, are:
the top silicon thickness,
the top silicon uniformity,
and the BOX (Buried OXide – the insulating layer).

The thickness of the top silicon of the SOI wafers (denoted as TSOI) we provide ranges from 10 to 16nm, depending on customer requirements and node. The top silicon essentially “pre-defines” the channel. But, it’s important to remember that the starting thickness of the top silicon in the wafer has to be a little thicker than you’ll find in the processed device, as a few nanometers of top silicon is etched away during device processing.  So in a TEM of a 28nm FD-SOI transistor, you might see TSOI of 7nm, but the wafer that it started on would have had top silicon of 12nm, to accommodate the 5nm that would be etched away during processing.

In FD-SOI, the BOX layer is actively leveraged in back biasing, wherein you’re essentially creating a second (“back”) gate. This makes the parameters of the BOX layer especially important for ultra-low power operation.

ASN:  Why do the wafers have to be so uniform?

CM: With respect to the top silicon uniformity, uniform thickness is crucial to controlling transistor threshold voltage (Vt) variability. The top silicon uniformity of Soitec’s FD2D wafers is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. For the BOX thickness, we can offer thicknesses ranging from 10nm to 25nm, again depending on the customer’s approach.  Technology’s like ST’s UTBB (ultra-thin body and Box) leverage very thin BOX for body biasing, which gives them a big edge in performance and low-power.

ASN: Are suppliers really ready to produce these wafers in high volumes?
ST300mmFDSOIwafer

CM:   Yes, at Soitec we announced that we were ready for FD-SOI wafer volume back in 2012. Having met the specifications, we focused on offering good yields to our customers. In fact, the yield for Soitec’s FD-2D substrates is already reaching the yields we have for our wafers for partially-depleted SOI, which we’ve been selling for over a decade. This was critical to our clients, in order for them to have a fully-qualified 28nm FD-SOI process using wafers from Soitec and other suppliers. The results that customers have demonstrated in terms of variability (especially for Vt distribution, which is closely linked to wafer uniformity) and the electrical results show the wafers fully meet their production requirements. Smart CutTM technology enables us to manufacture according to these stringent requirements, and our years of experience let us move into high-yield, high-volume FD-SOI wafers at the right cost and at the right time for the market.

ASN: Can wafer suppliers adapt to the fluctuations in demand seen in very high-volume markets?

CM:  The SOI ecosystem is already familiar with the mobile market, which in terms of volumes is currently the world’s biggest market – and certainly is volatile. SOI wafers are widely used in RF, particularly in RF switches, where over 70% of the devices for smartphones are built on SOI.  While wafers for RF have some specific parameters, generally speaking the FD-SOI wafers are produced using similar technology, flow and logistics as our SOI wafers for RF – so for us, it’s just another segment of the mobile market.

ASN: Some say that managing buffer wafer stocks would be too complicated for the foundries – is that true? Can you explain briefly how the wafer supply contracts are typically structured?

CM: The SOI supply chain is no different than the bulk supply chain. As such, the structure of the wafer supply model is similar to supply chains in other industries. The foundries don’t have to fully own and manage a costly buffer stock of wafers. In the case of large customers, they typically negotiate a supplier-managed inventory dedicated to their needs, and they only pay when they actually consume parts from this stock.  This kind of buffer also helps smooth out possible rapid fluctuations of the demand.

ASN:  For its latest report (which found that FD-SOI is the most cost effective approach for the 28nm an 14nm nodes), IBS uses the figure of $500/wafer. Is that realistic?

CM: While of course pricing depends on commercial negotiations, 500USD in volume for 28nm FD-SOI wafers is definitely a sensible budgetary price: conservative and achievable. And starting at the 28nm node, as IBS points out, using SOI wafers results in similar cost for processed wafer when compared to typical 28nm bulk reference – a phenomenon that gets even better with scaling to 14nm. And although the specifications for the 14nm wafers are more exigent, we confirmed that substrate cost increase will not exceed 10%.

ASN: What about the future – will the wafers be able to meet the specs for the 10nm market? What about the move to 450mm wafers?

CM: ST has indicated a 3-node FD-SOI roadmap: 28nm-14nm-10nm. Working with our partners, we’ve shown that from the perspective of the wafer specs, we can fully comply with the parameters required to support this. For example, we have engineered strained silicon that meets the 10nm node specifications for boosting mobility – there are no show stoppers here. In terms of 450mm, while it seems unlikely that the move is imminent within the next few nodes, we are full participants in the industry’s R&D efforts, and have demonstrated that with our Smart Cut technology using the standard toolset found in CMOS FEOL, we can produce 450mm versions of our FD2D wafers, when and if the need arises. We’re ready whenever the industry is.

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