Part of the  

Solid State Technology


About  |  Contact

Archive for March, 2014

FD-SOI: Back to Basics For Best Cost, Energy Efficiency and Performance

Monday, March 31st, 2014

By Bich-Yen Nguyen and Christophe Maleville (Soitec)

We are in the era of mobile computing with smart handheld devices and remote data storage “in the cloud,” with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life.  With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer market.

The fully-depleted SOI device/circuit is a unique option that can satisfy all these requirements. Here’s how.

Demonstrated benefits

Planar FD-SOI benefits have been demonstrated by industry and researchers:

- Better immunity to short channel effects
- Lowest threshold voltage variation (because random doping fluctuation (RDF) is minimized, enabling a low operation voltage and improving the SRAM and analog mismatch)
- Low leakage and effective capacitance
- Better reliability
- Very importantly: multiple threshold voltage (VT) capability [1]. FD-SOI devices on ultra-thin BOX (UTBOX), as shown in Figure 1, address a major challenge of the undoped channel devices requirement for SoC applications.

Figure 1: Planar FD0SOI structure
(Courtesy: STMicroelectronics)

Simple FD-SOI Fabrication: Back to Basics

Starting at the 90nm node, to meet the performance, power and density needed to stay on track with Moore’s Law, the process complexity of integrated circuit fabrication has steadily increased. The adoption of new materials, new process/tools and lately new device architecture such as FinFET has resulted in a tremendous increase in wafer processing cost and design cost to extend the life of the bulk MOSFET.

In contrast, planar FD-SOI is simply fabricated with the basic front-end modules: trench isolation, well implants (for ground plane (GP)), gate stack, and source/drain with existing manufacturing CMOS processes.

Moreover, to provide multi-Vt capability for better trade-off of performance and power in bulk devices, both planar and FinFET require additional masks and processes for Vt tuning. The heavy channel doping resulted in large Vt variation due to RDF.  Planar FD-SOI on thin buried oxide (BOX), on the other hand, uses the combination of the work function of the front gate (defined by the metal gate stack) and ground plane (implanted under the box) for tuning Vt. The undoped nature of the FD-SOI channel is retained after the GP implant and the excellent thickness uniformity of the thin silicon film (1nm range) resulted in a lowest Vt variation.

The back bias is a unique feature of this device for ultimate Vt tuning, which further improves SOC energy-efficiency for mobile communications. The FD-SOI process saves several masks and process steps for Vt tuning. It also eliminates the additional masks and the processes needed to build-in the uniaxial stressors for boosting performance in planar and FinFET bulk [4,5].

As a result of integration simplification, Figure 2 shows FD-SOI charting a cost-effective manufacturing path to develop high-performance and lower-power CMOS technology for 28nm and beyond.

Figure 2: FD-SOI vs. Bulk CMOS & FinFET for performance and cost
(Source: Soitec research)

A second generation of 28nm FD-SOI, which implements source/drain engineering, delivers a 25% performance gain over the high-end 28nm high-K/metal gate (HKMG) bulk with slightly lower process wafer cost, or achieve the same performance as 20nm bulk but at the cost of 28nm HKMG. This new generation uses in-situ boron doped SiGe epi for PMOS and phosphorus or arsenide  doped Si or Si(C) Epi for NMOS, as well as forward back bias. Note that this is source/drain engineering – the channel remains undoped, so the advantage of FD-SOI in terms of avoiding RDF is maintained.

The 14nm planar FD-SOI can provide at least the same performance as 14/16nm FinFET-Bulk [7,8], but with much lower total processed wafer cost: approximately 20% lower.  STMicroelectronics has demonstrated, as shown in Figure 3, the performance versus total power comparison for 28nm FD-SOI versus bulk low power (LP) technology. The results show the 28nm FD-SOI with FBB achieved either 35% improved performance at the same total power or 49% total power saving with the same performance. [5]

Figure 3: Performance and Power benchmarking for 28nm FD-SOI vs. Bulk
(Courtesy: STMicroelectronics, ISSCC)

FD-SOI Scalability:  Revolutionary change

FD-SOI is an evolutionary innovation because it has the advantage of being a planar transistor that can use the existing design and EDA tools for early time to market. It is a cost-effective solution for consumer electronic applications.
Figures 4 and 5 describe the FD-SOI technology roadmap, design rule, device architecture and key processes/materials for 3 nodes: 28, 14 and 10nm, respectively [4,8].

Figure 4: FD SOI roadmap
(Courtesy: ST, Leti)

Figure 5: FD-SOI Device Integration for 3 generations: 28, 14 and 10nm
(Source: Soitec)

As FD-SOI technology scales, it is still able to meet density/area, performance and power saving requirements with the same device architecture, standard process module and silicon-based channel material and substrate. Thanks to the non-disruption nature of its change, the simplicity of the process integration and the excellent control of the thin silicon and BOX thickness, the processed wafer cost added per node is much lower than those of the other disruptive device/material changes currently proposed for SoC mobile and consumer applications.

FD-SOI uses the same EDA flow and design techniques as planar bulk, offering a low risk design and manufacturing path for extending Moore’s Law.  The industry’s first Fully-Depleted SOC using 28nm FD-SOI technology was demonstrated by STM/STE with 3GHz performance using low cost 28nm process [4,5]. 15 design-wins with 28nm FD-SOI have been announced by STM for different markets including consumer and networking, with more design wins in the pipeline [9].

In addition, FD-SOI devices with back bias can operate at voltages as low as 0.35V [5,10] without the area and cost penalties caused by the design complexity incurred in bulk devices. This makes FD-SOI technology an extremely attractive option for enabling the Internet of Things.

~ ~ ~
1.   O. Weber et. al., ” High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding”, in Proceedings of the IEDM 2008
2.   O. Weber et. al., “Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX” in Proceedings of the IEDM 2010
3.   F. Andieu et. al. “Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond“, in Proceedings of the Symposium on VLSI Technology (2010)
4.   J. Hartmann, “Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs”, Fully Depleted Transistors Technology Symposium, December 10, 2012 – San Francisco. See               
5.   P. Flatresse, in Proceedings of the SOI Short Course, S3S Conference, Monterey, October 2013
6.   Q. Liu et. al., “High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond” in Proceedings of the IEDM (2013)
7.   A. Khakifizoor et. al., “Strain Engineered Extremely Thin SOI (ETSOI) for High-Performance CMOS” in Proceedings of the Symposium on VLSI Technology (2012)
8.   L. Grenouillet et. al., “UTBB FDSOI scaling enablers for the 10nm node “, in Proceedings of the S3S Conference, Monterey, October 2013
9.   J. M. Chery PR
10.   H. Makiyama et. Al, “Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation” in Proceedings of the IEDM (2013)

Why Migration to FD-SOI Is A Better Approach than Bulk CMOS and FinFETs at 20nm and 14/16nm For Price-Sensitive Markets

Monday, March 24th, 2014

By Handel Jones

IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry.  The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within the next 24 to 60 months, covering the 28nm, 20nm and 14/16nm nodes.

We conclude that:

  • at 28nm and 20nm, the lower power consumption and higher performance of FD-SOI compared to planar bulk CMOS gives major competitive advantages to FD-SOI in high volume portable applications.
  • the lower cost of FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI for high volume applications at this technology node.

Here is a brief summary of our findings.


High volume applications need lower cost per transistor in order to use the new generation of process technologies. It is, consequently, appropriate to evaluate the options for continuing the pattern of lower cost per gate, with the analysis of different technology options.

After the 28nm node, the decreasing cost-per-gate trend with reduction in feature dimensions for bulk CMOS is reversed: at 20nm, cost-per-gate starts to increase rather than decrease.

Cost Per Gate Reduction Trends

The impact of not reducing cost per gate is one of the most serious challenges that the semiconductor industry has faced within the last 20 to 30 years. It is, consequently, appropriate to evaluate whether other options are available that can allow scaling to 20nm and smaller feature dimensions to be effective in cost and power consumption because of the large financial impact on the semiconductor industry of not continuing with Moore’s Law.

Wafer Cost Analysis
Our analysis considers depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.

Already at 28nm, the wafer cost is lower for FD-SOI than for bulk HKMG CMOS, although with a relatively small difference. The key reason for the lower cost of FD-SOI is the smaller number of mask and processing steps.

The cost analysis is based on eight-layer metal and 3Vt levels. The following graph is built from the more detailed analysis in our report.

Furthermore, while the difference in total yielded wafer cost at 28nm and 20nm is not very large, it is very important to remember that the FD-SOI technology has the added advantage of providing significantly lower leakage and higher performance than the bulk CMOS.

The reality is that performance of 28nm FD-SOI is 15% better than 20nm bulk CMOS and extends the lifetime of the 28nm technology node. Lower cost, lower power consumption, higher performance, the conclusions are clear.

The situation is even more compelling at 14/16nm.

The wafer cost for 14nm FD-SOI is 18.4% lower than 16nm FinFET.  A key factor contributing to the high cost of FinFET wafers is that of the extensive inspection steps required to ensure high yield and high reliability. A number of wafer processing steps need to be tightly controlled and monitored with the processing of FinFET structures. The result is that depreciation cost per wafer for FinFET structures is significantly higher than for FD-SOI.

Note: the generation we call 20nm FD-SOI in our report is called “14FD” by ST Microelectronics, as they also position it as a competitor to 14/16nm FinFET.

Die Cost

While wafer cost is an important factor, die cost is a more vital factor for most companies. Our analysis includes yielded wafer cost, gross die/wafer and yield.

At 28nm, FD-SOI has higher yield, slightly lower die cost (3%) and 30% lower power consumption than bulk CMOS. At 20nm, FD-SOI die cost is 13% lower than bulk CMOS, has higher yield, and is expected to provide 40% lower power consumption.
At 14nm/16nm, the FD-SOI die cost for a 100mm2 die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.

The lower cost of the FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI at this technology node.

However, despite the fact that FD-SOI is clearly more cost effective, large investments are being made by the pure-play foundries in 14/16nm FinFET wafer processes, and while FinFETs will be needed in the future, the issue is timing. It is clearly in the interest of the fabless industry to pay lower die prices, and collaboration with the foundry vendors is needed in this arena. The power structure in the industry has moved too much in favor of the provider rather than the user.

For the fabless industry, the key requirement for FD-SOI is to establish supply chains that can support the participation in high-volume end markets. The fabless companies need to be much more active in ensuring that their needs are being satisfied.

Strategic Considerations Within the FD-SOI Supply Chain

Strategic considerations within the FD-SOI supply chain include the following:

Complex, working products with FD-SOI at 28nm have been demonstrated by STMicroelectronics with significant performance and power consumption advantages compared to bulk CMOS.

The supply chain for FD-SOI starting (i.e., raw) wafers is in place (by Soitec, SunEdison, and Shin-Etsu Handotai (SEH)) and can be expanded rapidly to provide the required wafer capacity if a demand environment is established.

The use of body biasing provides significant performance and power consumption advantages for FD-SOI. Body-biasing methodologies for FD-SOI can use EDA tools that have been developed for bulk CMOS technology.  Also, design flows for FD-SOI are effectively identical to those for bulk CMOS. However, it is important for the EDA vendors to become more proactive regarding the potential opportunities for FD-SOI.

Libraries and basic IP developed for bulk CMOS can be easily modified for FD-SOI. The cost of modification between bulk CMOS and FD-SOI is approximately 10% of that required to migrate to a new technology node for bulk CMOS at 20nm.

An ecosystem needs to be set up for FD-SOI, and it is important for the electronics industry that this ecosystem is established.


There are many advantages for FD-SOI to be widely adopted for high volume, low cost, and lower power applications in the future. It is important for the semiconductor industry to be willing to make investments to provide optimum solutions to its customers rather than follow the roadmap of a specific company. The fabless companies need to be proactive in supporting the supply chain within an FD-SOI ecosystem.

Timing of the migration to 20nm, 14nm, and 10nm technology nodes need to be based on cost, power consumption, and performance metrics that can be easily verified. Being short-term focused and not willing to adopt new concepts can have large cost penalties within the foundry-fabless environment.

FD-SOI technology can be viable in many applications for the next ten years. The semiconductor industry needs to be willing to make the investments for the future rather than responding to short-term pressures.

Cost penalties resulting from very high design costs and long time-to-market can have a serious impact on the competitiveness of semiconductor vendors that select the FinFET approach at 14/16nm. Semiconductor companies that are participating in fast-moving markets cannot tolerate the additional costs of design and long time-to-market associated with trying to fine-tune technologies that are inherently high cost.

While migration to FinFETs may be required beyond the 10nm node, until then FD-SOI represents the best approach for many of the high volume segments of the semiconductor industry.

The reality is that the foundry vendors will not invest unless they have a high probability of getting customers. This means that the customers need to provide the leadership and accept that the present roadmaps in the industry will not provide them with the best financial returns.

FD-SOI Keeps Moore’s Law On Track

Thursday, March 6th, 2014

By Adele HARS

Take a look at this graph – it’s obvious, isn’t it? FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFETin the performance/power ratio, and keeps the industry on track with Moore’s Law.

This was part of a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during Semi’s recent ISS Europe Symposium.

If you’re a designer, and you want faster-cheaper-cooler, you’ll go with FD-SOI, right? You can leverage existing designs, it’s an easy port of IP, and you get terrific power-performance benefits from back biasing.

Which leads to the question: is FD-SOI really what’s best for the industry, too? From the designers’ and fabless perspective, it’s a clear “yes!”

Of course, the pure-play foundries clearly need the volumes to make FD-SOI worth their while. We all remember last year when this GloFo slide made the rounds (it was shown at the SOI Consortium workshop in Kyoto, Japan last summer – see the full ASN article here):

When I spoke to Subi Kengeri, GloFo’s VP Advanced Technology Architecture at a developers event this past fall, he said that GloFo was ‘s enthusiastic about the prospects for FD-SOI. But the foundry giant was still considering its options, while comparing FD-SOI to (bulk) FinFETs. While FD-SOI comes out a winner when leakage is the primary issue, he said, GloFo potentially sees a bigger opportunity in FinFETs.

This was last fall, remember, and he said that some customers had expressed reservations about the difficulty of back-biasing in FD-SOI. Now surely with all we’ve heard about the amazing things you can do with back-biasing in FD-SOI (click here if you need a refresher), nobody really thinks it’s hard anymore, do they?

So why should the fabless world swallow a major and very costly veer off the trend line of Moore’s Law just to do FinFETs at this point?

Subi told me, “We are a foundry and are here to serve our fabless customers.” He said if there is serious high-volume customer interest in FD-SOI, they can make it happen.

ST’s now indicated that a big foundry announcement will be made shortly, which is very exciting. (Read about that here if you missed it before.)

So, the foundries can make it happen.  And they will. Because maintaining cost-efficiencies is what makes this industry tick.  Ultimately, the best interests of the industry will always prevail. Just ask!

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.