Part of the  

Solid State Technology


About  |  Contact

Archive for February, 2014

FD-SOI, Body-Biasing Shine in 10X Faster DSP with Ultra-Wide Voltage Range

Monday, February 24th, 2014

Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here).

In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you do with your phone – snapping pictures, listening to music, watching video, oh yeah, even talking and listening –  involve the DSP’s number-crunching prowess. It takes real-world analog information that describes sound, pressure, light, and temperature and mathematically optimizes and processes them in real-time, so the data can be displayed, analyzed, compressed, enhanced, or converted. The DSP’s raison d’etre is to maximize work-per-clock-cycle.

When product designers talk about “user engagement” with their portable device, chances are there’s a DSP involved. And the better the DSP does its job, the cleaner your sound, the clearer your picture, the faster your download, and the more easily you can converse. But all this processing comes at a price – an energy price.  Chip designers are always looking for better ways to improve the power-performance trade-off, so that we as users get all this great performance without running out of batteries.

Power is directly proportional to clock frequency (MHz, GHz) and the square of the voltage that’s supplying the device. So, if you have a device that operates at higher frequencies with lower supply voltages, you’ve got a big edge on saving power – and of course, the less power you pull from your battery, the longer your battery will keep you snapping, listening, watching, and conversing.

That’s what’s at play here with this Leti/ST news. They’ve demonstrated a DSP that can hit 500 MHz while pulling just 460mV – that’s ten times better than anything the industry’s seen so far.

In fact, Fabien Clermidy, head of Digital Design and Architecture at Leti told ASN that this could mean extending your battery life by about another 30% for typical usages.

Leti and ST showed the FD-SOI DSP at ISSCC – the IEEE’s International Solid-State Circuits Conference (February 2014), which is widely considered the premier forum for presenting advances in solid-state circuits and SOCs.

Ultra-Wide Voltage Range

Specifically, at ISSCC Leti and ST presented the successful demonstration of an ultra-wide-voltage range (UWVR) DSP, based on 28nm ultra-thin body buried-oxide (UTBB = ST and Leti’s flavor of) FD-SOI technology.

This may be the first you’ve heard of Leti/ST’s UWVR, but it’s been making the conference rounds over the last year. Leti/ST presented it at the DATE Conference in 2013. (You can get the paper on the IEEEXplore site – click here.) In that paper, Leti and ST engineers demonstrated the technology on an ARM A9, where they showed performance boosted by 40% to 200% without added energy cost. Conversely, when saving power is more important than boosting performance (which turns out to be about 90% of the time!), FD-SOI reduced leakage power by a factor of 10 using Reverse Body Biasing.

Leti and ST also presented FD-SOI in the memories section at ESSCIRC ’13, where they applied it to a 28nm FD-SOI SRAM bitcell array, noting “…over 10x energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.” (This paper is also available from the IEEEXplore site – click here.)

In the case of the demonstrator DSP presented at ISSCC, the demonstrator was  produced by ST in their 28nm UTBB FD-SOI process technology. The UTBB FD-SOI allows:

  • body-bias-voltage scaling from 0V to +2V,
  • decreased minimum circuit operating voltage,
  • and clock-frequency operation of 460MHz at 400mV.

To the UWVR innovation, ST and Leti have added optimized standard-cell libraries they had developed to cover the 0.275V to 1.3V range. They then were able to leverage the voltage scaling they get with FD-SOI with system clocking techniques in the optimized cells, including:

  • non-overlapping pulses;
  • fast pulse-triggered flip-flop devices designed for variability tolerance at low voltage;
  • monitoring on-chip timing-margins to dynamically adjust the clock frequency to a few percent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology.

As a result, even at 0.4V, the DSP exhibits 10x better operating frequency than the previous state-of-the-art.

Clermidy also adds that their innovative design techniques reduced design margins, thus avoiding over-design. Again, doing this in FD-SOI rather than bulk was key, since FD-SOI really reduced variability issues.

The Leti/ST ISSCC paper, which is entitled, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented on Feb. 12, during Session 27, “Energy-Efficient Digital Circuits..  A demonstration kit was shown to attendees. As of this writing, it’s not yet been posted on the IEEEXplore site, but it should be in the weeks to come.

A New Open Foundry Source for FD-SOI? Soon, Says ST.

Monday, February 3rd, 2014

STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry.  This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.

While ST signed a licensing agreement with GlobalFoundries a year ago, it was not exclusive, Jean-Marc Chery reminded attendees. Chery is EVP and GM of the Embedded Processing Solutions (EPS) division.  The company has racked up 15 active designs in FD-SOI, including multiple design wins in ASICs for networking and consumer markets.

While they weren’t naming names, ST was very bullish about their prospects.  They expect FD-SOI to be a significant contributor to the goal of doubling the Digital Convergence Group revenues by Q415. Ramp to volume production begins in Q4 of this year, said Chery, noting with some clear pride that “FD-SOI has moved from a technology opportunity to massive revenue generator in 2015.”

The 15 wins are complex, high-volume, high-ASP products, he said, and there are lots more in the pipeline. They are major wins with major customers, and fall into two main categories:  network infrastructure and consumer.  He outlined why the two groups are choosing FD-SOI.

For the networking infrastructure customers, there are three major factors of merit:

1. FD-SOI gives them the right performance vs. power trade-off. This is especially true with FD-SOI’s wider flexibility vs. bulk and FinFET because of the greater Vdd range and forward body biasing, which increases energy efficiency and can modulate performance depending on equipment load, he said.
2. Analog performance – for high-speed communications, this is very important, and things like SERDES do much better on FD-SOI than FinFETs.
3. Reliability – especially for memory, where the extremely low error rate makes design of embedded memories and TCAM much simpler and efficient.

For the customers in consumer markets, he cited four things they especially like:

1. As with their confreres in the networking world, they like the performance/power trade-off.
2. But they also really like the low, low leakage in SRAMs, which is key for SOCs, where it’s an important part of the mission profile.
3. There’s huge flexibility in the usage – and when the transistors operate at very low voltages, power consumption is next to nil.
4.  FD-SOI is simpler than FinFETs.

Volume production of 28nm FD-SOI will be ramping in Q4 of this year. They will also soon be ready with 14nm prototypes, and he cited the groundwork laid by the alliance in Albany (with IBM, Leti, GF and Samsung).

Chery sees the volume ramp coming in two waves. After 28nm, the first will be 14nm for set-top boxes. ST, of course, is using FD-SOI in a new generation of chips for advanced set-top boxes based on 64-bit ARM cores (click here for more on that). The second wave will be more ARM-based solutions for complex, high-volume consumer apps.

Writing for Electronics360, Peter Clarke reported that Chery told him, “Crolles can support a selective list of customers that need high complexity and low- or mid- volume. ST will be the preferred manufacturer for those customers.”

Clark also reported that “Of the 15 design wins six are in the communications infrastructure category and 9 are for consumer applications and ST’s STB design is only counted as one of these.” One of the designs is running at 0.6V, he said.
In the course of his presentation, Chery also cited other SOI-based revenue boosters for 2014, including RF-SOI and silicon photonics.

So, we’re looking forward to getting the name of the major foundry that will be both a second-source for ST, and will open up FD-SOI to the industry – watch this space!

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.