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Archive for January, 2014

SOI: Looking Back Over a Year of Moving Forward Part 2

Tuesday, January 21st, 2014

As we noted in the previous post (click here if you missed it), 2014 should be a terrific year for the greater SOI community.

But before we look forward (which we’ll do in an upcoming post), let’s continue considering where we’ve been and some of the highlights of the last year.  In fact, there was so much happening in 2013 that it’s taken two posts – the previous was about FD-SOI; in this post we’ll review RF-SOI and SOI-FinFETs.

The RF-SOI Juggernaut

SOI for front-end RF solutions rapidly gained ground throughout the industry in 2013, with announcements by Peregrine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth.

In April, SemiconductorEngineering reported that part of Qualcomm’s RF360 front-end solution is on SOI, a “shot across the bow”, according to StrategyAnalytics.

In June, ST announced a new manufacturing process, known as H9SOI_FEM, for production of complete integrated front-end modules.

In October, Toshiba chimed in with a new RF-SOI product announcement, noting that it had been using SOI for RF since 2009.

In November, Peregrine Semiconductor announced that it has shipped its 2 billionth RF chip, released version 10 of its UltraCMOS RF-SOI technology, and is working with GlobalFoundries.

In December, SOI wafer leader Soitec announced that they’re in high-volume manufacturing of a new flavor of SOI wafers for advanced RF apps like LTE/4G. In fact, these new wafers are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications.  Developed with UCL, they’re called Enhanced Signal Integrity™ (eSI) substrates, and enable cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production.

14nm SOI-FinFETs Get Real

In November, IBM posted a piece in ASN entitled FinFET on SOI: Potential BecomesReality. The IBM team shared impressive hardware data for 14nm SOI-FinFETs.  SOI eliminates the need for doping, they remind us, which enables FinFETs to attain unsurpassed threshold voltage (Vt) matching between transistor pairs. (Vt is the point at which a transistor switches on or off.)

They found, on top of the well-documented improvements in Vt matching for logic and SRAM devices, an even more dramatic matching improvement for thick-dielectric devices. These are used for analog and IO devices, and also in DRAM — where this opens the door to various optimizations and enables fundamental area scaling.

For the classic 6T SRAM, improved Vt matching means you can lower the minimum operating voltage. For their SRAM array, the IBM team showed minimum operating voltage down to 400mV, with full read and write capability. That’s as good or better than any yet reported, and it was done without using chip-specific tuning techniques. The bottom line: real SOI-FinFET SRAMs can operate at very low voltages.

Manufacturing a FinFET on SOI also enables a more ideal fin profile.  In turn, this near-ideal shape delivers performance well in line with the “theoretical”  benefits of FinFET technology. It avoids the need for the more tapered shape seen on bulk FinFETs that trade-off some electrical performance for manufacturability.

IBM’s results exhibit excellent correspondence between the actual hardware and the expectations, which include far less dependence on the supply voltage than conventional planar technology.

The various pieces contributed to ASN by IBM about SOI-FinFETs are amongst our all-time most popular posts. We’ve also shared some of them with the folks over at SemiMD, where they continue to generate enormous interest.

So we’ll look forward to hearing more about SOI-FinFETs in 2014, too!

SOI: Looking back over a year of moving forward (Part 1: FD-SOI)

Monday, January 13th, 2014

2014′s going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise.

But before we look forward (which we’ll do in an upcoming post), let’s consider where we’ve been and some of the highlights of the last year.  In fact, there was so much happening that we’ll review 2013 in two posts – this post is about FD-SOI; in the next post we’ll cover RF-SOI and FinFETs.

Highs, lows, and the promise of an extra day

It was just a year ago that you read in the first ASN post of 2013 about ST-Ericsson’s NovaThor™ L8580 ModAp: at 2.5GHz it was “the world’s fastest and lowest-power integrated LTE smartphone platform” at CES ’13 in Las Vegas.  Then in February in Barcelona ST announced that its 28nm FD-SOI technology clocked in at 3GHz, but what was really amazing was that it got 1GHz using using just 0.6V VDD, aka the “supply voltage”, which is the main voltage “in” that powers the chip. No one had been able to run stably on that low a voltage before.  28nm FD-SOI got you a full extra day before you had to recharge your device.

But then of course came the sad news that the plug was pulled on ST-E. Happily the technology moved into the ST fold, and the 28nm process is now ramping in volume, with 14nm is set to debut shortly.

May was a big month. ST’s FD-SOI got the EETimes ACE Award for Energy Technology – and the company announced it had started winning FD-SOI customers. We also got the news of a big public-private funding boost, to the tune of €360M, for the Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe). It is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL. A 3-year public-private project involving 500 engineers from 19 members in seven countries, it’s looking to enable volume manufacturing in Europe from 28nm down to 10nm.

Also in May, Leti told us that they’d gotten silicon layers down to 3.5nm, and for boosting pFETs with SiGe, were seeing better results with FD-SOI than bulk FinFETs. What’s more, they found that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!

In August, the French government upped the ante with a 600 million Euro investment in the Nano2017 program, which was in addition to the 3.5 billion Euros that ST and partners had already pledged, bringing the total to 4.1 billion Euros (about $5.4 billion).

In October, Leti said it would have the 10nm FD-SOI PDK ready in June of 2014.

In November, the wafer supply chain got a boost when SOI wafer suppliers Soitec and SunEdison (formerly MEMC) ended their longstanding legal feud and entered into a patent cross-license agreement.

At IEDM in December Leti announced UTSOI2, a compact model for electrical simulations. Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers use before they run silicon. Dedicated to Ultra-Thin Body and Box (UTBB) FD-SOI technology, UTSOI2 accurately describes independent double gate operation for sub-20nm nodes. Also at IEDM, ST, Leti, IBM, Renesas, Soitec and GlobalFoundries presented the big paper showing great results for 14nm FD-SOI.

So 2014 promises to be an excellent year.  Stayed tuned – next up we’ll review the great strides made in RF-SOI and SOI-FinFETs.


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