Part of the  

Solid State Technology

  Network

About  |  Contact

SOI Highlights at Common Platform Tech Forum

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

~  ~

The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a live stream (which is now reposted – click here to register and watch it yourself).

The Common Platform Alliance is IBM, Samsung and GlobalFoundries, operating, as IBM’s Dr. Gary Patton points out, as a “virtual IDM”.

Here’s a round-up of the SOI-based highlights.

DR. GARY PATTON, VICE PRESIDENT OF SEMICONDUCTOR RESEARCH & DEVELOPMENT CENTER, IBM

In his keynote address, Gary covered the following SOI-based innovations:

Flexible computing with FD-SOI. (Courtesy: IBM, Common Platform Technology Forum 2013)

  • FinFETs: As ASN readers know, IBM is driving FinFETs very hard. With ARM & Cadence, they taped out their first 14nm FinFET processor last fall (on SOI). Gary’s talk gave an overview of the evolution of device structures, including PD-SOI (the basis for IBM’s Watson supercomputer), FD-SOI, FinFETs and future structures and materials.
  • Wearable electronics & folding displays – IBM has developed a new, low-cost technique that starts with the FD-SOI technology developed with ST and Leti, for manufacturing silicon-based electronics on a flexible, plastic substrate. Gary showed a sample, and said that “research suggests that flexible, affordable electronics can be made with conventional processes at room temperature.”
  • Silicon nanophotonics – most all of the industry’s nanophotonics work is on SOI, and IBM is no exception here.  As Gary notes, “…the key innovation isn’t just the technology…it’s the fact that it’s commercial and scalable…”.
  • Carbon nanotubes breakthrough – IBM has attained 10,000 working nanotube transistors on a single device using standard semiconductor processes.  As we noted in ASN when this news broke last fall, IBM researchers fabricated trenches made of hafnium oxide onto SOI wafers, which allows the self-assembly by the carbon nanotubes into neat rows rather than a spaghetti-like tangle.

As seen here, carbon nanotubes start on an SOI wafer. (Courtesy:IBM, Common Platform Technology Platform 2013)

MIKE NOONEN, EXECUTIVE VP, GLOBAL SALES, MARKETING, QUALITY & DESIGN, GLOBALFOUNDRIES.

In Mike’s keynote on particularly innovative customers, he covered ST’s FD-SOI technology.  Here are the main points he made about it:

  • STMicroelectronics has been a partner in the Common Platform.
  • FD-SOI leverages 80% FEOL of the 28nm SLP; the BEOL is identical to 28nm LP.
  • “You can really dial-in optimal transistor performance,” he said.  The thin silicon channel introduces “interesting and exciting capabilities”, including:
    - lower leakage, lower capacitance, enhanced latch-up immunity, electrostatic control;
    - speed boost through back biasing;
  • This technology is a simpler planar process:
    - reduced masks offsets cost;
    - considerable IP reuse.
  • With a nod to Soitec, the world-leader in SOI wafers, he said, “Soitec has been a really enthusiastic evangelist of this technology, and I really want to acknowledge their efforts in making Fully-Depleted over SOI something that the industry has become very excited about.”  He added that they’re joined by MEMC and SEH as SOI substrate suppliers.
  • Regarding the roll-out, he concluded, “A PDK of this technology is available this quarter, and GlobalFoundries has partnered with ST for volume manufacturing and will be entering risk production in the 4th quarter of 2013, with volume production in the first half of 2014.”

GlobalFoundries’ keynote highlights FD-SOI. (Courtesy: GlobalFoundries, STMicroelectronics, Common Platform Technology Forum 2013)

HANDEL JONES, OWNER & CEO, INTERNATIONAL BUSINESS STRATEGIES

In a “fireside chat” with Brian Fuller, Silicon Valley Bureau Chief, EETimes, Handel Jones touched on a number of SOI-related topics.  (In case you missed it, Handel recently wrote an excellent article for ASN on FD-SOI vs. Bulk & FinFET economics.) In addition to his general discourse on the impact of design & process issues on cost/gate, the importance of the ecosystem, and general industry outlook, here are some of Handel’s SOI-related observations during the forum chat:

  • RF: he is particularly impressed with IBM’s work on RF, which he says is “…doing extremely well.”  As you may have seen previously in ASN, IBM’s CMOS 7RF SOI technology, which the company says offers significant cost advantages to designers of mobile handsets, has been on SOI for over five years.
  • FD-SOI: When asked about any single, major disruption on the horizon, he noted that designing with FinFETs for mixed signal is tough, so there may be a delay there.  However, FD-SOI looks very positive, he says. He sees FD-SOI offering lower power, lower cost/gate, re-usable IP and scalability to 14nm.

~~

Leave a Reply