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Archive for May, 2012

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

Wednesday, May 30th, 2012

The following is a special guest post by Dr. Chenming Hu, TSMC Distinguished Professor at UC Berkeley. He and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). This post first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization


The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges have been increasing over time, they’ve finally gotten painful enough that the industry is ready to embrace new transistor structures.

The essence of the problem is that the leakage current does not flow along the Si-oxide interface, but nanometers below the interface  when the gate lengths (Lg) becomes very small. That leakage path is physically far from the gate even if the oxide were infinitely thin. The gate cannot shut off the leakage as if the oxide were nanometers thick. Essentially the MOSFET becomes a resistor. Ioff and variations got worse and worse with Lg reductions.

The solution is new MOSFET structures, in which there is no Si far (more than nanometers) from the gate(s). In other words, the transistor body must be ultra thin. Body doping becomes optional.

Both FinFETs and FD-SOI devices are ultra-thin-body transistors. As such, compared to traditional planar bulk CMOS, they both provide:

  • Higher speed and lower leakage
  • Lower supply voltage (Vdd) and power consumption
  • Further scaling and lower cost
  • Better sub-threshold swing and scaling
  • No random dopant fluctuation (RDF), less variability
  • Better mobility, especially for future sub-threshold design


The FinFET body is a thin fin and the thin body is controlled from three sides instead of just the top.

FinFET is easy to scale because leakage is well suppressed if the fin thickness is equal to or less than Lg. Thin fins can be made with the same gate patterning/etching tools.

While our original FinFET work was on SOI wafers, a few years later (2003), Samsung presented a way to manufacture them on bulk substrates. There is an advantage to continued use of  bulk substrates; however, FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance.

When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing. The choice will be made by performance and comparisons.

Planar FD-SOI

Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon.  When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.

However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.

The FD-SOI approach can save the fabs and designers significant investment. Existing chip designs and associated IP can be ported with minimum effort, starting today at the 28nm node.

While FinFETs have a larger Ion, FD-SOI has a good back-gate bias option, which make it particularly interesting for low-power applications.


This is a very exciting time for the industry. Although it may seem that the industry is splitting into FinFETs and FD-SOI camps, both approaches use body thickness as the new scaling parameter, and can use undoped body for high performance chips without RDF. Both allow MOSFETs to be scaled beyond traditional MOSFET’s limit. And both can derive substantial benefits from SOI wafers. Real choice is good news because competition will bring the best out of both new transistor technologies.

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Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET

Thursday, May 24th, 2012

The following is a special guest post by Steve Longoria, Senior VP of Worldwide Business Development at Soitec.  It first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.


Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to the market and our customers. With traditional CMOS reaching the end of life as demonstrated by the struggles to ramp 28nm in high yields and the unattractiveness of 20nm’s specifications and costs, the entire semiconductor industry is looking to fully-depleted transistor structures as the path forward.

But if FinFETs and other fully-depleted multigate structures only get started at the 14nm node in an open foundry offering, what do we do between now and then?  It is this gap in technology and timing that Soitec identified several years ago in working closely with our partners to develop the right solutions at the right time with the right economics.

Having worked in close collaboration with an ecosystem of manufacturing and design partners, Soitec has announced availability of advanced wafer substrate products that bridge the gap.  We have wafers for both of the industry’s fully-depleted approaches: planar and three-dimensional (which includes FinFET and other multigate devices). By pre-integrating critical characteristics of the transistor within the wafer structure itself, we’re helping our customers significantly improve their products, accelerate time-to-market and simplify manufacturing processes resulting in lower cost and better SOCs.

As such, our fully depleted (FD) roadmap offers an early, low-risk migration path starting at the 28nm node extending the cost, power and performance advantages down to 10nm and beyond leveraging both our FD-2D and FD-3D product families.

Lowering costs and enabling significant advances in the performance and power efficiency are especially important for makers of mobile devices such as smartphones and tablets.  Our data indicated that the cost savings our wafers enable in the overall manufacturing process more than compensate for the wafer cost delta.  We’ve done our homework, and are priced for high-volume manufacturing with aggressive cost points.

The FD-2D Product Line – Next-generation Power Efficiency and Performance, Now

While the 28nm node on bulk CMOS is proving more difficult than anticipated, 20nm is looking downright ugly.  Yield, cost, power and performance are all well off what would be expected from a next generation technology.

Soitec’s FD-2D wafer product line enables a unique planar approach to bring forward fully depleted silicon technology as early as the 28nm node and put scaling back on track. With planar FD technology (often referred to as FD-SOI), chipmakers can continue to leverage their existing planar designs and process technologies through the 14nm node.  The result is cheaper, higher-yielding, higher-performance, lower-power chips.

Manufacturers use the same fab tools and production lines, and extremely similar process steps (just fewer steps). At 28nm, compared to conventional technology, the energy consumption of chips built on our FD-2D wafers can be reduced by up to 40 percent, and the maximum operating frequency of the processors these chips embed can be improved by 40 percent or more with design optimizations. In addition, exceptional performance is maintained at very low power supply (sub-0.7V), enabling ultra-low-power operation in many use cases.

With respect to the wafers, silicon thickness uniformity is critical for best results. Leveraging the inherent accuracy of Soitec’s Smart Cut process, silicon uniformity across a full 300mm-diameter wafer can be as good as 3.2 Angstroms. To give you an idea of just how uniform that is, consider that it corresponds to about 5mm (less than a quarter of an inch) over the distance between Chicago and San Francisco.

Between this top layer and the underlying silicon base is an ultra-thin layer of buried oxide. Substrates targeting the 28nm node are using 25nm-thick buried oxide (BOX). Future generations can leverage even thinner BOX layers down to 10nm thick providing a path for planar transistor scalability down to 14nm for mobile devices.

In addition to delivering all the power and performance benefits, the chipmaker’s bottom line for manufacturing devices on our 2D-FD wafers is a lower cost SOC.

The FD-3D Product Line – Simplified & Accelerated  Manufacturing

FinFET and other multigate (“3D”) device architectures offer enormous promise in terms of cost, power and performance.  But a major shift like this is always accompanied by a major learning curve.

Targeting the nodes below 20nm, Soitec’s FD-3D product line will shorten the learning curve, facilitating the introduction of 3D architectures with reduced time and investment. Because our FD-3D substrates drive substantial simplifications in the transistor fabrication process, experts estimate that they will confer a potential gain of as much as one year with respect to the trajectory possible using conventional bulk silicon substrates.

Compared to using conventional bulk silicon starting wafers, our FD-3D wafers result in fewer challenging steps in the FinFET fabrication process, driving lower capital expenditures and operating expenses, higher production throughput and ultimately lower cost. Typical savings include four lithography steps and over 55 process steps.

Using a “fin-first” approach, chip manufacturers can count on the top silicon layer to predefine the fin height, and the BOX layer to provide built-in intrinsic isolation.  This results in excellent variability control:  because there is no need for channel doping and the fin height and profile is better controlled, the electrical behavior of all transistors is kept close to nominal.

Beyond simplified manufacturing, Soitec’s FD-3D wafers deliver the benefits of lower leakage than bulk silicon wafers (thanks to the buried layer of isolation) and better chip-level power-performance-area trade-off.  And – very importantly – because they are functional at lower supply voltages (VDD), the resulting chips consume significantly less power.

Through the process simplifications, enabled by our FD 3D wafer, we provide reductions in R&D investments and accelerating time to market for FinFETs.  The benefits of the simplified process play forward into ongoing cost and cycle time benefits when we transition into a manufacturing mode for FinFETs, resulting in lower cost SOCs built on FD-3D from Soitec.

Soitec, in tight collaboration with our partners, has the right products at the right time at the right economics to accelerate the semiconductor industry’s migration to fully depleted transistors, starting now.

Looking Further Down the Roadmap

Soitec also is working actively to propose new ways to further boost transistor performance, both silicon-based and with new materials. To continue pushing the performance of silicon CMOS, we’ll add “strained silicon” to both our FD-2D and FD-3D product lines, with pre-production expected no later than 2014. With this solution, the crystalline structure of the silicon layer, in which transistors will subsequently be built, is modified by Soitec during fabrication of the starting wafers. This results in significantly improved electron mobility and higher maximum operating frequency for the transistors and circuits.

Looking further, several new CMOS technology options are being researched in the semiconductor industry for introduction beyond the 14nm node. The main candidates include incorporation of high-mobility materials such as germanium or III-V materials, as well as new transistor architectures such as nano-wires. Soitec is actively engaged in industry R&D programs and has a number of joint development programs with partners to enhance our product lines and propose the best products to meet evolving needs.

Finally, Soitec is also anticipating the transition from 300mm to 450mm wafers through in-house and collaborative R&D programs to support the industry roadmap. Both the FD-2D and FD-3D offerings are fully scalable to 450mm.


Steve Longoria is Senior VP of Worldwide Business Development at Soitec, the leading manufacturer of SOI and other advanced wafers. Prior to this, his experience includes 18 years at IBM, where he was VP of the Common Platform group.