ST-Ericsson NovaThor This Year, 28nm FDSOI, Soitec Wafers
By Adele Hars, Editor-in-Chief, Advanced Substrate News
Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson’s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry’s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers.
Soitec has just issued an official press release, but ST-Ericsson President-CEO Didier Lamouche had already heralded the news to analysts at the Barcelona Mobile World Congress last month. (You can see/hear the presentation here.)
His Slide 29 from the Barcelona event pretty much says is it all:
This architecture is essential in implementing transistor technology that solves – with less process complexity – the scaling, leakage and variability issues that are associated with shrinking CMOS technology from 28nm to 14nm.
ST-Ericsson’s planar FD-SOI technology is supplied by STMicroelectronics. As Lamouche said in his presentation, “The world needs to go fully-depleted.” Choosing this flavor of fully-depleted, planar SOI technology (as opposed to a 3D fully-depleted technology such as FinFETs) puts ST-Ericsson a full two-years ahead of the competition, he estimates.
With the NovaThor platform, ST-Ericsson’s been wracking up some nice wins lately – with Samsung, Nokia and Sony, to name a few. So this is a high-volume endeavor.
Wafer manufacturer Soitec has been working on these wafers with key partners for years. The wafers for planar FD-SOI require an extremely thin and incredibly uniform (+/- 5 Angstroms!) layer of silicon on top of a very thin layer of insulating buried oxide (BOX). Soitec sells them under the banner “FD-2D”; they’re now ready to roll in volume.
“We are positioned to provide the volume of qualified wafer manufacturing required to enable the industry to speed the adoption of planar fully depleted technology into mainstream mobile applications,” says Soitec COO Paul Boudre.
In case you missed it, STM went into significant detail on the advantages of the technology and announced a 28nm product line at the SOI Consortium’s recent FD-SOI workshop (see Important News Comes Out of Recent FD-SOI Workshop in ASN online).
The key planar FD-SOI advantages cited by ST-Ericsson include:
- a fully-depleted architecture that is cost-competitive with bulk
- simplified processing (10 percent few steps)
- 35 percent lower power consumption at maximum performance
- big performance boost – double (!) when supply voltage is at 0.6V
- designers can leverage powerful back-biasing techniques to further boost performance or lower power
- it’s processed with standard fab tools
(Look for more about these and other features in a soon-to-be-published white paper.)
From the Soitec announcement, here are the key quotes from the parties involved:
ST-Ericsson’s chief chip architect Louis Tannyeres: “Next-generation mobile consumer devices will need to deliver an even better user experience and higher performance without sacrificing battery life. Together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with ST on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions.”
STMicroelectronics’ assistant general manager, Technology R&D, Joël Hartmann: “STMicroelectronics and its partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology, and ST has recently demonstrated the strong differentiation of this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28nm and below. This combination makes FD-SOI particularly suitable for wireless and tablet applications where it essentially provides the fully depleted transistor benefits of FinFETs on a planar conventional technology, while allowing advanced back bias techniques, which are not available with FinFETs. We are delighted that it could be adopted by ST-Ericsson for their next generation of products.”
Soitec’s COO, Paul Boudre: “FD provides a low-risk option for semiconductor companies such as ST-Ericsson that are seeking to take advantage of the benefits of a fully depleted transistor architecture while leveraging existing design and manufacturing capabilities.”
Clearly this is a very significant and exciting moment for the industry. It’s the first major fully-depleted announcement since Intel/FinFETs. Might it be the first shot across the bow in the next round of the transistor wars?