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Archive for March, 2012

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead

Tuesday, March 27th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications.

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The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.

Armed with the information from the 28nm bulk vs. FD-SOI benchmarking study, the SOI Consortium members then did new benchmark simulations at the 20nm node. This confirmed the trends they saw in silicon at 28nm. When comparing FD-SOI technology to bulk technology specifically intended for System-on-Chip (SOC):

  • Peak performance was improved by 12 to 30 percent at constant total power, depending on design optimization efforts,
  • Low-Vdd (0.7V) performance was improved by 65 to percent,
  • Total power was reduced by 22 to 40 percent at constant maximum operating frequency.

Here’s the graphic that says it all. Follow the suggestions in the annotations to see how the power vs. performance trade-off works.

By adjusting Back Bias, FD can be changed from: High Performance Mode TO Leakage Saving Mode

To use this graph: pick any point on the lower, bulk line, then move horizontally to the left to see how much less power it will take to hit the same frequency with FD-SOI.

(a) Reverse back-bias allows you to cut leakage, here by a factor of 10
(b) This line is 20 nm FD-SOI with back biasing
(c) Or with back-biasing FD-SOI, you can hit over 269 MHZ using 120 mW at 1 V power supply

(1) This line is 20 nm Bulk
(2) This line is 20 nm FD-SOI
(3) Bulk takes over 130 mW to hit frequency of about 223 MHz with supply voltage of 1 V
(4) To hit the same with FD-SOI takes just over 100 mW and a supply voltage of just 0.9 V

(Courtesy: SOI Consortium)

About the study

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this blog.

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance

Wednesday, March 21st, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications.

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Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technology, and can be on SOI or bulk) and other Multi-gate (MuGFET) devices each having compelling advantages in their favor.

Designers are considering the power and performance needs of their applications, assessing the manufacturing risks and evaluating the importance of extending current IP – which makes FD-SOI a very strong contender for current and upcoming nodes.

The recent SOI Industry Consortium announcement indicated that FD-SOI handily beats traditional planar CMOS devices built on bulk-silicon substrates even at 28nm.

28nm: FD-SOI saves power, boosts performance

The Consortium benchmarked 28nm bulk vs. 28nm FD-SOI, so they could make comparisons in silicon of representative IP blocks, such as ARM cores and memory controllers. Here are some of the potential implications of what they’re saying.

• Peak performance is comparable with the much leakier ‘General Purpose’ technology flavors, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology flavors achieve.

FD-SOI peak performance is comparable to that of GP, and significantly better than LP (low power) technologies.

The dynamic power gap, however, gets better and better as you can reduce the power supply voltage (i.e. when you’re not shooting for extreme operating frequency) — because the drop in performance when the supply voltage Vdd is lowered is much less marked with a fully-depleted technology.

The trick is, 1) not all portions of an SOC need highest possible performance and 2) even those that do need that performance only a fraction of the time — when running very demanding scenarios.  So when you consider the dynamic power at chip level across use cases, then your overall dynamic power is dramatically better.

This also means, if you have a chip in bulk technology (LP or G)  that runs fine in terms of performance but you’d like to cut its total power, then planar FD-SOI is a great solution.

• The feasibility of running all digital device designs, including SRAMs, at very low Vdd (e.g., 0.6 volt).

One of the great problems of traditional bulk CMOS is that SRAM memories quickly become unstable if their Vdd is reduced.  Being unable to reduce Vdd, you cannot lower their power consumption even when you don’t need maximum access speed from them. By contrast, fully-depleted technologies enable you to operate both logic and SRAM at reduced Vdd.

• The opportunity for substantial power savings of up to 40 percent by using a lower Vdd to reach the same target frequency.

AND

• Much better performance than bulk CMOS when the power supply (Vdd) is lowered. At 0.6V, critical paths on 28nm FD-SOI circuits were more than 50 percent faster than the General Purpose technology and more than twice as fast as Low Power technology;

With respect to dynamic power consumption (the power lost in switching), it’s proportional to the square of Vdd. So if you reduce Vdd and still hit the target frequency, you get a big savings in dynamic power consumption.

Leakage power – AKA static power – is the power lost when sub-threshold currents wander away even when the  transistor is off.  It’s the major cause of wasted power in standby mode.  The Consortium study found that FD-SOI does better than both G and LP bulk technologies at 28nm in terms of leaky transistors.

About the study

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study.  The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Editor’s note: Special thanks to the SOI design experts who helped with the explanations in this blog. Look for Part 3 of this blog series on the SOI Consortium results soon.

ST-Ericsson NovaThor This Year, 28nm FDSOI, Soitec Wafers

Wednesday, March 14th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson’s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry’s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers.

Soitec has just issued an official press release, but ST-Ericsson President-CEO Didier Lamouche had already heralded the news to analysts at the Barcelona Mobile World Congress last month. (You can see/hear the presentation here.)

His Slide 29 from the Barcelona event pretty much says is it all:

Slide 29 from ST-Ericsson’s Analysts & Media Briefing at Mobile World Congress in Barcelona (28 February 2012)

This architecture is essential in implementing transistor technology that solves – with less process complexity – the scaling, leakage and variability issues that are associated with shrinking CMOS technology from 28nm to 14nm.

ST-Ericsson’s planar FD-SOI technology is supplied by STMicroelectronics.  As Lamouche said in his presentation, “The world needs to go fully-depleted.” Choosing this flavor of fully-depleted, planar SOI technology (as opposed to a 3D fully-depleted technology such as FinFETs) puts ST-Ericsson a full two-years ahead of the competition, he estimates.

With the NovaThor platform, ST-Ericsson’s been wracking up some nice wins lately – with Samsung, Nokia and Sony, to name a few. So this is a high-volume endeavor.

Wafer manufacturer Soitec has been working on these wafers with key partners for years. The wafers for planar FD-SOI require an extremely thin and incredibly uniform (+/- 5 Angstroms!) layer of silicon on top of a very thin layer of insulating buried oxide (BOX). Soitec sells them under the banner “FD-2D”; they’re now ready to roll in volume.

“We are positioned to provide the volume of qualified wafer manufacturing required to enable the industry to speed the adoption of planar fully depleted technology into mainstream mobile applications,” says Soitec COO Paul Boudre.

In case you missed it, STM went into significant detail on the advantages of the technology and announced a 28nm product line at the SOI Consortium’s recent FD-SOI workshop (see Important News Comes Out of Recent FD-SOI Workshop in ASN online).

The key planar FD-SOI advantages cited by ST-Ericsson include:

  • a fully-depleted architecture that is cost-competitive with bulk
  • simplified processing (10 percent few steps)
  • 35 percent lower power consumption at maximum performance
  • big performance boost – double (!) when supply voltage is at 0.6V
  • designers can leverage powerful back-biasing techniques to further boost performance or lower power
  • it’s processed with standard fab tools

(Look for more about these and other features in a soon-to-be-published white paper.)

Key Quotes

From the Soitec announcement, here are the key quotes from the parties involved:

ST-Ericsson’s chief chip architect Louis Tannyeres: “Next-generation mobile consumer devices will need to deliver an even better user experience and higher performance without sacrificing battery life. Together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with ST on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions.”

STMicroelectronics’ assistant general manager, Technology R&D, Joël Hartmann: “STMicroelectronics and its partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology, and ST has recently demonstrated the strong differentiation of  this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28nm and below.  This combination makes FD-SOI particularly suitable for wireless and tablet applications where it essentially provides the fully depleted transistor benefits of FinFETs on a planar conventional technology, while allowing advanced back bias techniques, which are not available with FinFETs. We are delighted that it could be adopted by ST-Ericsson for their next generation of products.”

Soitec’s COO, Paul Boudre: “FD provides a low-risk option for semiconductor companies such as ST-Ericsson that are seeking to take advantage of the benefits of a fully depleted transistor architecture while leveraging existing design and manufacturing capabilities.”

Clearly this is a very significant and exciting moment for the industry. It’s the first major fully-depleted announcement since Intel/FinFETs. Might it be the first shot across the bow in the next round of the transistor wars?

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FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line

Monday, March 12th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights.

STMicroelectronics

In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line based on planar FD-SOI at the 28nm node this year. Prototypes will be ready in June.

The objective, he said, is “…to have a compelling technology offer for the mobile application processor speed race.”

And compelling it is: their 28nm FD-SOI technology performances is 61% higher than comparable bulk technology at 1V. It gets even more interesting at lower Vdd – boasting a 550% improvement at 0.6V.

Slide 32 from ST's presentation, 28 & 20nm FDSOI Technology Platforms, given at the SOI Consortium's 6th FD-SOI Workshop (Feb. 24, 2012).

Check out the presentation – it’s got excellent descriptions, detailed roadmaps (look for products on 20nm FD-SOI in 2014), and clear comparisons. Topics include:

  • 28FDSOI positioning vs. bulk technologies
  • Design methodology and EDA flow
  • From spice models to product: migration methodology from Bulk to FDSOI
  • Biasing techniques on FDSOI
  • FDSOI ST design environment
  • 20FDSOI development track

ARM

In FD-SOI Design Portability, Betina Hold, Senior Principal for Silicon R&D at ARM in San Jose emphasized the ease of porting existing designs from bulk to FD-SOI.

FD-SOI, she concluded, is perfect for high-performance, low-power mobile apps.

Here are the main points she made:

Slide 29 from ARM's presentation, FDSOI Design Portability, given at the SOI Consortium's 6th FD-SOI Workshop (Feb. 24, 2012).

(You can also read ARM’s perspective on the ease of porting from bulk to FD-SOI in a recent ASN article by the company’s Director of SOI Technology, Jean-Luc Pelloie.)

IBM

There were two presentations from IBM, addressing the two major flavors of fully-depleted architectures on SOI: planar FD-SOI, and FinFETs on SOI.

The presentation entitled Recent Advances in FDSOI given by Bruce Doris, Manager of Device Integration at IBM Research, reviewed various device structures. He presented new data indicating that FD-SOI performance is competitive for high performance and at a much shorter gate lengths (Lg), and will scale well beyond 20nm.

FINFET on SOI presented by Terence Hook, Senior Technical Staff Member at IBM, compared with both clarity and depth the characteristics and manufacturability of FinFETs on SOI and bulk with other SOI and bulk structures.

Leti

In a very in-depth presentation, FDSOI strain options FDSOI for 20nm and below, Olivier Faynot, who leads the Innovative Devices Lab at CEA-Leti, demonstrated how most of the existing techniques used on bulk technology are compatible with FDSOI. However, he emphasized that FDSOI devices already meet high performance requirements, especially at the circuit level. A unique feature of FDSOI for future nodes, he noted, is that strained SOI wafers (sSOI – wherein the top layer of silicon is strained at the wafer level) are particularly effective in giving NMOS a boost  (Ion NFET 1.4mA/µm – PFET 1.2 mA/µm @ Ioff 100nA/µm).

Soitec

Enabling Substrate Technology for a Large Volume FD Standard, presented by Christine Pelissier, Director of Business Operations at SOI wafer manufacturer Soitec, gave a broad view of the both the technological and volume supply requirements for the wafers. Soitec is now manufacturing wafers for FDSOI in which the top silicon is controlled to within +/-5 angstroms.

She looked both at the wafers used in FDSOI as well as the partially depleted (PD) SOI wafers which have been in high-volume production for over a decade. She then went on to explain the key features in wafers for planar FDSOI (which Soitec refers to as FD2D) and in wafers for SOI-based FinFETs (FD3D).

Slide 8 from Soitec's presentation, Enabling Substrate Technology for a Large Volume Fully Depleted Standard, given at the SOI Consortium's 6th FD-SOI Workshop (Feb. 24, 2012).

Other highlights

Two presentations are not available online. Brian Chen of Agilent (Accelicon) presented 20nm ETUTBB-FDSOI Rev3 Models. (Note that 20nm FD-SOI logic evaluation model cards are now available through SOI Consortium in cooperation with Accelicon/Agilent. An NDA is required.)

Professor Borivoje Nikolic from UC Berkeley presented Microprocessor Design in FD-SOI. This showed their design of a Planar FDSOI microprocessor that will be taped out later this year.

In all, this 6th workshop acknowledged the reality of Planar FDSOI technology starting with the 28nm node. There were plenty of relevant questions and discussions, confirming the promise FDSOI holds as a cost-effective and reliable solution.

As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve been offering these workshops for over two years,” he said. “The community has taken Fully Depleted SOI from a technical advantage in the lab to a technical advantage on mobile products (as presented by ST). The cost, power, performance and manufacturability of FD SOI is a significant driving force.”

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FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing

Monday, March 5th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking of planar FD-SOI.

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Chipmakers constantly have to manage risk.  Generally it is sensible not to try to engage in more than one major change at a time – geometry shrinks already introduce enough headaches.  So planar FD-SOI devices, which use proven, well-understood design and manufacturing techniques should be particularly appealing for both current and upcoming nodes.

Horacio Mendez, executive director of the SOI Industry Consortium noted that FD-SOI  also represents a low risk in terms of manufacturing for upcoming nodes.

“FD-SOI’s ability to accommodate planar architectures presents much lower manufacturing risk than FinFET,” he said. “This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers.”

For many if not most designers, extending the life of existing planar bulk CMOS designs will make good sense.  With a planar FD-SOI solution, these existing designs and related IP can be migrated in a comparatively straightforward way, producing chips that benefit from the intrinsic advantages of fully depleted wafer technology with minimal risk and lower cost.

(There was an excellent piece in ASN from ARM SOI guru Jean-Luc Pelloie on the logistics and ease of porting from bulk to FD-SOI a few months ago – click here to read it.)

The SOI Consortium also points out that FD-SOI is compatible with all power-reduction techniques used by IC designers – and can even boost the efficiency of some. Furthermore, FD-SOI can accommodate some design tweaks (not available with FinFET designs), such as leveraging dynamic back-bias to increase performance or reduce leakage power in some applications.

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About the study:

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies participated, each tackling different aspects of the study. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability – key for both designers and foundries.

Next –  Part 2 of this blog series on the SOI Consortium study looks at FD-SOI from a power & performance perspective.


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