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Archive for November, 2011

FD-SOI bests FinFETs for mobile multimedia SOCs? ST says yes.

Tuesday, November 29th, 2011

In a recent and excellent article in ASN by Thomas Skotnicki, Director of the Advanced Devices Program at STMicro, he explains in a very clear and accessible way why FD-SOI with ultra-thin Body & Box (UTBB) is a better solution for mobile, multimedia SOCs than FinFETs — starting at the 28nm node and running clearly through 8nm.  It is based on the paper he presented at the 2011 IEEE SOI Conference.

In case you missed it in Advanced Substrate News, here it is again.


ST: FD-SOI for Competitive SOCs at 28nm and Beyond

By Thomas SKOTNICKI, Advanced Devices Program Director, STMicroelectronics

The multi-functional system-on-chips (SOC) needed at the heart of the next generations of wireless, high-performance, low-power multimedia devices have very different needs than the mono-functional processors of the past. Traditionally, the trade-off for computers and servers has been accepting high operational voltages (Vdd) and high stand-by leakage in return for high-performance. This is obviously not an acceptable trade-off for mobile internet devices.

In a mobile world, high-performance must go hand-in-hand with low-operation Vdd and low stand-by leakage. That requires different technologies. As we approach the 20/22nm node and beyond, traditional planar-bulk technologies cannot meet these requirements. The choice comes down to either a planar fully-depleted (FD) SOI solution or a FinFET solution. At STMicroelectronics, we call our flavor of planar FD-SOI UTBB, for ultra-thin body & box. As such, it leverages SOI wafers with both ultra-thin top silicon and ultra-thin buried oxide (BOX). Where more practical, we use a hybrid SOI/bulk configuration, wherein certain devices are placed in the bulk silicon that has been exposed by etching back the insulating BOX layer.

The results we’ve obtained make UTBB a compelling option.

Designing a good SOC involves using the right blend of low-, standard- and high-threshold-voltage (Vth) devices according to the target application and how it’s being used at any given time. Our FD-SOI technology can handle multiple Vth devices and I/Os through a cost effective approach, solving challenges for low-power operation (LOP), low-standby power (LSTP) and analog and high-performance (HP) needs.

UTBB at 28nm

ST’s UTTB technology may be a good candidate even for the 28nm node, as it would provide a boost in speed before 20nm bulk technology is ready. Therefore, we have explored an industrial solution for its implementation.

Our objectives that we met for FD-SOI at the 28nm node were as follows:

  • Demonstrate with respect to 28 LP Bulk :
    • + 30% Performance at same Vdd (1V)
    • or 40% lower power consumption for at least the same performance
  • Demonstrate feasibility of “easy” porting from Bulk to FD-SOI
  • Demonstrate manufacturability (including SRAM yield) of FD-SOI/UTBB (with 7nm top silicon thickness and 25nm buried oxide thickness)

FD-SOI/UTBB structure (Courtesy: STMicroelectronics, IEEE SOI Conference 2011)

With respect to porting the design, the goal of “easy” porting means:

  • the design only needs recharacterisation of critical paths
  • FD-SOI masks are redefined from Bulk by CAD2MASK.
  • Spice models are available for all devices

The process flow is derived from 28LP Bulk of the ISDA Alliance: Metal Gate First and no stressors. Out of 15 major process modules in the Front-End of Line, only 3 are specific to the FD-SOI process. The number of masks is similar to 28 LP Bulk (actually with a saving of 2 or 3, which could be used for analog adjustments in Hybrid bulk/SOI parts if needed).

More than 25 implant steps are saved vs. 28nm LP Bulk for two Vths. This eliminates 15% of the process steps and results in a process cost saving of 10%. So as long as the SOI substrate cost overhead is less than 10% of the bulk process cost, the FD-SOI process is more cost-effective than the bulk LP process.

It is worth noting that the relative impact of the substrate cost will be more favorable to FD-SOI at subsequent nodes, since the process becomes more complex on bulk and adds more metal levels.

DIBL: the SOC performance metric

The drive current, Ion, has long been the key metric for speed in high-performance microprocessors. But, especially for multimedia SOCs, the effective current Ieff is a much better metric and is heavily dependent on DIBL (Drain Induced Barrier Lowering). The lower DIBL of UTBB transistors reflects their superior electrostatic control and leads to higher performance. The influence of DIBL on maximum operating frequency is more pronounced for higher Vths and/or lower Vdd, which explains why this parameter is crucial for low-power multimedia SOCs – which use higher Vths than high-performance microprocessor chips.

Vth adjustment and Performance Results

The means to adjust Vth constitute a fundamental difference between bulk and FD-SOI devices.

On short devices in bulk, Vth is controlled primarily by channel doping. Vths for logic and SRAM can be adjusted independently.

In FD-SOI, however, Vth is controlled primarily by the gate stack on short and long devices in both logic and SRAM. By also playing upon channel length and ground plane implant below the BOX, we are able to obtain all the Vths we need for our 28nm FD-SOI technology. According to its type (n or p), the ground plane (GP) can shift Vth up by more than 50mV (in the case of our 25nm BOX). GP implants also suppress the depletion depth below the BOX for better DIBL, and improve the effect of body biasing.

Body bias is a powerful performance booster usable at different Vdd points — at low voltages, for example, speed is increased by 30%. The Ion/Ioff trade-off is not hurt (body-biasing simply shifts the operating point along the technology’s Ion/Ioff curve), even for body bias voltages up to 2V. This flexibility is not available with FinFET, and while body bias is possible with planar bulk, at 28nm it is of limited practicality and effectiveness.

We then compared the 28nm FD-SOI to a 28nm bulk low-power-oriented ‘LP’ process and to different performance-oriented ‘G’-type processes, on a DDR3 Memory Controller.

The results indicated FD-SOI had:

  • comparable performance to the “G”-type processes at high Vdd, with additional room for overdrive (and without the complexity of ‘G’-type processes)
  • overall best performance across all practical Vdd values
  • a competitive advantage at low Vdd, with over 40% performance advantage over ‘G’ at 0.6V power supply
  • best power efficiency

Additional benchmarking on an ARM Cortex-A9 is confirming these results.

20nm goals

We want to propose a differentiated technology at 20nm node providing a 20% boost in performance versus 20LPM at the same Vdd. We also want it to be competitive versus a potential Trigate SOC at 22nm.

Under our 20nm UTBB FD-SOI scheme, performance will be boosted by dynamic control of a Full-Forward Body Bias (F-FBB) architecture. Vth modulation sources will include gate stack, ground-plane, counter-doping, body-bias and L poly-bias.

We have now compared our FD-SOI with bulk and FinFETs at 20nm, with impressive results. While FinFETs and UTBB FD-SOI very much resemble one another (in fact, a UTBB device looks rather like a FinFET tipped on its side), with FD-SOI we are seeing:

  • a large gain in performance: 42% at 0.9V and 98% at 0.7V
  • best performance
  • G-like performance on an LP process
  • best power efficiency

(Courtesy: STMicroelectronics, IEEE SOI Conference 2011)

Work by Leti and by IBM and partners also shows excellent SRAM transistor matching. UTBB was also found to have much lower threshold voltage variability, thanks in large part to the undoped channel. This in turn enables smaller SRAM cells and/or lower minimum voltages (Vmin) – a gain of 150mV, which translates into significantly lower power consumption. We have determined that the SRAM remains fully functional as low as Vdd=0.4V.

14nm to 8nm

An FD-SOI roadmap through 14nm indicates an orderly and logical progression. Leti has shown that further thinning of the insulating BOX layer enables FD-SOI scalability down to 8 nm with top silicon thickness (TSi) no thinner than ~ 6-7nm (post-processing).

Soitec’s Xtreme SOI wafers with ultra-thin BOX (25nm) is ramping to volume this year, targeting the 28nm node. With SEH and a third supplier on tap, the supply chain is in place.

2Onm FD-SOI vs FinFET: summary table (Courtesy: STMicroelectronics, IEEE SOI Conference 2011)

Straightforward Move to 28nm

ST has been working on FD-SOI for over 10 years. We have research programs or partnerships on 3 sites : Crolles, Leti, and IBM Albany NanoTech. We have collaborated with Soitec for wafer supply.

The key technology elements for UTBB have been demonstrated.

The move from R&D to an industrial process of 28nm FD-SOI technology is for us (and for our partners) an efficient and straightforward response to the world-wide competition. The extension of FD-SOI towards the 20nm and 14nm nodes is also in preparation with new boosters to further increase the performance growth rate.

UTBB FD-SOI promises to give STMicroelectronics a significant edge in both the near term and for years to come.


This article was adapted from “Competitive SOC with UTBB SOI”, T. Skotnicki et al, presented at the 2011 IEEE SOI Conference.  It was first posted in Advanced Substrate New on November 18, 2011.

ARM: Bulk ports directly to FD-SOI

Thursday, November 17th, 2011

In a recent ASN posting, ARM Fellow Jean-Luc Pelloie said that bulk logic designs can be ported directly to fully-depleted (FD)-SOI for high-performing, low-power mobile apps.

ARM sees fully-depleted FD-SOI is a potential alternative to BULK 20nm.  Jean-Luc addressed the question of  what sort of impact a port from bulk FD-SOI would  have on the design flow. His answer is: very little.

Jean-Luc’s article recaptures a  presentation he gave at the recent IEEE SOI Conference.  In case you missed it in ASN, here it is again:

Bulk logic designs for mobile apps port directly to FD-SOI

By Jean-Luc PELLOIE, Director of SOI Technology, Fellow, ARM

Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of increased performance and decreased power when ported to 20/22nm fully-depleted (FD)-SOI. From the designer’s perspective, the port is essentially direct – really no different from any standard port to a smaller geometry.

Interconnects, routing and RC parasitics are identical. Logic, memories, low- and high-voltage I/O and analog parts are handle in the same way as on bulk. Where there are differences, they are more at the device/process level, and do not pose any particular challenges to the designer at this point. This includes SPICE models, antenna effect, ESD protection, I/O and analog, and back-gate bias.

ARM uses standard packages from the leading EDA vendors in SOI ASIC design

20nm FD-SOI v. 28nm Bulk

To get some clear figures on power and performance, ARM recently ported a Cortex-M0 from 28nm bulk to 20nm FD-SOI.  We used the Cortex M0 implementation flow that was proven in 22nm SOI. This included:

  • synthesis, place and route, and the same reduced set of standard cells for 20nm FD-SOI and 28nm bulk
  • parasitics extraction for interconnects from the routed 22nm SOI M0 core (22nm SOI Back-End Of Line (BEOL) is considered to be the most representative of current bulk/FD-SOI 20nm BEOL)
  • characterization of 20nm FD-SOI and 28nm bulk standard cells (typical process corner and room temperature)
  • different voltages to create the corresponding .lib files that would be used for timing and power analysis of the M0 core: 0.7, 0.8, 0.9 and 1V
  • timings and power were compared for the routed M0 core based on 20nm FD-SOI and 28nm bulk characterizations (.lib).

ARM, 2011 IEEE SOI Conference

Source: ARM, 2011 IEEE SOI Conference

In any next-node port, you typically expect to get a 25% improvement in performance, but in porting from 28nm bulk to 20nm FD-SOI, FD-SOI boosted the improvement far beyond the expected 25%. At a Vdd (supply voltage) of 1.0V, we saw a 40% improvement in performance. At 0.9V, we saw 66%. For Vdd of 0.8, we saw an 80% improvement. And for Vdd of 0.7, we saw an improvement of 125%.

Power is consistently reduced by 30%, and leakage holds steady.

Remember, this is a straight port, which gives us a baseline figure. There are several powerful process and design optimization techniques that can boost those numbers even higher without significantly increasing the complication factor.

Existing design, tremendous results

The conclusions we have drawn are that:

  • a standard bulk ASIC design flow can be used for FD-SOI – don’t expect any change
  • an existing bulk logic design can be directly ported to FD-SOI
  • you just need to check the timing closure – there is no timing variability (this is not PD-SOI)

FD-SOI should give tremendous advantages in terms of both power and performance. These low-voltage, high-performance chips are perfect for low-power applications, with the undoped channel in the low voltage SRAM resulting in higher margins. For some applications, RF features will also be improved if designers choose high-resistivity substrates.

FD-SOI is all a designer needs for high-performing, low-power mobile applications. And happily from the designer’s point of view, FD-SOI is as simple as designing in bulk.


This article was adapted from “FDSOI Design Portability from BULK at 20nm Node”, which was presented at the 2011 IEEE SOI Conference.