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Archive for October, 2011

SOI Conference Shows SOI Driving Key Roadmaps

Friday, October 21st, 2011

By Adele Hars, Editor-In-Chief, Advanced Substrate News

2011 IEEE SOI Conference logoThe 2011 IEEE SOI Conference, held in Tempe, AZ last week was not one to miss…but I did. Happily, I got the papers right away, along with observations shared by some of the folks who did get there. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at the heart of many a roadmap.

Consider some of the plenary talks.

First was Competitive SOC on UTBB SOI by Thomas Skotnicki of ST Microelectronics.  This was a detailed presentation on ST’s vision for planar fully depleted (FD) SOI (which he described as equivalent to a FinFET rotated by 90 degrees). Here are some of  the key points:

  • ST’s FD objectives are +30% performance at Vdd 1V and +40% at Vdd – 0.1
  • The FD Process saves 10% cost over the equivalent bulk process, mainly because there are 25 fewer implantations steps.
  • The process options for 28, 20, and 14nm were detailed.
Jean-Luc Pelloie, Director of SOI Technology, ARM

Jean Luc Pelloie, Director of SOI Technology, ARM, presenting at the 2011 IEEE SOI Conference.

Next up was FDSOI Design Portability from BULK at 20nm Node by Jean Luc Pelloie of ARM. Jean Luc, who is ARM’s Director of SOI Technology, described how a Cortex M0 implementation flow was proven in 22nm SOI. He emphasized that the design migration to FDSOI is straightforward in terms of EDA flow: the interconnects routing, parasitics are identical, and FDSOI transistors’ electrical behavior is similar to bulk transistors.

There’s no floating-body effect, no history effect, no timing variability, he reminded attendees. Logic and memories are identical. That said, further optimization can be done to account for different electrical features at the device level. The few differences specific to FDSOI are not design related but more process/device related (SPICE models, antenna effect, ESD protection, potential parasitic bipolar, and back-gate bias).

Look at the results ARM’s seeing:

ARM Cortex-M0 performance comparison 28nm bulk and 20nm FDSOI.

Cortex-M0 benchmark – performance comparison between 28nm bulk and 20nm FDSOI. (Courtesy: ARM, 2011 IEEE SOI Conference)

As SOI Consortium Director Horacio Mendez pointed out in ASN this summer, you typically expect to get about a 25% improvement in performance moving to the next node. But ARM’s showing that if you move to the next node and move to FD-SOI, you get really phenomenal results, especially at the lower supply voltages.

In the Hot Topics Session, Bruce Doris (IBM) announced new High Performance values for FDSOI in his presentation on The Future of SOI Transistor Technology:

  • At Vdd 1V, for Ioff 100nA, he reported NFET Ieff 0.82 and Isat 1.4 mA/um
  • At Vdd 1V, for Ioff 100nA, he reported PFET Ieff 0.68 and Isat 1.2 mA/um

Integration of photonics and electronic circuits on SOI was the subject of both Yuri Vlasov’s (IBM) plenary talk, and Juthika Basak’s (Intel) Short Course.

A half-dozen excellent presentations by Leti during the short course and invited papers explored FD-SOI from many perspectives, including scaling paths, properties and challenges/solutions.

Papers from Peregrine and Soitec showed some impressive results for their new mass-produced bonded silicon-on-sapphire (BSOS) wafers for RF applications. In Strain Reduction in Silicon-on-Sapphire by Wafer Bonding BSOS films showed 56% higher electron mobility than traditional SOS; and RF switch performance in BSOS was better than GaAs PHEMTs.

J.P. Raskin (UCL), who’s doing some fascinating work, presented Sensing and MEMS Devices in Thin Film SOI MOS Technology.

And finally, a team from MIT/Lincoln Labs once again slipped in a tantalizing concept in their late paper submission entitled SOI Circuits Powered by Embedded Solar Cell.

Here’s a link to the program. I’ll cover more of the papers presented at this conference in upcoming PaperLinks articles.  But clearly, the 2011 IEEE SOI conference was an excellent one.


Many thanks to Nicolas Daval and Christophe Didier of Soitec for their help on this blog entry.

Ultra-thin wafers for 450mm FD-SOI on schedule

Monday, October 3rd, 2011

By Adele Hars, Editor-in-Chief, Advanced Substrate News

While much of the focus on the impending move to 450mm has focused on the equipment challenges, the wafers themselves are of course the primordial consideration. Predictions are starting to mount up linking the move to 450mm with a move to fully-depleted silicon-on-insulator (FD-SOI). So the question needs to be asked: will the wafers be ready?

Engineered substrates like SOI wafers need to be ready years in advance of any major shift in technology – and before much of the rest of the materials and equipment. The fabs and foundries as well as the entire design chain – need real wafers they can work with early on to meet R&D and testbed needs – plus to ensure that volume ramping goes smoothly when the time comes.

450mm wafers for FD-SOI are on target for the industry’s current 450mm deployment plans. (If you want some more info on FD-SOI, see the related blog.)

The current buzz says that 450mm will coincide with the 14nm technology node – around 2015. That’s actually not all that much time for such a big shift – pilot lines will have to be in place in just a couple of years.

FD-SOI requires SOI wafers with very thin top silicon, and current trends also include a very thin layer of insulating buried oxide (BOX). Soitec, the leading SOI wafer manufacturer, is currently in volume ramp for the 300mm version of its Xtreme SOI wafers for FDSOI, shipping thousands of samples every month (wafer giant SEH is producing them, too). In synch with the industry rollout, wafers for 450mm FD-SOI will be ready on schedule, too.

450mm FD-SOI wafers

Both 300mm and 450mm SOI wafers with ultra-thin top silicon and ultra-thin insulating buried oxide (BOX) will ramp to high-volumes on target with the industry's schedules. (Courtesy: Soitec)

Soitec makes wafers of all sizes using their industry-proven Smart Cut(TM) technology. They’ve used it in high-volume production of SOI wafers for over a decade, so there are no surprises there. (To see how they do it, see their ASN article, FD-SOI: The Substrates Are Ready.)

Under the aegis of the European 450mm Equipment and Materials Initiative – or EEMI 450, for short (which we covered last year in ASN), the EV Group and Soitec worked together on the requisite wafer bonding equipment for 450mm SOI wafers. The first system is being delivered to Soitec’s manufacturing facility near Grenoble this fall for test and qualification.

EVG says the EVG850SOI/450-mm runs at production line speed and comprises a cleaning module and pre-bonding module.

So to recap, it’s all systems go for FD-SOI – first for 22nm/300mm, then for 14nm/450mm. FD-SOI is:

  • comparable to FinFETs (which can be bulk or SOI) in terms of speed gain and low-power performance
  • turn-key, and easily manufacturable, both in terms of the technology and the wafers
  • a simpler solution than bulk FinFETS in terms of the design platforms
  • cost competitive and superior to planar bulk CMOS in terms of power-performance

And it will keep right on going through 11nm. The ball is clearly rolling.


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