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Great FD-SOI Start for 2016: Samsung, GF, Renesas, NXP/Freescale, ST, Soitec

February 5th, 2016

By Adele HARS

Just a month into 2016 and we already have a raft of FD-SOI news from Samsung, GlobalFoundries, NXP/Freescale, Renesas and more. And of course RF-SOI continues ever stronger.

logo_soiconsortiumHere’s a quick update of what we’ve been seeing, starting with news from the recent SOI Consortium forum in Tokyo. Many of the presentations are now available on the SOI Consortium website – but keep checking back for more.

Samsung: 28nm FD-SOI hits maturity, mass production starts 1Q2016

Yongjoo Jeon, Principal Engineer in SEC Foundry marketing, Samsung, gave a talk entitled, The industry’s first mass-produced FDSOI technology for the IoT era, with single design platform benefits.

Here are his key messages with respect to 28nm FD-SOI:

  • The technology, which was qualified in 2015, is now ready for mass production, with the first commercial production set for 1Q2016.
  • Yield levels are excellent.
  • There were 12 tape-outs in 2015 in connectivity, security, games, set-top boxes, application processors for consumer and automotive, plus CMOS image sensors (aka CIS — for an excellent explanation of why FD-SOI is right for CIS and why leaders in this arena are considering it, see Junko Yoshida’s recent EETimes piece here).
  • The 16 tape-outs planned so far for 2016 expand to a wider range of automotive apps, plus we see the first in IoT and wearables, MCUs and programmable devices.
  • A production PDK for a version of 28nm FD-SOI with RF integration will be available in 2Q16.
  • eNVM (embedded non-volatile memory) will be ready in 2018.

For other key Samsung slides showing data on their success in manufacturability, check out EETimes.

GlobalFoundries: RF-SOI for 5G, FD-SOI Customers Engaged

Subramani Kengeri, VP of Global Design Solutions at GlobalFoundries talked about their 22nm FD-SOI, in his presentation Enabling SoC Innovations with 22FDXTM. He indicated that they’ve got over 40 customers engaged on it. Key points they’re hitting on that make them bullish on their prospects include:

  • FinFET-like performance and energy efficiency at 28nm cost
  • Ultra-low power consumption with 0.4V operation
  • Maximum flexibility in power/performance trade-off with software-controlled body biasing
  • Integrated RF cuts RF power in half and means designers don’t need an extra RF chip.
  • They’ll reach high-volume production by the middle of 2017.

For more on how GF see 22FDX as very well-positioned for IoT, see their Foundry Files blog. There’s also a really good piece in EEJournal by Byron Moyer entitled, A Non-FinFET Path to 10 nm – GlobalFoundries’ FD-SOI Alternative.

GF is of course also a dominant RF-SOI player, as seen in RFSOI: Defining the RF-Digital Boundary for 5G by Peter Rabbeni, Sr. Director RF Product Marketing and Business Development, GlobalFoundries. The presentation, which is available on the SOI Consortium website, notes that, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results,” so that, “SOI holds great promise in delivering on the key requirements of 5G systems.” (For an overview of GF’s RF-SOI position, see RF-SOI is IoT’s Future, and the Future in Bright on their Foundry Files blog.)

Renesas: in FD-SOI production at 65nm this year

Shiro Kamohara, Chief Engineer, Renesas Electronics Corp., lead off the presentations with Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era.

Nikkei article reported from the conference that Renesas will be in mass production of 65nm FD-SOI – which they call Silicon-on-Thin-Box, or SOTB – for IoT products this year. Renesas reports the move cuts power to a tenth of what they’d seen in bulk. You can see the original article in Japanese here or a translated version here.

Soitec: wafers ready for mass adoption

Soitec_SOIsourcing

In the presentation Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms, Soitec Sr. VP of Digital Electronics Group Christophe Maleville, Senior Vice President, Digital Electronics BU provided data on every conceivable aspect of SOI wafers for FD-SOI and RF-SOI. He explained adaptations in the company’s Smart CutTM manufacturing technology that achieve astonishing levels of uniformity and thickness – or rather, thinness! With new metrology, they can predict and protect against variability in devices. And they are now producing FD-SOI wafers for 28nm processes with uniformity of +/- 1 atomic layer.

ST: making the case

For analog/RF, RF/mmW and mixed-signal/high-speed designers, Andreia Cathelin, Senior Member of Technical Staff at STMicroelectronics explained how and why FD-SOI makes their lives easier. Her presentation, FDSOI Technology Advantages for Analog/RF and Mixed-Signal Designs drills down to the technical for these folks.

Pietro Maestri, ST’s RF Product Line Director presented ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration. (BTW, we had an excellent high-level article by ST when H9SOI_FEM was first announced, describing the challenges faced by designers of smartphone front-end modules (FEMs) and how their H9SOI_FEM solves them – read it here.)

For anyone wondering about the status of FD-SOI following the just-announced company reorganization, COO Jean-Marc Chery told EETimes’ Peter Clarke that they remain fully committed to the technology. As noted in the article (read the whole thing here), “Chery emphasized that, following the announcement of ST’s withdrawal from STB and home gateway markets and of a proposed redeployment of 600 engineers, the company is now focused on automotive and Internet of Things applications and that therefore FDSOI is a core manufacturing process. Indeed it could be argued that moving engineers familiar with FDSOI from the STB group into MCUs and automotive will help to proliferate the technology through the company.”

NXP/Freescale: Loving FD-SOI

In another recent EETimes article, Peter Clark reported from the NXP “Smarter World Tour” that the newly merged NXP-Freescale is very bullish on FD-SOI (see the full article here).

He cites Goeff Lees, the GM for the MCU part of the merged businesses, who especially likes 28nm FD-SOI for IoT and MCUs. Ticking off the reasons, he lists energy efficiency, cost, analog support, security, temperature control and lower leakage current. In fact, he says, “I believe all MCU vendors could move to FD-SOI.” Wow.

So stay tuned – here at ASN we’ve got contributions from NXP/Freescale, Synopsys, GlobalFoundries, Surecore and more at the top of the 2016 queue. Yes, it’s going to be a good year.

The Ever-Expanding 28nm FD-SOI Ecosystem (Samsung Interview, Part 3 of 3)

December 24th, 2015

By Adele HARS

For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)

ASN: Let’s talk a little more about IP availability.

Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.

Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.Samsung_28FDSOI_IP_reuse_14

ASN: In terms of the ecosystem, what remains to be done?

KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.

AF: Especially as you have good support for RF/analog functionality. So, this ecosystem becomes quite important.Samsung_28FDSOI_enablement_11

KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.

As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.

ASN: Any closing thoughts?

KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.

Samsung_28FDSOI_future_15

~ ~ ~

This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).

When to Choose 28nm FD-SOI And Why (Samsung Interview Part 2 of 3)

December 22nd, 2015

By Adele HARS

For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)

ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?

Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.

Samsung_28FDSOI_lowpower_knobs_13

Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.

Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.

ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?

KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.

Samsung_28FDSOI_Vdd_9

Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.

KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.Samsung_28FDSOI_PPA_7

ASN: Can designers get started today?

KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.

Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.

There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.

ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.

KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.

Samsung_28FDSOI_bodybias_8

FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.

There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.

AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.

ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?

KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.

Samsung_28FDSOI_apps_6

AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.

KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).

Yes, 28nm FD-SOI Silicon Is Running (Samsung Interview, Part 1 of 3)

December 19th, 2015

By Adele HARS

ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 1, we’ll talk about technology readiness. In parts 2 and 3, we’ll talk about design and the ecosystem.

ASN: Where does Samsung stand in terms of rolling out your 28nm FD-SOI offer?

Kelvin Low: We have completed key milestones. Wafer level qualification was completed in September 2014, and then product level qualification in March 2015. So, the good news is the technology is fully qualified now.

What we have additionally in terms of overall technology readiness is production PDKs available right now. We have run a couple of MPWs already, and we’re scheduling more for next year. Silicon is really running in our fab. I think many may not have grasped that fact. Silicon is running, and we are running production for ST as one of our lead customers.

Samsung_28FDSOI_PDKS_12

Axel Fischer: We already have a long relationship with ST – since 32 and 28nm HKMG bulk. We had a press release where we stated that more than a dozen projects had been taped out. EETimes published an article at the time. Adding 28 FD-SOI was a natural extension of an existing relationship

KL: That’s right –This is not a new customer scenario – it’s an existing customer, but an expansion of technology. And, in this case, it’s also a collaboration technology and IP solutions.

We are ST Micro’s primary manufacturing partner; this is one reason that it’s mutually beneficial for both of us. Crolles is not aiming for high volume. They prototype well. They do MPW and IP well, but they are not a high-volume fab. So, we complete the production rollout at Samsung Foundry.

ASN: Do you have other customers lined up?

KL: The short answer is yes. Beyond ST, Freescale can we talk about, since they have openly stated that they are using FD-SOI with us. Other customers, unfortunately, we just can’t say.But, they are in all the market segments (especially IoT) where the cost and ultra-low power combination is a very powerful one.

ASN: What about technology readiness and maturity?

KL: We have a couple of different 28 variants: the LPP, the LPH with more than a million wafers shipped. And because of that, our D0 – defect density – is at a very mature level. 28FD-SOI, sharing almost 75% of the process modules of 28 bulk, allows us to go to a very steep D0 reduction curve. We are essentially leveraging what we already know from the 28 bulk production experience. Defect density is essentially the inverse of yield. So, the lower the D0, the higher the yield.

Samsung_28FDSOI_process_costThis slide [[see above]] show the similarities between our FD-SOI and our 28 HKMG bulk. You can see how more than 75% of bulk modules are reused. The BEOL is identical, so its 100% reused. On the FEOL, some areas require some minor tuning and some minor modification, but anything that is specific to FD-SOI is less than 5% that we have to update from the fab perspective. All the equipment can be reused in the fab. There may be a couple of pieces related to the FD-SOI process that need to be introduced.Other than that, the equipment is being reused and can depreciated,.which is essential for any business. We leverage another lifetime for the tools.

ASN: When will we see the first high-volume FD-SOI chips? Next year?

KL: It depends on what market segment. Consumer, yes, I fully agree, they can ramp very fast. But other segments like infrastructure, networking or automotive, they’ll take a longer time to just qualify products.

AF: It’s not just us. If our customer needs to prove that the product is compliant with certain standards, you have to go through test labs and so on, this can be a very lengthy process. Product can actually be ready, and we’re all waiting to produce, but they’re still waiting for reports and the software that’s goes on top – this can be a very long cycle.

KL: We’re already starting to support the production ramp for ST. They’ll be on the market very soon.

[[Editor’s note: ST has announced three set-top box chips on 28nm FD-SOI– you can read about them here.]]

Samsung_28FDSOI_wafersAF: ST is our first partner for high-volume production. We started working together very early, so they have a time-to-market advantage.

KL: Everyone’s waiting for ChipWorks or TechInsights to cut away an end-product device that has FD-SOI. It’s just a matter of time.

Interview (Part 2 of 2): Leti Is A Catalyst For The FD-SOI Ecosystem, CEO Marie Semeria Explains Where They’re Headed

December 17th, 2015

By Adele HARS

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

Leti_MobileCR_JAYET_CEALeti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

CEA002051_JAYET_CEALeti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

Interview: Leti Is The Moving Force Behind FD-SOI. CEO Marie Semeria Explains The Strategy (Part 1 of 2)

December 8th, 2015

By Adele HARS

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?

MarieSemeria_LetiCEO_©PIERREJAYETMarie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.

Minatec_aerial_loresLeti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

~ ~ ~

Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.

RF-SOI Roars Back Into The Headlines

November 27th, 2015

By Adele HARS

Articles about chips built on RF-SOI technology are back in the headlines. What’s driving it? Data – lots of it, and at ever higher speeds, finding its way in and out of your mobile device.

Bear in mind that we’re talking now about RF-SOI, which is not the same thing as RF in FD-SOI. These RF-SOI chips serve front-end module (FEM) functions, and are designed specifically for the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances. They handle the back-and-forth of signals between the transceiver and the antenna. Today it would be practically impossible to find a smartphone that doesn’t have an RF FEM based on RF-SOI wafer technology. And the advent of 4G/LTE/LTE-A (and next, 5G) only serves to drive this market to new heights.

(In a recent ASN post, we explained the differences between RF-SOI and FD-SOI with RF – if you missed it, you can still read it here.)

By way of background, the current RF buzz is aligning with lots of activity on the world standards stage. The ITU (International Telecommunications Union), which sets time lines and processes, has just finished up its Radiocommunication Assembly (RA-15), where it approved the IMT-2020 Resolution, paving the way for 5G mobile systems (press release here). That puts 5G rolling out in 2020. If you’re really going to connect all the things in the big IoT picture, you’re going to need a whole lot more bandwidth.

But in the meantime, driven by video, even the current move from 3G to 4G/LTE-A is massive when it comes to what your mobile device has to handle. FEM designers are working all out to accommodate this, and new generations of SOI substrates are key to making it happen.

Check out this graphic from Cisco’s Global Mobile Data Traffic Forecast Update 2014–2019 White Paper, showing a CAGR of 57% in mobile data through 2019 – so this is in the 4G to LTE-A time frame.

CiscoVNI_white_paper_c11-520862_1Cisco Forecasts 24.3 Exabytes per Month of Mobile Data Traffic by 2019 (Courtesy: Cisco VNI Mobile, 2015)

And the just-released Ericsson Mobility Report (get it here) sees a huge increase in M2M (machine-to-machine – an essential of IoT) and consumer cellular and non-cellular hitting the airwaves in the next five years.

EricssonNov15conndevA connected device is “…a physical object that has an IP stack, enabling two-way communication over a network interface.” (Source: Ericsson Mobility Report, November 2015.)

So, new solutions are needed, and RF-SOI is at the heart of it. Here’s a quick round-up of important pieces you won’t want to miss.

Microwave Journal

MicrowaveJcover_RFSOI_Oct15RF-SOI was the cover story and in the technical features of the October 2015 issue of the prestigious Microwave Journal (click here for that October digital edition).

Just to put it in perspective, getting published in the Microwave Journal is a holy grail for RF engineers. For over 50 years, it’s been the leading RF and microwave technology publication, with all peer-reviewed articles. So for RF-SOI to take center stage there is a blockbuster – it just doesn’t get much better than that. Here are the links:

Semiwiki goes to GF

Industry guru Scotten Jones wrote in semiwiki.com about the key role of RF-SOI in GF’s strategy. This was gleaned from a recent trip to the (ex-IBM) fab in Burlington, VT. His wrap-up, GlobalFoundries Visit – Part 2 – Waking the Sleeping Giant (see it here) provides new insight into just how important RF-SOI is for the company.

The article contains a link to the slide deck of the presentation given to them by the folks at GF. It’s tremendous – if you’re at all interested in RF-SOI, you really should look at it. You can access it directly here.

As recounted in the article, GF’s Burlington fab has shipped more than 18 billion RF-SOI devices since IBM first announced the their RF-SOI process back in 2007. They’ve had more than 1450 tape-outs. The 60,000 wafer/month RF-SOI market is driven by tuner and switch apps. By virtue of putting these apps on SOI rather than using III-V materials, they reduce costs and are able to integrate key logic and control functionality.

(Source: semiwiki.com and GlobalFoundries)

Check out this GF slide showing the massive growth they’re projecting:

GF_RFSOI_SAMapps(Source: semiwiki.com and GlobalFoundries)

And here’s the roadmap that says it all:

GF_RFSOI_roadmap

(Source: semiwiki.com and GlobalFoundries)

Elsewhere in the news, there have also been a number of new RF-SOI-based products announced. We’ll be expanding on those in the ASN Buzz, so stay tuned!

FD-SOI Everywhere: GF & Samsung Videos, Press, Conferences and More – A Quick Roundup

November 23rd, 2015

By Adele HARS

GlobalFoundries video

Info on GlobalFoundries 22nm FD-SOI offering just keeps on coming. Following the ASN roundup of info from the summer and fall (missed it? read it here), they’ve posted yet another excellent FD-SOI video:GF22_FDSOI_BodyBias_video

How to optimize power and performance with 22FDX™ Platform body-biasing – Dr. Jamie Schaeffer gives a quick (under 3 minute) guide to the basics of front and reverse body-biasing, and the GF approach to a dynamic trade-off between power and performance . He explains how forward body bias (FBB) boosts performance at both high and low voltages, and how reverse body bias (RBB) cuts leakage for the lowest standby power. He also touches on FBB techniques for analog/RF designs.

Samsung video

Samsung28FDSOI_runnersThey’re back! Though they’ve been pretty quiet recently, this latest Samsung video on their 28nm FD-SOI foundry offering hits right at the heart of IoT. Entitled The IoT Revolution and Samsung Foundry’s 28nm FD-SOI, the fun two-minute spot features two runners talking shop during a break. She asks: Is there a lot of design ecosystem support for FD-SOI? He answers: Absolutely. And he goes on to talk about the EDA/IP ecosystem they’re building. It ends on this tantalizing note: He: So you’re done? She: Not! Race you to the next station!He: Oh, it’s on!

SemiWiki.com

With reader interest high and higher, FD-SOI continues to get great coverage in SemiWiki.com. Here are some recent good reads:

IP-SoC Rebound in 2015 ! – IP expert Eric Esteve covers FD-SOI highlights from the upcoming IP-SOC 2015 conference in Grenoble, France (2-3 December 2015), including these presentations (full program here):

  • FDSOI is taking on speed as platform and a European focus project by Gerd Teepe, GlobalFoundries
  • FDSOI IP Shop: The key enabler of success by Patrick Blouet, Collaborative program manager, STMicroelectronics
  • Strategies for SoC / IP Design for Emerging Applications: An Indian perspective by Samir Patel, Sankalp Semiconductor
  • Assessing and managing the IP Sourcing Risk by Philippe Quinio, STMicroelectronics
  • Power Planning and Timing Signoff Solutions by SOI guru and ARM Fellow Jean-Luc Pelloie
  • FD-SOI a New Era for Power Efficiency: Why and How? By Olivier Thomas, Silicon Impulse, CEA – LETI (btw, if you missed his excellent ASN piece explaining Leti’s Silicon Impulse program, you can still read it here)

28nm FD-SOI: A Unique Sweet Spot Poised to Grow – Pawan Fangaria explains why “…today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on.”

Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node – Tom Simon was at ARM Techcon, where he attended a talk sponsored by Cadence on the topic of using GlobalFoundries 22nm FD-SOI process to implement a quad core ARM Cortex-A17. He shares a number of the key slides in this informative blog.

SemiEngineering

SemiEngineering Editor-in-Chief Ed Sperling continues his great line-up of incisive interviews. In Increasing Challenges At Advanced Nodes, he gets some spot-on FD-SOI quotes from GlobalFoundries CTO Gary Patton, including:

  • “It’s great that you get finFET performance at 28nm cost. But what’s really interesting for me is that you get software control. You can turn chips, blocks and circuits on and off. It’s a whole new degree of freedom for the designer.”
  • “ I believe 22nm FD-SOI fits the sweet spot.”
  • “We wouldn’t do 14nm FD-SOI. We would want a bigger jump than that. It would something closer to 10nm.[…] …it would be planar. If you go to finFET, you would lose the back body biasing. That’s a key attribute.”

RF-SOI vs FD-SOI with RF – What’s the Difference?

October 28th, 2015

By Adele HARS

Is RF-SOI the same thing as RF on FD-SOI? No, it’s not. However, the runaway success of RF-SOI and the growing list of recent announcements related to FD-SOI with integrated RF has lead to some confusion in the press and social media. The two are different technologies, addressing different markets, and built on two very different types of SOI wafers. The use of one technology or the other depends on the requirements of the targeted RF application.

For the non-technical reader, here is a bit of basic background. At the most simplistic level – RF: radio frequency – is part of the analog family, and as such is all about waves. And when you talk about waves, you talk about losses over distance (attenuation), speed, wavelength and frequency – which is why the RF design has a rep of being something of a black art. The distance to cover, the power envelope and the amount of data to carry over that distance (and of course, the cost) determine the chip solutions. An important part of the RF chip solution is the choice of the wafer substrate itself.

So here’s a quick primer to help sort out what’s what. Please bear in mind, though, that this is a fast-evolving world, so what you’re about to read is not a definitive and forever what’s what – but more of a general (and simplified) “this is how it is currently shaking out”.

RF-SOI – Talk to the Tower

When it comes to using your mobile device for data transmission over a 2G, 3G, 4G/LTE/LTE-A (and next, 5G) network, you still need dedicated RF front-end modules (FEMs). FEMs handle the back-and-forth of signals between the transceiver and the antenna. They contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. Traditionally, they were built on gallium arsenide substrates. But more and more, the multiple chips in FEM chipsets are being reduced to single SOCs built on a special class of high-resistivity SOI wafers. This is the realm of RF-SOI. The wafers for RF-SOI are designed specifically to handle the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances.

eSI_SoitecUCLwaferSoitec premiered a radically new and immensely successful generation of RF-SOI substrates in 2013: the enhanced Signal Integrity™(eSI) family, which introduced the concept of the “trap-rich” layer developed at UCL. (Image courtesy of Soitec)

The latest standards (LTE-A and 5G) raise the stakes ever higher, requiring mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

For RF designers, that means choosing substrates that favor low RF loss and high RF linearity. A couple of years ago, SOI leader Soitec, in partnership with UCL, brought breakthrough RF-SOI wafer technology to the market (read about that here). Now, a few generations later, Soitec estimates that one billion RF devices are produced each quarter using their advanced and enhanced Signal Integrity™(eSI)wafers for RF. In fact it would be nigh near impossible to find a smartphone that doesn’t have an RF FEM based on  RF-SOI wafer technology.

Here at ASN, we’ve covered many of the leaders in RF-SOI FEMs over the last few years. Click on any of these names to get an idea of what they’re doing: IBM (now part of GlobalFoundries), PeregrineSkyWorksTowerJazzSTQorvoSony, QualcommGraceToshiba and MagnaChip. To learn more about the latest developments in wafer technology for RF-SOI, click here. With demand soaring, Soitec’s most advanced RF-SOI wafers are now also being produced by Simgui in China – read about that here.

In fact, the cover story and technical features of the October 2015 issue of the prestigious Microwave Journal is dedicated to RF-SOI – click here to read it.

So in terms of terminology, that’s “RF-SOI”. Now let’s look at how RF on FD-SOI is different.

RF in FD-SOI – for digital integration

When we talk about RF in FD-SOI, we’re typically talking about some RF functionality being integrated into SOCs that are essentially digital processors. True, you can integrate RF functionality into an SOC built on planar bulk (it’s generally agreed to be a nightmare in bulk FinFETs, though). But you can integrate RF into your digital SOC much more easily, efficiently and with less power if you do it in FD-SOI.

RF/analog has a (well-deserved) rep of being the most challenging part of chip design. Analog/RF devices are super sensitive to voltage variations. The digital parts of a chip, which have strong, sudden signal switching, can raise havoc with nearby analog/RF blocks. This means that the analog/RF designers have to care acutely about gain, matching, variability, noise, power dissipation, and resistance. They use all kinds of specialized techniques: FD-SOI makes their job a lot easier (good explanation in slide 8 here). What’s more, FD-SOI’s analog performance far exceeds bulk.

What sort of chips are we talking about? For now, we’re talking about processors for mobile devices, for IoT, for automotive, for consumer electronics. When we say “RF in an FD-SOI SOC”, we’re currently talking about chips that are connecting over a relatively short distance to a nearby box or device (<100m for local WiFi, or a few meters for Bluetooth or Zigbee, for example).

ST’s new set-top-box processors on 28nm FD-SOI (read about them here) are a great example. They are the first on the market integrating 4×4 802.11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This means the set-top boxes can reliably serve lots of HD video via WiFi to multiple users throughout the house (hopefully ending the cry: “Who’s hogging all the Wifi?!?”). ST credits their 28nm FD-SOI silicon technology with providing that highly-efficient RF, state-of-the-art WiFi performance and robustness required for reliable video delivery inside the home.

For RF on FD-SOI – as in other FD-SOI apps – designers use SOI wafers with ultra-thin silicon, ultra-thin insulating BOX and phenomenal top silicon thickness uniformity. These wafers are not the special high-resistivity wafers used in RF-SOI. Rather, they are the latest generations of the same (amazing!) FD-SOI wafers that Soitec introduced in 2010. (For an excellent, in-depth interview with the Soitec FD-SOI wafer guru on the supply chain and the most recent developments, click here.)

TopSiLoss_FDSOIThe top silicon uniformity of Soitec’s “FD-2D” wafers for FD-SOI is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. The BOX thickness is 10nm to 25nm, depending on the customer’s approach.

This is the type of wafers that GloFo, ST, Samsung, Freescale, Sony, several other companies in Japan and many more around the world are using when they say they’re doing RF on FD-SOI. Bear in mind that this level of SOC integration is fairly new (Samsung and TSMC just announced RF integration into SOCs for the first time in 2014 on 28bulk). But using FD-SOI technology and the corresponding ultra-thin SOI wafer substrates makes life much easier for the RF folks on the design teams, gets far better performance and far lower power at a much more attractive cost.

Further ahead, FD-SOI is also a candidate for transceivers and baseband/modem SOCs, which require high-performance digital and analog/RF integration. But even with transceivers on FD-SOI, you’ll still need the FEM on RF-SOI to handle the interface.

So, that’s the current difference between RF-SOI and RF on FD-SOI.

Hope that helps to clear things up?

Advanced Substrates for 3D and Other New Markets Drive New Fab Inspection Equipment: Interview with Altatech GM

October 6th, 2015

By Adele HARS

New approaches in chipmaking and fast-evolving specialty markets are driving the need for new equipment on the fab floor. 3D chips (be they stacked or bonded), MEMS, lighting, power – they’re all leveraging wafer substrates in new ways. Altatech, the equipment division of SOI-wafer leader Soitec, has just announced new inspection equipment for foundry and IDM customers fabbing 3D and other chips. ASN talks to Jean-Luc Delcarri, Altatech general manager, about the company and its recent announcements.

Advanced Substrate News (ASN): Can you tell us briefly about the company and the markets it serves?

mgmt_jldelcarriJean-Luc Delcarri, Altatech general manager

Jean-Luc Delcarri (JLD): Altatech makes specialty equipment for the fab floor. We have two main areas of deep expertise: one is in defect inspection, and the other is in CVD* technologies for semiconductor, LEDs, MEMS and photovoltaic devices. I founded the company in 2004, and then in 2012 we became a subsidiary of SOI wafer leader, Soitec.

ASN: At Semicon Europa 2015, you announced “…a new, high-speed inspection system for ultra-thin, transparent and bonded substrates inspection for 3D applications in power, MEMS and mobile technologies.” What’s driving that market?

JLP: Yes, at Semicon we announced the Eclipse TS, which is a unique, high-reliability and easy-to-implement inspection system solution that’s now ready for mass production.

You’ve got the need for these advanced substrates that’s being driven by really rapidly growing markets in automotive, industrial power and mobile electronics. We’ve been working quietly on this tool for years, and now the Eclipse TS has been qualified for volume manufacturing at a leading-edge semiconductor manufacturer, so we’re really excited about it.

AltatechEclipseTSInspectionSystem2015Altatech’s Eclipse TS, a high-speed inspection system for ultra-thin substrates in 3D applications.

ASN: What makes the Eclipse TS different from other inspection sytems?

JLP: When you’re looking for defects on these advanced wafer solutions, you have to do much more than scan the top: you need to inspect the front side, the back side and the edge of very thin wafers – and you have to do it without touching them. Our ability to do all this makes us totally unique on the market: we have built this tool on a strong IP portfolio.

So with the Eclipse TS, you have a high-speed inspection system that can measure very thin and stacked wafers down to 50 microns, as well as Taiko rings, stacked substrates and silicon-on-glass wafers. Plus we can do the front-side, back-side and edge inspection in one pass with no back-side contact.

In today’s 3D technologies, substrates undergo grinding, stacking and gluing, so you can end up with wafers with a very high bow, or  wafers with a warp of up to 6 mm. We can handle those wafers. In fact, the Eclipse system can monitor these sorts of processes. The inspection occurs without any contact on the active surface, and at a throughout of more than 90 wafers per hour for 300-mm substrates.

We’re of course compliant with the latest automation standards, so the system can be fully integrated into the line, and provide comprehensive reporting for defects classification and yield maps.

Our full Altatech Eclipse series covers advanced metrology and holistic inspection systems. That means we can detect, count and bin defects during the wafer manufacturing process as well as do continuous outgoing wafer-quality inspection. So the quality of both the wafer-surface and edge is ensured. We also have proprietary Eclipse sub-modules that detect specific sorts of particles and defects of interest for both patterned or unpatterned wafers.

All that puts Altatech in a leading position in what is a very large market opportunity.

AltatechAltaCVD3DMemoryCell2015Altatech’s AltaCVD 3D Memory Cell deposits the ultra-thin semiconductor films used in high-density, low-power memory chips 10 times faster than conventional ALD systems.

ASN: You also make CVD – deposition – equipment. Can you tell us a little about that, and what’s driving those markets?

JLP: Sure. Last year we introduced the AltaCVD 3D Memory Cell™, which is the newest member of our AltaCVD product line. This is used for depositing ultra-thin semiconductor films when you’re manufacturing the high-density, low-power memory chips used throughout mobile electronics. Our new system does atomic-layer deposition 10 times faster than conventional ALD** systems, which is of course huge when you’re manufacturing advanced memories where you need to run in very high-volume production with extreme cost efficiency.

In the new 3D device architectures for mobile apps, our customers are looking to really increase memory capacity and boost performance. And to do this, they need very advanced material deposition to create atomic-layer films with high uniformity – you really are at the atomic level of control here. The AltaCVD 3D Memory Cell deposits layers of chalcogenide*** materials by using a combination of precursors, which is very leading edge.

So with our tool you can use conventional gaseous or solid precursors, but we also have a patented pulsed technology, which means you can also use advanced CVD precursors that are available only in liquid form. This is remarkable versatility: it allows us to achieve exceptional step coverage over features with very high aspect ratios – that’s a key performance requirement when you’re talking about vertical integration high-density memory circuits.

You can also use it for advanced pre-treatment of semiconductor surfaces (which improves circuit functionality), as well as post-treatment of surfaces (which enhances electrical performance).

Because it’s used in everything from research to high-volume manufacturing, it can process 200-mm or 300-mm substrates, and uses a single-wafer, multi-chamber architecture. One of our key customers demonstrated it last year. We’re now selling production units, and we’re pleased to say it’s been very successful.

ASN: Do you have other products in the pipeline?

JLP: Next up we have a new solution for high aspect ratio 3D copper deposition. The system, which is called RUBY, can deposit a barrier layer of titanium nitride or tantalum nitride with almost 100% step coverage on an aspect ratio higher than 10:1. This is followed by deposition of a copper seed layer with similar performance. Combined with a proprietary copper cleaning process, it will be able to meet the growing challenge of copper metallization in MEMS and semiconductor 3D integration. We’ll release it as soon as we’ve completed our product milestones for reliability and performance.

ASN: Where do you see the highest-growth areas?

JLP: We’ve developed the right technology for the right time in a number of key markets, so we’re really well-positioned to answer the needs of a number of high-growth markets. The move to 450mm wafers is something we’re ready for, which will probably happen first in advanced memories. But in the meantime we also see significant activity in MEMS, RF, high power and LEDs. We’re winning customers in China who are looking to be leaders in these markets. All in all, much of the future of the phone in your pocket depends on what we can help our customers do in high-volume and cost-effectively on the fab floor – so it’s a very exciting time to be in this business.

~ ~ ~

*CVD=chemical vapor deposition

**ALD=atomic layer deposition

*** chalcogenides include sulphides, selenides, and tellurides

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