- Horacio Mendez: To answer the question directly: This is absolutely NOT a SOITEC and ST only effort. • At the Fully...
- litho guy: I couldn’t rely on EUV for beyond 14-15 nm anyway since the resist can’t resolve that....
- Chris EDA: The casual and imprecise language in this article may make for a fun read, but it doesn’t inspire me...
- Adele Hars: ST says there’s no particular impact to design flow/EDA, beyond extraction deck and SPICE models,...
- SoC Guy: Is this a SOITEC and ST effort only, is the rest of the support infrastructure involved. (IBM, foudry, EDA...
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Industry Research
Qualcomm, Micron, GlobalFoundries Gain in IC Rankings
Qualcomm, Micron and GlobalFoundries gained ground in the top 20 rankings in terms of sales in the first quarter of 2012, according to IC Insights. GlobalFoundries replaced Elpida in the top 20 rankings. The foundry vendor also jumped ahead of United Microelectronics Corp. (UMC).
Forecasters Boost Capital Spending Outlook
The IC business climate continues to improve in 2012, prompting various firms to raise their respective capital spending forecasts. Total semiconductor capital spending is now projected to hit $56.5 billion in 2012, nearly flat from the previous year and almost $6 billion higher than the January outlook, according to a new forecast from VLSI Research Inc.
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White Papers
Improving the Quality of PVD Cu Seed Layer
Authors from Novellus Systems and The University of Illinois describe how the quality of PVD deposited barrier/seed interface in copper interconnect metallization was significantly improved by enhancing Cu nucleation on the Ta surface.
Considerations for Porting a Bulk CMOS Design to FD-SOI
Technologists describe a straight port of an existing bulk CMOS design to
FD-SOI at the same node, obtaining the value of fully depleted SOI for a
modest redesign effort.
RF Substrate Technologies for Mobile Communications
Two Soitec Group managers — Eric Desbonnets and Stéphane Laurent — describe how SOI wafers support RF technology development.
Metric Pitch BGA And Micro BGA Routing Solutions
Via fanout and trace routing solutions for metric pitch ball grid array packages.
Design Impacts of Fully Depleted SOI
Xavier Cauchy, digital applications manager at Soitec, describes the design implications of fully depleted SOI technology at the 22/20 nm node.
Frequently Asked Questions About FD-SOI
Xavier Cauchy of Soitec and François Andrieu at LETI raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading.
Manufacturing Closure with Calibre InRoute and Olympus-SoC
This Mentor Graphics paper describes the physical signoff challenges seen in advanced node designs.