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Latch-Up Detection: How to Find an Invisible Fault

Way back when, in the olden days (which, in the semiconductor industry, usually means last week), designers used visual inspections and manual calculations to check their layouts.

How Critical Area Analysis Optimizes Memory Redundancy Design

As any design engineer knows, the farther downstream a design goes, the less likely a manufacturing problem can be corrected without a costly and time-consuming redesign.

Context-Aware Latch-up Checking

Latch-up in CMOS circuits is a long-studied and troubling phenomenon that often leads to chip failure through the inadvertent creation of parasitic PNP and NPN junctions being driven (turned on/forward-biased).

Established Technology Nodes: The Most Popular Kid at the Dance

I remember back in the day at high school dances, always wanting to dance with the most popular girl in school. I never could, because there were a constant stream of others queued up to dance with her. If you are trying to build an integrated circuit (IC) today, and trying to get fab capacity at 28nm and above, you are faced with the very same situation.

Leveraging Reliability-Focused Foundry Rule Decks

Not that long ago, all designers had for integrated circuit (IC) reliability verification was a plethora of home-brewed scripts and utilities they combined with traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) tools.

Reliability Scoring for the Automotive Market

The annual growth for car sales is typically in the single digits, but the electronic content inside those cars is rapidly expanding as we enter the age of the digital car.

Interconnect Robustness Depends on Scaling for Reliability Analysis

The safety net of design margins that were once available to designers has disappeared. Whether you’re implementing a new design start at your “next” node or an established node, the desire for greater functionality has eroded what margins used to exist.

Collaborative SoC Verification

With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation is now a team sport.

System-Level MEMS Design: An Evolutionary Path to Standardization

Successful design of highly-integrated IoT systems requires simulating MEMS components together with the peripheral circuitry.

Five Steps to Double Patterning Debug Success

Has debugging double patterning (DP) errors got you pulling your hair out, or wishing you had pursued that career in real estate, like your mom suggested? Now you can unlock the secrets of DP debugging in five easy steps! Once you learn these steps, you’ll be the envy of your team, as you deliver clean DP designs on schedule, and still have time to eat lunch each day!

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