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Faster Signoff and Lower Risk with Chip Polishing

By Bill Graupp, Mentor, a Siemens Business

Designing integrated circuits (ICs) today is a complex and high-risk endeavor; design teams are large and often scattered around the world, tool flows are complex, and time-to-market pressures omnipresent. It’s no surprise that product releases are often delayed because design teams can’t get to signoff on schedule. Schedules certainly account for the time required for full verification, as well as design optimizations like DFM fill and via enhancements, but all the delays along the way accumulate. Engineers are then pressured to compensate for those delays to stay on schedule. Typically, the final days of signoff are the worst—the deadline is looming, and each iteration between finding and fixing layout issues increases the risk of being late.

Engineers are all about increasing efficiency and reducing risk. When considering how to get to signoff faster, there are many ways to do that. You could hire more designers, but that makes coordination harder. You could increase design margins, but that reduces your product’s value. You can make sure to plan plenty of time for final verification and signoff, yet delays earlier in the flow can still impinge on that allotted block of time.

The counterintuitive solution? Add another step to the process flow—more verification performed at many levels throughout the design flow to catch and fix problems earlier. The phenomenon of putting in more thought and effort to get “less” isn’t unique to IC design. Mark Twain captured the idea when he said, “I didn’t have time to write a short letter, so I wrote a long one instead.”

IC designers already do this to find design rule checking (DRC) violations, starting in early implementation, but how about the non-DRC layout issues, like nano-jogs, space ends, mushrooms, dog bone ends, and offset vias? None of these items is necessarily a design rule error, but all of them are likely to affect manufacturability and lower yield. Fixing these issues is referred to as chip polishing, and is one of the keys to improving a product’s manufacturability. Figure 1 illustrates some typical chip polishing activities.


Figure 1. Automated chip polishing modifies the layout to improve robustness of the design and yield. Modifications are inserted back into the design database.

There are software tools that automate these chip polishing tasks and can be easy to adopt and customize into any flow to reduce the risks associated with reaching signoff. A key to usability of chip polishing software is the ability for engineers to combine a focused set of commands into macros that can be peppered throughout a customized flow for engineering change order (ECO) filling, passive device insertion, custom fill to increase densities, jog removal, via enhancements, and programmable edge modification (PEM) commands to eliminate fragmented edges. If, for example, your power structures or capacitor placement rules cause system-level final verification issues, a solution can be implemented quickly and systemically across all blocks and top cells.

Categorizing issues by groups, based on the methodology needed to fix the issue, improves the efficiency of design closure. Correction of some issues requires the insertion of passive devices, while others require polygon shifts and edge movements. Some require the insertion of additional shapes for manufacturability. Each of these categories can best be handled by a custom electronic design automation (EDA) process designed to resolve that category of issue. When one process is used for each category, then all the processes can be combined into one final sign-off flow that can be customized for each design methodology, using a common programming language and database.

Many of the failures of today’s post-route sign-off flows can be solved by creating the conditions for an effective and timely solution to late-stage DRC errors and enabling engineers to insert and modify any shapes needed to achieve the final signoff. A well-designed automated sign-off flow can improve your product’s manufacturability, allow you to get to market faster, and enable you to create market differentiation.

For example, many issues that require or benefit from chip polishing arise from hierarchy conflicts, such as two lines from two cells being connected at the parent cell without the knowledge of the entire line shape or width. Other typical problematic layout features include:

  • Space Ends – Metal lines formed into a “J” due to the router passing a short adjacent track line and coming back to the far end. The connection bottom of a “J” can pinch if the loopback is too narrow.
  • T-Line Ends – Metal lines with a narrow cross “T” at the end can cause necking.
  • Mushrooms – A long metal line connected to the center of a short metal adjacent track line typically causes necking of the connection metal.
  • Nano-jogs – When two metals of slightly different widths are connected end to end, it creates breaks in long edges that cause unnecessary runtime in verification and mask generation.
  • Offset Vias – Manually-placed vias at an adjacent metal overlap that are not centered in the overlapping region create potential via coverage issues that can cause higher electrical resistance.

Chip polishing software can execute programmable edge modification (PEM) commands to correct for these issues, including polygon shifting, polygon sizing, edge-based polygon creation, feature-based edge identification (jogs, space ends, etc.), and polygon growth with spacing considerations.

By reducing the number of edges in the design through chip polishing, many chip release tasks can be improved or eliminated. It’s only logical that mask generation can optimize long edges more quickly when they do not contain jogs or notches, so it’s no surprise that final verification runtimes for large blocks and chip layout can be reduced by eliminating any edges broken into fragments due to accidental jogging. Mask generation is also faster with optimized line ends, because there are fewer edges that will require optical proximity correction (OPC). By having a faster mask flow with fewer issues to manage, the manufacturing process can be optimized for the consistency of the manufacturing models used to control the process. A more robust design will also create a more reliable product, as well as reduce yield variability over the life cycle of the product.

Getting to signoff faster, with less risk, while generating a layout that is highly manufacturable can be accomplished with automation tools with the types of analysis and fixing capabilities described here. PEM commands can improve a layout by automatically analyzing a design, then smartly removing or altering the offending edges. A well-designed automated PEM flow can improve your product’s manufacturability, allow you to get to market faster, and enable you to create market differentiation.


Graupp_Bill_2015_2x2 Bill Graupp is a DFM Application Technologist for Calibre in the Design to Silicon division of Mentor, a Siemens Business. He is responsible for product marketing and customer support for the DFM product line, focused on layout enhancement and fill. Bill received his BSEE from Drexel University, and an MBA from Portland State University. After hours, he currently serves as the mayor of Aurora, Oregon, and as a director on his local school board.

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