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Archive for December, 2015

Electromigration and IC Reliability Risk

Thursday, December 10th, 2015

By Dina Medhat, Mentor Graphics

Electromigration (EM) is the transport of material caused by the gradual movement of the ions in a conductor, due to the momentum transfer between conducting electrons and diffusing metal atoms (Figure 1). The EM effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated circuits (ICs) decreases, the practical significance of the EM effect increases, decreasing the reliability of those ICs.

Figure 1: EM is caused by the momentum transfer from electrons moving in a wire. (source: Wikipedia)

EM can cause the eventual loss of connections, or failure of an entire circuit. Since reliability is critically important for applications such as space travel, military systems, anti-lock braking systems, and medical equipment and implanted devices, and is a significant consumer demand in personal systems such as home computers, entertainment systems, mobile phones, and the like, the reliability of ICs is a major focus of research efforts in the semiconductor industry.

Reliability risk goes beyond that of physical device reliability (a challenge unto itself), extending to interconnects and their susceptibility to EM effects. Failure analysis techniques can identify failure types, locations, and conditions, based on empirical data, and use that data to re­fine IC design rules.

Let’s look at one approach using the Calibre® PERC™ reliability solution. The Calibre PERC tool can perform topology identification for pins/nets of interest, run parasitic extraction and static simulation, compare the results against EM constraints, then present violations for debugging using the Calibre RVE™ results viewing environment (Figure 2).

Figure 2: Automated EM analysis flow.

With basic EM analysis explained, let’s discuss in greater detail some selected EM analysis techniques, such as current density analysis, Blech Effect analysis, and hydrostatic stress analysis. Current density analysis seeks to identify the maximum current any piece of metallization can sustain before failing. Current densities below this threshold can be used to predict EM effects over time. Blech Length is a process- and layer-defi­ned wire length at which EM effects are unlikely to occur. By fi­nding these short wires, designers can quickly eliminate error results representing false violations. Hydrostatic stress analysis derives the degradation of the electrical resistance of interconnect segments from the solution of a kinetics equation describing the time evolution of stress in the interconnect segment.

A toolset that can combine geometrical and electrical data, like the Calibre PERC™ logic-driven-layout framework, can dynamically and programmatically target reliability checks to specifi­c design features and elements. This flexibility allows designers to selectively target and dynamically con­figure EM analysis to those specifi­c interconnect wires that are most critical, or most susceptible to EM failure. This design-context-aware interconnect reliability technology provides a scalable, full-chip EM analysis and veri­fication solution that considers interconnect resistance, the Blech Effect, and nodal hydrostatic stress analysis for failure prediction. It also allows designers to apply EM analysis techniques to a broad range of designs and process technologies, with only minor adjustments to the setup and con­figuration.

Although fi­xed constraints work well in most IC verification cases, EM analysis and verifi­cation requires a much more flexible constraint mechanism. In current density analysis, allowing current density constraints to be a function of properties of the parasitic resistor (such as the length and width of the resistor) enables layouts to contain resistors with a smaller length and width and a higher current density. The dynamic constraint infrastructure allows adjustments to the current density constraint based on the parasitic resistor properties.

In Blech Effect analysis, the Calibre PERC solution provides access to the measured EM length for any interconnect tree. If the longest path of the interconnect tree is less than the Blech Length, the tool returns a current density constraint of some very large value, which acts as a constraint waiver for this resistor with a segment on an immortal interconnect tree.

Hydrostatic stress analysis must be performed on each interconnect tree. For each node, the Calibre PERC tool compares σi to σcrit. For any interconnect tree where σi ≥ σcrit , the interconnect tree and its individual nodes can then be highlighted in a layout viewer, as well as possible EM failure locations. The determination of σcrit is a function of process technology and segment geometry, and ideally should be provided by the foundry.

Once the EM analysis is complete, an importantaspect of ensuring reliability is debugging any errors or issues. Figure 3 demonstrates the debugging of EM violations by grouping and sorting them, then using colormaps to see current density violations/severity on the layout.

Figure 3: Debugging EM violations

Combining hydrostatic stress analysis with Blech Effect and current density analysis provides a well-rounded platform for the prediction of EM failure, allowing designers to filter out trees that are considered immortal. With the knowledge gained from such analyses, design rules can be modified to eliminate or minimize EM conditions in future designs. Using a reliability analysis tool like the Calibre PERC solution, designers can be more confident that their layouts are resistant to the long-term effects of EM, and will perform as designed for the intended lifetime of the product.

Dina Medhat is a technical lead for Calibre Design Solutions at Mentor Graphics. She has been with Mentor Graphics for ten years in various product and technical marketing roles. She holds a BS and an MS from Ain Shames University in Cairo, Egypt. She can be reached at dina_medhat@mentor.com.

Technical Workshops – Providing Access to the Industry’s Best

Tuesday, December 1st, 2015

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions

It may not seem like such a revelation, but many of the opinions and traits we carry around with us are often attributable to our peer group. From a professional perspective, this could include colleagues, advisors, managers, and a host of other influencers that have crossed your path along the way. Good, bad, or indifferent, these experiences influence how you work and what you consider “normal.” In some of the focused and specialized fields of IC design and verification, like electrostatic discharge (ESD) and reliability, it is often a challenge to find and connect with suitably well-informed individuals that you can bounce ideas off, learn from, and grow with.

There are a number of pockets of excellence within the industry, but if you are not fortunate enough to have been introduced to the right post-graduate program or advisor, or to work in a company that supports a thriving eco-system of like-minded individuals, you’re pretty much left to your own devices in a vacuum. So, if you are working on an island, how do you build bridges to other experts in your field, outside your organization? One way to gain exposure to new ideas, techniques and best practices is to attend industry conferences. Another is to forgo the large-scale format that conferences provide, and look at what workshops have to offer.

Not familiar with the workshop format? Generally speaking, workshops provide 3-4 long days with the same folks, in an environment probably a lot like those summer camps you attended as a kid. You all eat together, attend the keynote, invited talks, and paper/poster presentations together, and participate in one or more discussion groups occupying the evenings. The focus of a workshop is, by design, much narrower than a large industry conference, so everyone attending has the same range of interests and issues. Overall, with the smaller groups of the workshop format, there is a lot of time for discussion and interactions with others. Want to know something? Ask! In my experience, the pedigree of attendees is often outstanding, with a welcoming and inclusive disposition to newcomers looking to learn more about the field. None of us are experts in every field, and being able to learn firsthand from insightful and interactive discussions only bolsters the learning experience. Another advantage extends past the workshop itself—the forging of professional relationships that can provide valuable advice, consultation, and collaboration long after the event is finished.

Over the last five years, I’ve seen a plethora of emails turn up at my inbox, proclaiming the 2nd or 3rd annual workshop on such and such a topic. These organizations are getting the ball rolling. I’ve even seen a number of 1st annual invitations. While I haven’t kept track of how many of these newer workshops survive to maturity, two established events that I’m particularly fond of are the International ESD Workshop, who are starting to ramp up for their 2016 event (which will be their tenth year), and the International Integrated Reliability Workshop, who can trace their origins as far back as 1982. For me, these legacies have demonstrated that smaller, focused groups having a high degree of interaction and discussions bring participants together, not only to focus on the program material, but also to bring a sense of community to a tight-knit and focused group.

I’d be interested to hear about your experiences of attending both conferences and workshops. For me, each has its place, but the workshop format provides a significantly more robust and in-depth framework to share a lot of ideas in a short, concentrated period of time, while really getting to know colleagues in your field.

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at matthew_hogan@mentor.com.