Part of the  

Solid State Technology

  Network

About  |  Contact

Archive for May, 2015

Custom Layout Designers Need New Tools for New and Expanding Markets

Wednesday, May 27th, 2015

By Srinivas Velivala, Mentor Graphics

For a long time, digital was the darling of the semiconductor industry. But then a funny thing happened—the advent of cell phones and GPS and tablets and a zillion other new products made things like power consumption and battery life important market factors. But this new emphasis on analog and mixed-signal designs also brought new market pressure to custom designers. Now more than ever, time to market could mean the difference between so-so results and profitability. With that came the need to reduce design and verification timelines while still ensuring high-quality products.

In response to that demand, we introduced Calibre® RealTime, which provides interactive DRC feedback in a custom layout environment using the same sign-off Calibre design rule checking (DRC) deck that is used for batch Calibre DRC jobs. By enabling signoff DRC during the design process, Calibre RealTime helped designers reduce the time to tapeout. Initially, the use model was intended for debugging DRC results in standard cells and block designs. As such, we included an integrated toolbar, so layout designers could highlight and step through DRC results as per the order of the results generated, or select a specific DRC check and step through the DRC results belonging to that check.

However, layout designers continued to expand the application of Calibre RealTime to larger designs, such as partial layout of a macro, or even full-chip designs, invoking it during final DRC review before tapeout (using a combination of batch Calibre and Calibre RealTime). With this use came a desire to see a complete picture of the DRC results: how many DRC checks are violated, how many DRC results are present in each check, how many DRC results can be disregarded at this design stage, and so on. Providing this type of analysis required an expanded interface GUI to allow layout designers to debug their DRC results efficiently.

The Calibre RealTime-RVE interface has the same look and feel as the Calibre RVE™ tool, to provide custom layout designers the flexibility to analyze DRC results generated from a Calibre RealTime job and formulate an efficient strategy to debug and fix the DRC errors. The interface opens up automatically after a Calibre RealTime DRC job run (Figure 1). Designers can select a specific DRC check and highlight the specific result/s belonging to that check. Designers also get a clear description of the DRC check that has been violated. In this example, the description of the check indicates that this is a double patterning (DP) error.

Figure 1. DRC error results in the Calibre RealTime-RVE interface.

The Calibre RealTime toolbar and Calibre RealTime-RVE interface are always synchronized (Figure 2), allowing designers to highlight DRC results from either the toolbar or the interface.

Figure 2. The Calibre RealTime toolbar and Calibre RealTime-RVE interface are always in sync.

In addition, designers can display and sort DRC results by associated characteristics, reducing visual “clutter” and allowing them to focus more efficiently on their debugging tasks (Figure 3).

Figure 3. Custom designers can display and sort by error characteristics.

To maximize efficiency, designers can run Calibre RealTime DRC jobs on multiple designs in the layout environment, and browse all the results using the Calibre RealTime-RVE interface. The interface opens separate tabs to display the results generated from each design, preventing any mix-up or confusion, and ensuring that there is no additional delay. Designers can select any particular results tab and highlight the results from that tab. The Calibre RealTime-RVE interface automatically ensures that the DRC results are highlighted in the design window corresponding to the DRC results tab from which the highlight commands are issued.

Figure 4. DRC results for multiple designs are displayed separately.

As custom layout designers use Calibre RealTime in an ever-expanding set of use models, they can be confident they will be able to easily comprehend, analyze and debug the DRC results using the Calibre-RealTime-RVE debug interface. Tools like this are essential to supporting the increasing market for custom designs while ensuring companies can produce reliable products in a timely, profitable manner.

Author

Srinivas Velivala is a Product Manager with the Design to Silicon Division of Mentor Graphics, focusing on developing Calibre integration and interface technologies. Before joining Mentor, he designed high-density SRAM compilers, and has more than seven years of design, field, and marketing experience. Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering. In his spare time, he likes to travel and play cricket. He can be reached at srinivas_velivala@mentor.com.

OPC solutions for 10nm nodes and beyond

Friday, May 15th, 2015

By Vlad Liubich, OPC Product Manager for Design to Silicon, Mentor Graphics

“The report of my death was an exaggeration”1. Nothing describes better the current situation of modern ArF immersion (193i) lithography. With continuous shrinking of the IC devices and inability of EUV lithography to reach high volume manufacturing demands, future of the 14nm node was heavily dependent on the availability of the double patterning technology, which at that time was considered as a bridge technology between 193i and EUV2.

Significant efforts to enable double patterning technology were made on the design and computational lithography side of the business. With EUV lithography still delayed, 10nm and 7nm technology nodes are heavily dependent on availability of triple patterning and quadruple patterning decomposition and OPC as well as other supporting technologies.

The traditional OPC approach of correcting one pattern at a time does not take into account situations where inter-pattern interactions start playing a vital role. The main goal of OPC is to make sure the polygon on the mask will produce high-quality images in the photoresist layer. The OPC software compares the simulated resist image to the intended target image, referred to as OPC target convergence. Comparing the difference of the error on a wafer to the mask gives a mask error enhancement factor (MEEF). For example, if a change of 1nm on the mask (1x) produces a change of 4nm on the water, then MEEF is 4nm/1nm, or 4. The higher the MEEF, the harder it is to control the lithographic process because small variations on the mask cause large errors on the wafer.

Target convergence in high-MEEF environment has always been a challenge, but with increased pattern fidelity requirements, edge placement error margins are getting tighter and tighter. Aggressive insertion of sub-resolution assist features (SRAFs), either model- or rule-based, for the critical layers of advanced nodes insertion is a norm, but it often leads to residual SRAF printing. Printing SRAFs causes divots in the resist layer that are transferred by the etching process into dielectric.

Another new challenge is that smaller critical dimensions require thinner films, which makes the final height of the developed photoresist a concern because it leads to less tolerance of resist loss. Usually undetected during a routine top-down measurements, the resist top loss might cause wafer-level post-etch defects that reduce the integrated process window of the patterning step.

With tighter process control requirements of advanced nodes, it becomes more important to eliminate the systematic process variation, and OPC tools must be able to address the effects of variation. At 10nm and below, even layers that were not previously considered to be “lithographically critical” are becoming such.

Whether 193i lithography can provide a viable cost-effective solution for the advanced technology nodes depends in significant degree on the ability of OPC software to provide a platform to compensate for or eliminate the concerns outlined in this introduction.

Tools to enable 10nm lithography

Because multi-patterning (MP) is required at 10nm, an OPC solution must be able to correct three or more patterns simultaneously. Figure 1 shows an example of OPC results for a triple-patterned layout.

Figure 1. Triple patterning OPC results for 10nm interconnect layer.

The experience gained during 22nm and 14nm technology development showed that standard OPC methods with sequential pattern processing are not adequate in the presence of inter-pattern constraints such as inter-pattern spacing and stitching. The loss of a couple of nanometers might seem insignificant at the first glance, but with the diminishing overlay budget of the multi-patterning solutions at advanced nodes, it may represent significant patterning risk.

Figure 2. Stitch location (a) and inter-pattern space (b) after traditional OPC when each pattern is processed sequentially. Same stitch and inter-pattern space locations corrected with the MP-aware OPC functionality are shown on (c) and (d) respectively.

In addition to the traditional process window-aware correction, an MP-enabled OPC can improve the amount of overlap at the pattern-stitching regions and enforcing inter-pattern spacing. Figure 2 shows an example of MP-aware OPC outperforming the traditional sequential correction and creating robust stitching regions that keep healthy pattern separations. Compare the stitch location in (a) and inter-pattern space in (b), both of which are results from traditional OPC, to the same stitch and inter-pattern space when processed with MP-aware OPC. A 15% increase in overlay between two patterns (c) and 50% increase in spacing between the patterns (d) will directly translate into a healthier patterning process.

Together with the traditional OPC algorithms that solve fragment placement problems, MP-aware OPC should work with today’s multiple fragment movement solver.  A fragment movement solver for advanced nodes should incorporate the influence of neighboring fragments into the feedback control of fragment movements for full-chip OPC3,4.—referred to as matrix OPC. The formation of a matrix is illustrated in Figure 3.

Figure 3. Edge placement error calculation and matrix generation in Calibre Matrix OPC, an edge-based, full-chip level, enhanced OPC that scales to large numbers of CPUs just as traditional OPC does and with comparable runtime.

Figure 4 compares the results of different OPC algorithms. Even compared to specially tuned OPC recipe, the matrix OPC achieves significant convergence improvement.

Figure 4. Via layer, double patterning case. Convergence comparison between different flavors of OPC algorithms.

The next topic of this narrative is the out-of-main-image-plane effects – phenomena that occur in the photoresist layer close to its surface such as printing SRAFs and resist top loss.

The ability to handle SRAF printing has been available for single pattern applications for several years now and it is important to ensure the same functionality is available for MP cases as well. Advanced solutions have overcome the complexity of handling multiple SRAF layers placed across multiple patterns, and also added a capability of negative SRAF handling and correction. An image of MP SRAF printing is shown in Figure 5. One might think this would add complexity to the OPC setup files, but there are ways to create a cleaner and simpler SRAF print avoidance interface while minimizing run time impact by careful simulation management.

Figure 5. Interconnect layer, double patterning case. SRAF shape is eliminated due to printing. Polygons belonging to sraf_p2 are not shown.

A mask shape correction—based on a specially calibrated resist top-loss model—reduces the loss of material from the top of the photoresist surface Photoresist top loss correction in many cases can be treated as a special process window condition whose simulated contour is extracted from the upper layer of the photoresist – a phenomenon that is analogous to the SRAF printing case but different in the final outcome. Unlike SRAF print avoidance, the top loss compensation has to be applied to the main shape in order to eliminate a potential hot spot. Figure 6 shows an example of such correction carried out for the interconnect layer.

Figure 6. The image on the left shows hot spots related to resist top loss, which are eliminated in the picture on the right. The histogram shows the hot spot critical dimensions. Top loss-aware correction eliminates every location with critical dimensions <24nm.

In summary, at 10nm and below, the industry needs to adopt new OPC technologies. With the wide acceptance of the new-generation negative tone development photoresists, and transition of the OPC models from thin mask approximations to more complex models that take into account reticle 3D effects, there is no question that techniques like custom advanced OPC techniques will be required at 10nm and below.

As technical challenges grow and intertwine with the manufacturing process marginalities previously deemed as non-critical, it is important that OPC engineers engage with their counterparts in EDA to develop the flows and setup files for their sub-14nm technologies.. The increased flow complexity due to introduction of advanced OPC techniques can affect the OPC recipe turn-around-time, but there are strategies to control the impact and keep the OPC solutions production friendly.

References

  1. “Mark Twain Amused”, New York Journal, 2 June 1897
  2. W.H. Arnold, M.V. Dusa, J. Finders, “Metrology challenges of double exposure and double patterning,” Proc. SPIE, Vol. 6518
  3. Model-based OPC using the MEEF matrix, Nicolas B. Cobb ; Yuri Granik, Proc. SPIE, Vol. 4889
  4. Model-based OPC using the MEEF matrix II, Junjiang Lei, Le Hong, George Lippincott, James Word, Proc. of SPIE Vol. 9052

Vlad Liubich is a Product Manager for Calibre OPC at Mentor Graphics, with over 15 years of experience. Before joining Mentor, he served for 11 years in various engineering roles at Intel. He holds a BSc from the Moscow Institute of Steel and Alloys, Physical Chemistry Department in Russia and a MSc from Ben Gurion University in Negev, Beer Sheva, Israel. Vlad can be reached at vlad_liubich@mentor.com.