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This IP Will Work…I GUARANTEE It!

By Matthew Hogan, Mentor Graphics

Intellectual property (IP) is usually bought from a 3rd party vendor or developed by a specialized internal IP group. This group performs testing to ensure the IP will work as designed. As the chip designer, you merely insert the IP into the IC design and make the necessary connections. Easy-peasey!

Except…robust design requires more than verifying each separate block—you must also verify that the overall design is robust. When you are using hundreds of IPs sourced from multiple suppliers in a layout, how do you ensure that the integration of all those IPs is robust and accurate?

For instance, IP is often designed with a certain set of design constraints and operating parameters in mind. As a chip designer, do you know what these conditions are when you place IP in your layout? How do you make sure you have implemented an IP in a way that conforms to the supplier’s “assumed” use model? Will the operating conditions of the overall SoC fall within each IP supplier’s design envelope? Using an IP validation process like TSMC9000 (TSMC’s IP Validation Center) helps IP designers ensure the IP is robust as a standalone component, but SoC designers must still verify that the IP is correctly implemented in the full-chip context.

The reality is that many IC reliability issues are actually the result of design flaws, not manufacturing issues per se, and involve subtle, longer-term effects like oxide degradation that cannot easily be detected by traditional production tests on the manufacturing line. Some of these result from incorrect use of IP, and are essentially design flaws. These problems can be particularly vexing in the area of electrostatic discharge (ESD) protection of cells, and input/output (I/O) pads with embedded ESD structures. The challenge is complicated by the presence of multiple power domains, because validation of the signal interactions between IPs is essential to ensuring correct and reliable behavior over the complete range of operating power states.

Consequently, it is critically important that IPs in a design are subjected to comprehensive circuit reliability checking in the context of the overall SoC. To automate this requirement, designers need a class of tools that can integrate several capabilities, including circuit classification, physical layout measurements, complex device interactions, and rule-driven circuit checking. The combination of these facilities allows designers to automate many of the circuit checks required to ensure SoC reliability. At the same time, guidelines for circuit reliability checking are emerging—some of them are proprietary to individual companies, while others have been defined collaboratively by open interest or standards groups. The ESD Association (ESDA) provides ESD verification guidelines [1], and the Silicon Integration Initiative (Si2) also recommends a standard ESD protection design flow methodology. Both of these trends (tools and methods) are having a significant impact on our ability to identify and remove design flaws that reduce long-term IC reliability.

For example, designers can validate the proper implementation of power design intent at the transistor level by combining Unified Power Format (UPF) power state tables (PSTs) with the transistor-level validation capabilities of a reliability verification tool like Calibre® PERC™. This can be done for both standalone IP and in the context of the full SoC in the same flow, providing both a timely reliability verification process and transistor-level accuracy and scalability from individual IP to full chip.

This approach is particularly handy in verifying that IPs dropped into a design have the required ESD protection. To protect SoCs from ESD, protection circuitry must be applied across I/Os and power lines. While interconnect routing is mostly automated in physical digital design, in practice, portions of I/O and power and ground routing are frequently completed manually. Designers following a typical routing strategy try to implement wires with enough “total width” for ESD protection when they have to split a wire to connect to a lower level of interconnects. To enforce this ESD design practice, the foundry assigns a minimum wire width to meet the ESD requirement (which varies per layer), and a design rule check (DRC) to ensure compliance. However, DRC checking alone is not effective because a measure of the total wire width does not ensure interconnects are safe in the presence of an ESD event.

It is actually current density that is directly correlated to ESD failure. If the current density along the ESD path on some wire segment or via region is too high, then that wire segment/via region is susceptible to ESD failure (Figure 1). Using Calibre PERC, a designer can perform a simulation along the ESD path to determine the current density on each wire segment and via area. With these current density measurements, the foundry-defined effective wire width can be converted to a current density constraint to be checked against the simulated current density.

Figure 1: Even if a wire width measurement meets foundry criteria, it may not be sufficient to provide adequate ESD protection.

The tool also checks the topology of the design for appropriate implementation of ESD structures and their placement with respect to devices to be protected and the core of the IC. It allows implementation of the ESD checks recommended by ESDA, such as layout checks, netlist checks, and current density checks, to name a few important ones. It can also identify the omission of required ESD protection devices on a schematic or netlist, and it can look for errant signal paths and other soft connection errors. These checks include well connection errors, floating devices, nets, pins, incorrect voltage supply connections, excessive series pass gates, problem-level shifter designs, guard ring and antenna checks, floating wells, and minimum “hot” NWELL widths.

Guarantees are nice, but at the end of the day, you need to make sure that you have implemented all IP blocks in a compatible way that works as a system, including all ESD protection. Validating IP blocks in the context of your design is a necessary part of the IC verification process, and the only sure way to do that is to understand all interactions and eliminate subtle design flaws.


[1] ESD Electronic Design Automation Checks, ESDA TR18.0-01-11, EDA Tool Working Group


Matthew Hogan is a product marketing manager for the Calibre Design Solutions group at Mentor Graphics with over 15 years of design and field experience. He is an IEEE Senior Member and ACM Member and holds a Bachelor of Engineering from the Royal Melbourne Institute of Technology and an MBA from Marylhurst University. He is actively working with customers who have interest in Calibre PERC and 3D-IC. He can be reached at

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