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Intensive Gardening: What to Expect When Filling Designs at 20nm and Below

By Jeff Wilson, Mentor Graphics

The word “garden” usually brings to mind tidy rows of vegetables, each neatly separated from its neighbor by the prescribed growing space. But there is another approach, often called “intensive” or “square foot” gardening, that places multiple plant types closely together. By interplanting compatible plants in a small space, a gardener can actually increase yield over a traditional garden, using far less area. However, intensive gardening requires a different mindset and approach to maintenance to ensure good results.

Designers beginning to design at 20 or 16nm might do well to think about “intensive gardening” as a metaphor for the changes they will encounter in fill technology and processes at these nodes. Let me explain why…

The most obvious change in any new node is the reduction in feature size. At 20nm and below, the changes in feature size lead to a plethora of new manufacturing effects and requirements. In addition, while features get smaller, chips don’t. A typical design in the newest technologies exceeds 15 mm on a side. Because there is a significant cost associated with moving to any new node, design teams focus on designs that are most likely to generate a profit, meaning they will want to incorporate as much functionality and as many features as possible. These designs trigger longer verification runtimes due simply to the increased number of features to be verified, and the increase in design rule coverage.

One of the major changes that occur at 20nm due to this increased manufacturing complexity is the approach to non-functional metal fill. At older technology nodes, designers added large fill shapes to open design areas because a certain metal density was required to pass the foundry’s density design rule checks (DRC). Intended to improve planarity for manufacturing by reducing thickness variations created during chemical-mechanical polishing (CMP) processes, the fill process was fairly simple—you defined an area to fill, and your tool filled the area with pre-defined shapes of a specific size and spacing. To avoid creating parasitic capacitance issues, the goal was to add only as much fill as needed to satisfy the minimum and maximum density requirements.

At 20 nm and below, the complexity and expansion of manufacturing requirements compel designers to completely change their fill strategy. These designs entail explicit and complex new analysis during the filling process to account for the new manufacturing rules that require designers to balance density constraints against the amount of capacitance added to the design, and to ensure that design rule checking (DRC) constraints are met. To combat issues associated with rapid thermal annealing (RTA), fill is now added as a multi-layer fill cells. For example, the base layers in the transistors, such as poly and diffusion, are added as cells. New rules for metal layers require the insertion of multiple fill layers, and the validation of constraints on a layer-by-layer basis. Density constraints include gradient rules that control density variations between adjacent windows, but some of the new requirements also include the analysis and balancing of perimeter values on a layer-by-layer basis. At 20nm and 16nm, the goal of multi-patterning is to balance the light that passes through the mask. Multi-patterning constraints must be taken into account when adding fill, as the fill shapes, along with the other polygons, must be properly decomposed into multiple mask assignments. Fill can also now be used to improve the results of electrochemical deposition (ECD), etch, and lithography, as well as to minimize the impacts of stress effects. Optical proximity correction (OPC) fill, which is smaller and placed in close proximity to design features, improves the uniformity of the interconnect, reducing the amount of parasitic capacitance generated and boosting its manufacturability.

As a result of all these new applications of fill, both the amount of fill and the number of fill shapes has increased. To give you a sense of the impact of the smaller size and tighter spacing of the fill shapes, the same open area in a 20nm design has seen an order of magnitude difference in the amount of fill added when compared with a 65nm design. These new manufacturing requirements require a fill strategy that now focuses on maximizing the amount of fill added to a design.

To provide-correct-by-construction results, fill tools must support all of the new and expanded DRC rules introduced at 20 nm and below, including spacing checks such as Euclidian, elliptical, pitch, and width-based rules. Additionally, because fill no longer comprises just a few fill shapes on one layer, fill analysis must now take into account groupings of related layers and fill shapes.

While all of these changes help ensure the manufacturability and performance of advanced node designs, they have had a tremendous impact on fill runtimes and database size. Significantly increasing the number and variety of fill shapes used, and adding new, complex fill rules, requires substantial increases in processing time and creates huge output files that impact transfer times when compared to past nodes. New fill techniques and tools seek to reduce both fill file size and fill runtimes with a variety of new strategies and analytical optimizations.

One way to deal with the file size increase is to raise the level of abstraction by moving from individual polygons to a cell-based fill solution, defining a multi-layer pattern of fill shapes that can be repeated in many places across the chip. These fill cells are a natural extension of multi-level fill constructs, and can be used for both front end of line (FEOL) and back end of line (BEOL). The cell-based approach helps reduce both runtime and file size, which helps maintain project schedules.

Correct-by-construction capabilities that combine a rules-based approach with sophisticated analysis algorithms to analyze items such as layout density (including gradient) and polygon perimeters help ensure that the insertion of dummy metal is accurately optimized for each layout, while minimizing fill runtimes. Correct by construction flows also require a detailed knowledge of the new design rules for such constraints as forbidden pitch and shielding.

Another design parameter that must be managed is the timing closure loop. The important fill factor here is the ability to support a net-aware fill strategy (to protect critical nets by enforcing a user-defined distance from specified nets to any fill shapes). However, with the explosion in fill shapes, customers are opting to keep the fill in a separate file, and then merge the drawn design and the fill shapes when extraction for timing verification is run, or when an ECO fill flow is required.

In addition, because design teams use a wide variety of EDA tools, fill solutions that support standard interfaces ensure that designers can easily execute a foundry-certified fill solution that addresses the newly complex fill technology from within their preferred design implementation tool. This ability to interact with a variety of toolsets can be critical, given that tools can change from one node to the next. Designers working with tools that use proprietary interfaces to communicate may find themselves left behind when they move to the next node, unable to effectively implement the new required “smart” fill techniques.

Intensive fill techniques, like intensive gardening, require more attention to detail than previous fill strategies. Using the right tools can help minimize the effects on fill runtimes and databases, while ensuring accurate, timely results.

Jeff Wilson is a DFM Product Marketing Manager in the Calibre organization at Mentor Graphics in Wilsonville, OR. He has responsibility for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Jeff previously worked at Motorola and SCS. He holds a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon. Jeff may be reached at

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