By Matt Hogan, Mentor Graphics
In today’s complex, specialized world, system on chip (SoC) designs contain many different types of intellectual property (IP), some obtained from multiple suppliers and others developed by internal design teams. At the same time, today’s low-power SoCs often contain multiple power domains. When many IPs are intermingled on an SoC, and assigned to multiple power domains, validation of the signal interactions between these IPs is essential to ensuring correct and reliable behavior in the complete range of operating power states.
A power domain is often thought of as a specific voltage value. Power domains may contain one to many IPs. Very often, each IP has multiple power states. These control how much power that IP uses in each state, and how much effort is required to change its operating state. Signal interaction validation was considered to be relatively simple when there were only one or two power domains in the design and very little interaction between design blocks. However, this same validation becomes complex and difficult when multiple power domains exist with multiple power states.
The performance and functionality gains of low-power designs that leverage multiple power domains are well-known, but without accurate reliability verification, these designs will never make it to market. Ensuring the reliability of your designs requires an understanding of how signals cross multiple power domains for both the individual IP and the full SoC. Figure 1 shows a three power domain design, requiring validation of the interactions within and across these power domains.
Reliability challenges abound. Designers look to avoid stressing thin-oxide gates by confirming the correct connectivity to the correct power domain to help minimize potential issues. While not an immediate failure, stressing thin-oxide gates results in a failure over time and is a concern for long term reliability. Designers must ensure that the correct level shifters, retention cells, and other design elements have been accurately placed for each of the different power domains. They must also validate the accuracy of bulk and well connections at the transistor level.
Some design teams may consider leaving design margin on the table by choosing a very simple power structure that can be easily validated. While that was once an acceptable design choice for market segments that did not include handheld and portable devices, in today’s market, even directly-powered devices (those that plug into a wall power socket) are looking to reduce power consumption with the use of multiple power domains.
So, how do we verify these multi-IP, multiple power domain SoCs?
The Unified Power Format (UPF) enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level. It can help simplify multiple power domain verification by enabling a consistent description of the power intent throughout the design flow. UPF support for power state tables (PSTs) enables verification of each power mode within the design. Figure 2 shows a typical PST for a three power domain design.
Transistor-level power intent verification is critical in designs that make extensive use of IP. Because SOCs can contain many IPs from different sources, and these IPs may all use different power methodologies, or contain their own internal global signals, correctly hooking up all of the IPs within the design is extremely challenging. If the design team does not understand the power intent of each IP, it’s very difficult to proactively prevent reliability issues (such as power domain crossing errors) from occurring when the IP is placed into the SoC. In Figure 3, the voltages internal to the IP block look consistent, but it’s been hooked up incorrectly in the SoC implementation.
Power state tables are a useful tool at the IP level, but describing power states for a complete SoC design can be incredibly difficult—how do you validate the interactions between all those IP blocks? Not only that, but the analysis of each set of table interactions is a one-time effort—the next SoC design will use some different IPs, or different versions of IPs, so the interdependencies will also be different, requiring an entirely new set of tables. Detailed SPICE simulation is not a viable option in these SoCs, because simulation of multiple domain designs requires the designer to not only include the power controller chip, but also to have the design cycle through multiple power transitions, which requires carefully chosen input vectors and produces long simulation times.
Figure 4 demonstrates a typical UPF tool flow. The power intent is described at the HDL/RTL level in the UPF file for the logic design. The UPF file is updated during the synthesis flow, and again during the place and route process. During verification, Calibre PERC can be used with either the GDS or LEF/DEF design, or the netlist (prior to physical implementation), to verify power intent.
While traditional UPF flows do not validate the final transistor implementation, especially for well and bulk connectors, reliability checking tools such as Calibre PERC can use the UPF’s description of power intent to validate power and reliability requirements at the transistor level to provide a comprehensive and deterministic reliability verification strategy for SoCs. Designers define a PST for each IP block in the SoC. Calibre PERC then merges these PSTs to enable transistor-level verification across the full SoC (Figure 5). The merged PST provides the understanding of the interactions and state overlaps needed at the SoC level to manage the reliability verification complexity. Calibre PERC examines the UPF definitions of supply networks and checks each supply port’s supply states and its connected supply net, then analyzes the power state tables defined in terms of these states to ensure it captures the legal combinations of supply voltages in the context of the entire design.
Accurate and repeatable reliability verification is now a critical capability, both for increasingly complex products being produced at established nodes and for the new designs emerging at advanced nodes. By combining UPF PSTs with the transistor-level validation capabilities of a reliability verification tool like Calibre PERC, designers can now validate power intent at the transistor level, both in standalone IP and as part of a full SoC, in the same flow, providing both a timely reliability verification process and transistor-level accuracy and scalability in reliability verification from IP to full chip.
Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. He is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at email@example.com.