Part of the  

Solid State Technology


About  |  Contact

How Critical Area Analysis Optimizes Memory Redundancy Design

March 8th, 2017

By Simon Favre, Mentor Graphics


As any design engineer knows, the farther downstream a design goes, the less likely a manufacturing problem can be corrected without a costly and time-consuming redesign. And it doesn’t matter if you are a fabless, fab-lite, or independent device manufacturer (IDM) company—reducing a design’s sensitivity to manufacturing issues should ideally be handled by the design teams. By identifying and resolving design for manufacturing (DFM) problems while the design is still in its early stages, many manufacturing ramp-up issues can be avoided altogether.

For example, embedded memories often cover 40-60% of the chip area in a large system-on-chip (SoC) design. The densely packed structures in memory cores make them very susceptible to random defects, so redundant elements are often added to embedded memories to improve final yields. However, if redundancy is applied where it has no benefit, then die area and test time are wasted, which actually increases manufacturing cost. Unnecessary redundancy can be a crucial and costly mistake. Using critical area analysis (CAA) to perform a detailed analysis of your design redundancy can accurately quantify the yield improvement that can be achieved, while minimizing impact on chip area and test.

Critical Area Analysis

The basic CAA process calculates values for the average number of faults (ANF) and yield based on the probability of random defects that introduce an extra pattern (short) or missing pattern (open) into a layout, causing functional failures (Figure 1).

Figure 1. Definition of critical area based on extra pattern (short) and missing pattern (open).

In addition to classic shorts and opens calculations, CAA techniques also analyze potential via and contact failures. In fact, once CAA is applied, via and contact failures often prove to be the dominant failure mechanisms (Figure 2). Other failure mechanisms can also be incorporated into CAA, depending on the defect data provided by the foundry.

Figure 2. Pareto of ANF values for defect types in a large SOC. The dominant defect type in this analysis is contact to diffusion.

As shown in Figure 3, critical area increases with increasing defect size. In theory, the entire area of the chip could be a critical area for a large enough defect size. In practice, most foundries limit the range of defect sizes that can be simulated, based on the range of defect sizes they can detect and measure with test chips or metrology equipment.

Figure 3. Critical Area CA(x) in square microns as a function of defect size in nanometers for one defect type.

Defect Densities

Semiconductor foundries have various proprietary methods for collecting defect density data associated with their manufacturing processes. To be used for a CAA process, this defect density data is converted into a form compatible with the CAA tool. The most common format is a simple power equation, as shown in equation (1). In this equation, k is a constant derived from the density data, x is the defect size, and the exponent q is called the fall power. The foundry curve-fits the opens and shorts defect data for each layer to an equation of this form to support CAA. In general, a defect density must be available for every layer and defect type for which critical area will be extracted. However, in practice, layers that have the same process steps, layer thickness, and design rules typically use the same defect density values.


Defect density data may also be used in table form, where each specific defect size listed has a density value. One simplifying assumption typically used is that the defect density is assumed to be 0 outside the range of defect sizes for which the fab has data.

Calculation of ANF

Once the critical area CA(x) is extracted for each layer over the range of defect sizes, the defect density data D(x) is used to calculate ANF according to equation (2), using numerical integration. The dmin and dmax limits are the minimum and maximum defect sizes according to the defect data available for that layer.

(2)ANF=∫_dmaxdmin CA(x)∙D(x) dx

In most cases, the individual ANF values can simply be added to arrive at a total ANF for all layers and defect types. Designers take note: ANF is not strictly a probability of failure, as ANF is not constrained to be less than or equal to 1.

Calculation of Yield

Once the ANF is calculated, one or more yield models are applied to make a prediction of the defect-limited yield (DLY) of a design. One of the simplest, most widely-used yield models is the Poisson distribution, shown in equation (3). Of course, DLY cannot account for parametric yield issues, so care must be taken when attempting to correlate these results to actual die yields.

(3) Y = e-ANF

ANF and Yield for Cut Layers

Calculation of ANF and yield for cut layers (contacts and vias) is generally simpler than for other layers. In fact, most foundries define a probabilistic failure rate for all single vias in the design, and assume that via arrays do not fail. While this simplifying assumption neglects the problem that a large enough particle will cause multiple failures, it greatly simplifies the calculation of ANF, in addition to reducing the amount of data needed from the foundry. All that is required is a sum of all the single cuts on a given layer, and the ANF is then simply calculated as the product of the count and the failure rate, shown in equation (4).


Once the ANF(via) is calculated, it can be added to the ANF values for all the other defect types, and used in the yield equation (3). Vias between metal layers may all use one failure rate, or use separate rates based on the design rules for each via layer. The contact layer can be separated into contacts to diffusion (N+ and P+ separately, or together), and contacts to poly, each with separate failure rates.

Memory Redundancy

As stated earlier, embedded memories can account for significant yield loss due to random defects. Typically, SRAM intellectual property (IP) providers make redundancy a design option, with the most common form of redundancy being redundant rows and columns. Redundant columns tend to be easier to apply, as the address decoding is not affected, only the muxing of bitlines and IO ports.

Memory Failure Modes

Every physical structure in a memory block is potentially subject to failures caused by random defects, classified according to the structures affected. The most common classifications are single-bit failures, row and column failures, and peripheral failures (which can be further subdivided into I/O, sense amplifier, address decoder, and logic failures). In terms of repair using memory redundancy, our primary interest is in single-bit row and column (SBRC) failures occurring in the core of the memory array.

To analyze SBRC failures with CAA, designers must define which layers and defect types are associated with which memory failure modes. By examining the layout of a typical 6-T or 8-T SRAM bit cell, some simple associations can be made. For example, by looking at the connections of the word lines and bit lines to the bit cell, we can associate poly and contact to poly on row lines with row failures, and associate diffusion and contact to diffusion on column lines with column failures. Because contacts to poly and contacts to diffusion both connect to Metal1, the Metal1 layer must be shared between row and column failures. Obviously, most of the layers in the memory design are used in multiple places, so not all defects on these layers will cause failures that can be repaired. There are also non-repairable fatal defects, such as shorts between power and ground. Given that a single-bit failure can be repaired with either row or column redundancy, we’ll ignore these differences for now.

Repair Resources

Embedded SRAM designs typically make use of either built-in self-repair (BISR) or fuse structures that allow designers to mux out the failed structures and replace them with redundant structures. BISR has greater complexity, with greater impact on die area. Muxing with fuses requires that the die be tested, typically at wafer sort, and the associated fuses blown to accomplish the repair. The fuse approach has the advantage of simplicity and reduced area impact, although at the expense of additional test time. Regardless of the repair method, placing redundant structures in the design adds area, which directly increases the cost of manufacturing the design. Additional test time also increases cost, and designers may not have a good basis for calculating that cost. The goal of analyzing memory redundancy with CAA is to ensure that DLY is maximized, while minimizing the impact on die area and test time.

Specification of Repair Resources

For a CAA tool to accurately analyze memory redundancy, it requires a specification of the repair resources available in each memory block. This specification must also include a breakdown of the failure modes by layer and defect type, and their associated repair resource. The layer and defect type together are typically called a CAA rule. Each rule with an associated repair resource must be in a list of all rules associated with that repair resource. Since some rules will be associated with both row and column failures, some means of specifying rule sharing is needed.

For each memory block, the count of total and redundant rows and columns is required. To specifically identify the areas of the memory that can be repaired, the designer must either specify the bitcell name used in each memory block, or use a marker layer in the layout database. This identification allows the CAA tool to identify the core areas of the memory.

Figure 4 shows a typical memory redundancy specification. The first line lists the CAA rules that have redundant resources for a particular family of memory blocks. The two lists are column rules, followed by row rules. The two lines at the bottom show SRAM block specifications and specify (in order) the block name, the rule configuration name, the total columns, redundant columns, total rows, redundant rows, dummy columns, dummy rows, and the name of the bitcell. In this example, both block specifications refer to the same rule configuration. Given these parameters, and the unrepaired yield calculated by the CAA tool, it is possible to calculate the repaired yield.

Figure 4. Memory configuration specification showing layers and defect types with redundant resources.

Yield Calculation with Redundancy

Once the CAA tool performs the initial analysis, it can calculate the yield with redundancy. The initial analysis must include the ANF(core) of the total core area of each memory block listed in the redundancy configuration file. Since the calculation method is the same, each row or column in a memory core can simply be referred to as a “unit,” and the calculation method only needs to be described once. If present, dummy units do not cause functional failures, and do not need to be repaired (in the initial analysis, dummy units do contribute to the total ANF, as the CAA tool has no knowledge of whether or not they are functional).

Calculation Method

The calculation method is based on the well-known principle of Bernoulli Trials. The goal is to get the required number of good units out of some total number of units. First, the tool calculates the number of active units in the core, as shown in equation (5).


Where NA is the required number of active units, NT is the total units, NR is the redundant units, and ND is the dummy units. In equation (6), the tool derives the number of functional non-dummy units.

(6) NF=NT-ND

Next, it calculates the unit ANF in equation (7).

(7) ANF(unit)=ANF(core)/NT

To be consistent with probability theory, the tool converts ANF(unit) back to a yield, using the Poisson equation in equation (8). This value becomes the p term in the Bernoulli equation, which denotes probability of success. The probability of failure, q, is defined in equation (9).

(8) p=Y(unit)=e-ANF(unit)

(9) q=1-p

Now the tool must add together the probabilities of all cases that satisfy the requirement of getting at least NA good units out of NF available units. The result, calculated in equation (10), is the repaired yield for that memory core for that specific rule. This process is repeated over all rules in the memory configuration specification, and all memory blocks listed with redundancy.

(10) YR=∑k=0k=NR C(NF,(NF-k))∙p(N_F-k)∙qk

Note that the case where k=0 is necessary to account for the possibility that all units are good. The term C(NF,(NF-k)) is the binomial coefficient, which evaluates to 1 if k=0. For any memory core or rule where no repair resources exist, the calculation in equation (10) is skipped, and the result is simply the original unrepaired yield.

Calculating the effective yield for memory blocks with no redundancy is still valuable if the CAA tool has the capability of post-processing the calculations with a different memory redundancy specification. This enables a “what-if” analysis, which can be crucial for determining whether or not applying redundancy adds more value than the inherent cost of adding it to the design. If the what-if analysis can be done without repeating the full CAA run, then iterating on a few memory redundancy configurations to find the optimum is quite reasonable. In addition, if the tool reports the intermediate calculations for each term in the Bernoulli Trials, the point of diminishing returns can easily be identified. This prevents costly overdesign of the memories with redundancy.


The technique presented has some limitations, but can still be applied with relative ease to determine optimal redundancy parameters. The obvious limitations are:

  • The test program must be able to distinguish the case where a failure on a redundant unit has occurred, but all the active units are good. This case requires no repair.
  • There is no accounting for fatal defects that cannot be repaired, such as power to ground shorts.
  • The redundancy calculation is applied only to the core bitcells, but redundant columns, for example, may include the sense amp and IO registers.
  • The CAA rules apply to specified layers and defect types anywhere within the memory core, not to specific structures in the layout. If a method existed for tagging specific structures in the layout and associating them with failure modes or rules, the calculation would be more accurate.
  • Algorithmic repair, such as data error correction, is beyond the scope of CAA analysis.


Memory redundancy is a design technique intended to reduce manufacturing cost by improving die yield. If no redundancy is applied, then alternative methods to improve die yield may include making the design smaller, or reducing defect rates. If redundancy is applied where it has no benefit, then die area and test time are wasted, which actually increases manufacturing cost. In between these two extremes, redundancy may or may not be applied depending on very broad guidelines. If defect rates are high, more redundancy may be needed. If defect rates are low, redundancy may be unnecessary. Analysis of memory redundancy using CAA and accurate foundry defect statistics is a valuable process that helps quantify the yield improvement that can be achieved, and determine the optimal configuration.


[1]   Stapper, C.H. “LSI Yield Modeling and Process Monitoring,” in IBM Journal of Research and Development, Vol. 44, p. 112, 2000. Originally published May 1976.

[2]   Stapper, C.H. “Improved Yield Models for Fault-Tolerant Memory Chips,” in IEEE Transactions on Computers, vol. 42, no. 7, pp. 872-881, Jul 1993.
doi: 10.1109/12.237727


Simon Favre is a Technical Marketing Engineer in the Design to Silicon division at Mentor Graphics, supporting and directing improvements to the Calibre YieldAnalyzer and CMPAnalyzer products. Prior to joining Mentor Graphics, Simon worked with foundries, IDMs, and fabless semiconductor companies in the fields of library development, custom design, yield engineering, and process development. He has extensive technical knowledge in DFM, processing, custom design, ASIC design, and EDA. Simon holds BS and MS degrees from U.C. Berkeley in EECS. He can be reached at

Context-Aware Latch-up Checking

September 28th, 2016

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

Latch-up in CMOS circuits is a long-studied and troubling phenomenon that often leads to chip failure through the inadvertent creation of parasitic PNP and NPN junctions being driven (turned on/forward-biased). Typically, an unintended thyristor or silicon-controlled rectifier (SCR) is formed and then triggered to generate a low-resistance parasitic path. Latch-up presents itself as a temporary condition that may be resolved by power cycling, but it may also cause fatal chip failure or permanent damage.

Recognizing unintentional failure mechanisms present in an integrated circuit (IC) is a constant and often difficult task for design teams. Increases in design complexity, larger pin counts, more power domains, and the ever-changing landscape of what process node and which foundry will host your next design all contribute to the challenge. Additionally, many of the geometric design rule checks (DRC) traditionally employed for latch-up detection lack the context awareness that modern reliability verification tools can provide. However, getting it right, particularly when you are trying to find and eliminate latch-up in your designs, is of critical importance.

Although no design team enjoys further complicating design and verification flows by adding additional checks, a fully automated latch-up rule check is highly desirable, particularly when multiple power domains are involved. Just as voltage-aware DRC checking [1][2] has provided a significant improvement in the accuracy and control of interconnect spacing for reliability and the avoidance of time-dependent dielectric breakdown (TDDB), context-aware latch-up verification offers similar advantages and opportunities to automate these challenging design interactions.

When considering the impact of latch-up on a layout, understanding both the unintentional devices within your design and how the layout impacts critical distances of specific latch-up susceptible structures is critical. For example, to be able to adjust the layout to prevent latch-up, designers must recognize where unfavorable conditions may lead to unintended parasitic devices formation in the PNP or NPN junctions as current is injected. Figure 1 shows how lateral separation can be used to protect against latch-up formation.


Figure 1 - Latch-up prevention with lateral separation [3

Impact of voltages and devices

While understanding the distances and physical layout within the design is essential, consideration must also be given to the voltages being used. As with voltage-aware DRC, the voltages being analyzed for potential latch-up conditions have a significant impact on the spacing rules that must be applied. The interaction of these voltages can greatly influence the location of susceptible regions in the design, as well as the location and degree of change necessary to avoid this susceptibility (Figure 2).


Figure 2 - Accurate latch-up checks require voltage awareness [3

While a single simple spacing rule may be all that is required with just a few voltages, the complexity of the protection needed increases as more power domains are included. How these domains switch, with different parts of the design being active at different times, adds to this complexity. The ability to leverage the power intent of your design, particularly through descriptions created using the Unified Power Format (UPF), enables a state-driven approach to determine what voltages are present in any given state.

What CMOS technology are you using: Bulk, FD-SOI or Both?

While much of the literature on latch-up assumes that the implementation technology impacted by latch-up is entirely bulk CMOS, and that fully-depleted silicon-on-insulator (FD-SOI) is immune, there are hybrid technologies that leverage characteristics of both FD-SOI and bulk CMOS. One such technology that comes to mind is the ultra-thin body and box (UTBB) FD-SOI process used by ST Microelectronics [4]. UTBB leverages the benefits of a FD-SOI process for the design logic, while taking advantage of a “hybrid” bulk CMOS for electrostatic discharge (ESD) and IO devices. For ESD protection, the ESD device in thin silicon film is two times less robust than the bulk CMOS device (due to the smaller thickness of the Si film for power dissipation). Leveraging an open box structure to access hybrid bulk CMOS configurations to build ESD power devices provides benefits for device robustness. In doing so, however, verification needs to consider possible sources of susceptibility to latch-up in areas of the design with hybrid bulk CMOS IO devices and ESD structures.


While traditional DRC has contributed to a valuable verification methodology for latch-up, it lacks the fidelity and context to fully identify the latch-up susceptible regions in your design. Learning and applying the latest reliability analysis techniques to solve these often intricate and complex verification requirements for latch-up detection, while also developing process improvements to avoid susceptible configurations in future designs, is critical from a best practices perspective.

To assist designers looking to integrate this technology into their design and verification flows, the ESD Association (full disclosure: I am a volunteer and serve on the Board of Directors) has extended its educational offerings in the area of latch-up detection to include these types of complex verification. A new course, DD382: Electronic Design Automation (EDA) Solutions for Latch-up [5], reviews a typical latch-up prevention flow, and delves into details necessary for improvement.

The continued evolution of your organization’s reliability verification checks and best practices, along with the evaluation and adoption of best practices from the industry as a whole, should not only be an aspiration, but a measurable goal to keep your design flows current. Incorporating new learnings into existing flows helps improve both their robustness and relevance for today’s complex designs, and leverages efficiencies learned in the development of new solutions. Latch-up, like many design flow challenges, provides significant opportunities for process improvement and flow automation in the ongoing effort to implement robust and repeatable verification solutions.

Further Reading:

How to Check for ESD Protection Using Calibre PERC High Level Checks


[1] Medhat, Dina. “Automated Solution for Voltage-Aware DRC,” EETimes SOC DesignLIne, December 23, 2015.

[2] Hogan, Matthew, et al. “Using Static Voltage Analysis and Voltage-Aware DRC to Identify EOS and Oxide Breakdown Reliability Issues.” EOS/ESD Association Symposium, 2013.

[3] Khazinsky, Michael. “Latch-up Verification / Rule Checking Throughout Circuit Design Flow.” Mentor Graphics User2User, 2016.

[4] Galy, Philippe. “ESD challenges for FDSOI UTBB advanced CMOS technologies.” International Electrostatic Discharge Workshop, 2014.

[5] EOS/ESD Association Symposium Tutorials, EOS/ESD Association Symposium, 2016.


Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at

Established Technology Nodes: The Most Popular Kid at the Dance

August 24th, 2016

By Michael White, Mentor Graphics

I remember back in the day at high school dances, always wanting to dance with the most popular girl in school. I never could, because there were a constant stream of others queued up to dance with her. If you are trying to build an integrated circuit (IC) today, and trying to get fab capacity at 28nm and above, you are faced with the very same situation. Lots of suitors jockeying for access. There are two interesting points to be explored here: 1) why are these nodes experiencing such a long life, and 2) how is this long life driving new challenges for designers?

Why Established Nodes Are Experiencing an Unexpectedly Long Life

The Internet of Things (IoT) means many things to many people, but the segment of IoT related to sensors and connectivity is the answer to the longevity question. The functionality we crave, such as smart power management for longer battery life, and Wi-Fi and Bluetooth for more connectivity, are more cost-effective when implemented at established nodes between 40 nm and 180 nm. Consequently, the high consumer demand for these capabilities is driving increased demand for ICs manufactured using these processes. In a nutshell, the nodes that best support radio frequency (RF) and mixed-signal IC designs with low power, low cost and high reliability are seeing a much higher demand than in the past.

The other dynamic driving a longer than expected life of established nodes—40/45 nm and 32/28 nm in particular—is the wafer cost trend at 20 nm and below. 20 nm and below are well-suited for advanced CPUs, application processors, etc., but from a price/performance perspective, they are generally a poor fit for sensors, connectivity, analog mixed-signal (AMS) applications, etc.

Although you wouldn’t necessarily know it from reading press releases each week, designs at 65 nm and larger still account for approximately 43% of all wafer production and 48% of wafer fab capacity. Even more significant, nodes 65nm and larger account for approximately 85% of all design starts (Figure 1). Clearly, established nodes are not fading away any time soon.

Figure 1. Production data shows established nodes still comprise a significant portion of the IC market. (source: VLSI Research)

Today’s Established Nodes Have Evolved to Meet Market Requirements

Designs at these established nodes are certainly not static. Today’s established node designs are vastly different from the original designs developed when these nodes were new (Figure 2).

Figure 2. Design complexity at established nodes is increasing, measured here at 65 nm by the number and type of IP blocks in typical designs (Source: Semico Inc.).

Historically, when a node was brought on line, it was optimized for Bulk CMOS digital logic. That is, the process design rules, supported device types, voltages, etc., were all tuned for this application. Today, established process lines such as 65nm are being “retooled” for an assortment of product types (Figure 3). It’s common to see mixed-signal IC designs (e.g., Wi-Fi, Bluetooth, etc.) using process and design rules that never envisioned such products. They require more power, meaning more rails, domains and islands. They contain more analog and mixed-signal components, as well as high-speed interface solutions like silicon photonics. They require a variety of advanced design rule checks (DRC), and “smart” filling routines designed to maximize the use of fill. They often include large intellectual property (IP) blocks, either developed internally or purchased from third-party suppliers. They often have far more reliability constraints, due to new market requirements and standards. And lastly, they are more and more frequently incorporated into a 3D or 2.5D package. All of those changes impact the physical verification strategy and techniques for these designs.

Figure 3. Consumer electronics is one market that powers the relentless drive toward more functionality and sophistication.

Why is this important to you? As a reader of this periodical, you probably work within the IC ecosystem, developing these types of products using an “advanced” mature node. Of course, time to market for a new Wi-Fi or Bluetooth chip built on an advanced mature node is just as important as a 16/14 nm application processor for a next-generation smart phone. And because the design you are building is far more complex than the first designs built on the target process, it may be that your team is struggling, because the EDA tools you used when that process was introduced 5 or 10 years ago cannot handle the new requirements and complexity. Fortunately, electronic design automation (EDA) tools built for later nodes with additional capabilities can be easily redeployed for advanced mature nodes to improve design team productivity and the quality of your designs.

Some of the capabilities commonly employed at advanced mature nodes include:

- Circuit reliability

  • Reliability checking to identify design flaws associated with electrostatic discharge protection, electrical overstress, electromigration and others in single- or multi-voltage-domain designs
  • Ability to handle voltage-dependent design rules, that is, spacing rules that depend on the voltage potential between devices and wires
  • Ability to check for accurate device symmetry in sensitive analog circuits and other reliability-related analog/mixed-signal issues
  • Ability to check for reliability conditions that are unique to a particular design methodology

- Pattern matching functionality to identify specific shapes and configurations.

  • Ability to define and locate patterns of interest that can affect performance or detract from yield
  • Specialty device checking
  • Multi-layer structure definition
  • SRAM cell, cell interactions, and interface checking
  • Ability to detect IP manipulation

- Automated DRC waiver management

  • Elimination of time spent debugging waived errors
  • Ensure ISO standard compliance for consistent behavior and traceability

- Equation-based design rules, which allow designers to define rules as complex mathematical functions, greatly simplifying rule definition while increasing accuracy.

  • Precise tolerance determination on multi-dimensions (such as multi-faceted polygons)
  • Accurate antenna checking and property transfer

- Automated fill process that satisfies complex fill requirements

  • Maximization of fill shapes to minimize density variation
  • Critical-net-aware fill
  • Analog-structure-aware fill (symmetry requirements)
  • Alternating and symmetrical fill for diffusion and poly
  • Matched fill for sensitive devices, cells, nets

Naturally, EDA vendors are stepping up to the challenge, and working to ensure these capabilities are available to design companies working at established nodes. At Mentor, we see extensive use of the tools in our integrated Calibre® nmPlatform being used for verification across the circuit and physical layout domains. Designers and foundries see that leading-edge tools such as the Calibre PERC™ reliability solution, the Calibre eqDRC™ functionality of Calibre nmDRC™, the Calibre Pattern Matching tool, SmartFill™ functionality in Calibre YieldEnhancer™, and others can provide as much value to the established nodes as they have for the newest processes.


The latest IC design and verification challenges are not all at the latest and greatest process node. Competition and market demand continue to challenge designers working at established nodes as well. In addition, industry economics and specialized applications are creating a growing volume demand for designs based on established nodes. While the market potential of established nodes is growing, so is the complexity and difficulty of validating designs that push these nodes far beyond their original capabilities. The new reality is challenging designers using EDA tools that were not available when the nodes were brand new. We’re learning that EDA tools are not frozen to the node, but must advance at these advanced established nodes just as they do at the leading-edge nodes. Design teams working at advanced established nodes have the option to upgrade their tools and make their life much easier. They might even feel like dancing…

Further Reading: Is Complexity Increasing For Designs Done at Older Process Geometries?

Michael White is the Director of Product Marketing for Calibre Physical Verification products at Mentor Graphics in Wilsonville, OR. Prior to Mentor Graphics, he held various product marketing, strategic marketing, and program management roles for Applied Materials, Etec Systems, and the Lockheed Skunk Works. Michael received a BS in System Engineering from Harvey Mudd College, and an MS in Engineering Management from the University of Southern California.

Leveraging Reliability-Focused Foundry Rule Decks

July 27th, 2016

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

Not that long ago, all designers had for integrated circuit (IC) reliability verification was a plethora of home-brewed scripts and utilities they combined with traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC) tools. There were no foundry reliability rule decks or qualified reliability verification tools to provide a central focus on, or automated process for implementing reliability checks. While SPICE simulation is still widely used for small blocks, the ease with which reliability issues can be overlooked at the circuit level (particularly for electrical overstress) is staggering. Missing an input vector or running too few simulation cycles to expose an issue are some typical concerns (and weaknesses) of the SPICE methodology. On the interconnect side, traditional reliability verification means using your favorite parasitic extraction tool, selecting the paths you know/care about for export, and running SPICE on your parasitic netlist to determine resistance. Quite the laborious and error-prone undertaking. Understanding the circuit structure (topology), interconnect, and physical layout of your design are critical when looking at reliability-focused issues, especially those involving electrostatic discharge (ESD) and latch-up (LUP). Despite the challenges of these approaches, the question from designers always seemed to be “How can I leverage this technology if I don’t write the rules myself?”

Reliability-Focused Foundry Rule Decks

The fabless ecosystem relies on the availability of comprehensive, well-qualified foundry rule decks for a broad range of process nodes. Over the last decade, collaboration between electronic design automation (EDA) companies and the world’s leading foundries have resulted in the creation and availability of reliability-focused IC verification rule decks that consider design intent. While DRC, LVS and design for manufacturing (DFM) have been well-ingrained deliverables for this ecosystem for years, these new decks have enabled the development of qualified automated reliability verification solutions, like the Calibre® PERC™ reliability verification platform from Mentor Graphics [1], to help designers specifically address more complex reliability design issues accurately and efficiently.

Because new node development allows for the introduction of new tools and design flows, and creates the opportunity to solve new problems, many recent press releases focus on emerging node technologies [2][3][4][5][6]. However, while established nodes like 28 nm and 40 nm may not get much press these days, reliability rules are also available for them, focusing primarily on ESD and LUP.

Many designers are now beginning to understand the value of using these foundry reliability rule decks and automated reliability verification to augment their internal reliability checking flows for a wide variety of complex reliability issues.

Early and often

As with other verification solutions, getting insight into problematic areas of the design that affect reliability earlier in the design process is extremely beneficial, reducing the extensive re-work and re-spins that destroy schedules and eat into profits when errors are discovered late in the flow. For example, ensuring that the interconnect at the intellectual property (IP) level of your design is robust is a check that can be run early in the design process, as can cross-domain and similar topology-based checks. Many rule decks have options to facilitate running reliability checks not only at the full-chip level, but also at the IP level. Utilizing these capabilities in an incremental approach helps provide context for problematic areas, particularly for IPs that are being used in a different context from previous implementations, or whose geometries have been shrunk to accommodate a new process node.

I often hear the statement that early reliability analysis cannot be done because the chip is not “LVS-clean.” False! While making sure you have no power or ground shorts when doing ESD or other power-related checks is critical, there are a whole slew of LVS errors that have no impact on ESD protection structures and evaluation. By understanding your design, and identifying the LVS errors that can impact the reliability verification results, you can achieve significant design closure benefits from employing early reliability verification. Of course, final sign-off verification can’t happen until your design is both DRC- and LVS-clean, ensuring accurate results, but the adoption of an “early and often” policy towards reliability verification will help you influence critical aspects of the design implementation while there are fewer barriers and lower cost to changes. Such checks as point-to-point (P2P) resistance, or current density (CD) issues due to inadequate metallization and/or insufficient vias, can be readily identified and rectified in the layout, as can topology issues for important protective structures like ESD or cross-domain circuits. Leveraging the foundry’s reliability checks with an automated reliability verification tool early in the design/verification cycle establishes an important baseline to identify potential issues without incurring significant costs in time and resources.


Foundry rule decks and qualified EDA tools have permitted the fabless ecosystem to flourish. Together, their trusted and well-qualified content and processes provide the foundation for your verification flows. With the proliferation of reliability-focused foundry rule decks, early verification of reliability issues and comprehensive full-chip runs can now leverage their guidance. As with more traditional DRC, LVS and DFM rule decks, augmenting your processes and flows with these foundry offerings and qualified tools provides you with the flexibility to implement reliability verification early in your design process, while ensuring confidence in the results.

Related resource: Improving Design Reliability by Avoiding Electrical Overstress


[1] Fabless/Foundry Ecosystem Solutions,

[2] Mentor Graphics Enhances Support for TSMC 7nm Design Starts and 10nm Production

[3] Mentor Graphics Announces Collaboration with GLOBALFOUNDRIES on Reference Flow and Process Design Kit for 22FDX Platform,

[4] Intel Custom Foundry Expands Offering with Reliability Checking Using Calibre PERC,

[5] UMC Adds Calibre Reliability Verification and Interactive Custom Design Verification to Design Enablement Offering,

[6] SMIC Adds Reliability Checks to IP Certification Program Based on Mentor Graphics Calibre PERC Platform,

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at

Reliability Scoring for the Automotive Market

June 23rd, 2016

By Jeff Wilson, DFM Product Marketing Manager, Calibre, Mentor Graphics


The annual growth for car sales is typically in the single digits, but the electronic content inside those cars is rapidly expanding as we enter the age of the digital car. Current estimates posit up to 30% of the production cost of a new vehicle come from the electronic systems. The typical new automobile now contains over 100 microprocessors, performing various tasks from safety (braking control and sensors) to comfort (heating, cooling, seat positions) to infotainment (navigation and communication systems), as well as one of the fastest-growing uses—advanced driver assistance systems (ADAS). This explosion of automotive electronics is one of the bright spots in the current semiconductor industry, making these devices an attractive market for semiconductor companies looking to expand their markets. The challenge for any company new to the automotive market is to understand the market requirements and performance standards, especially in the area of quality and reliability. Safety, efficiency, and connectivity are the primary drivers for automotive electronic components.

Expanding Automotive Market

As more companies expand into this market, a key element to their success is ensuring that designs properly account for the environmental variability associated with automotive use, the stringent quality and reliability requirements with which they must comply, and consumer expectations for performance and reliability. Design teams must understand these conditions and apply the appropriate technology to solve design issues and achieve compliance.

There are a number of factors driving the need for reliability. First, there is the physical environment in which these devices must operate, which includes extreme weather conditions and broad ranges of temperatures. In addition to the climate, other environmental conditions that these devices must endure include ambient heat, vibration, and both extended and start-stop operation. Designing to meet this extended set of requirements is typically a new experience to those who have recently made the decision to produce chips for the automotive market.

Another reliability requirement that is new to most designers is the expected lifespan for their designs.  While consumer products typically operate for a few years, an automotive device is expected to last at least 10-15 years. In addition, an automobile creates its own system, with a significant amount of connectivity between devices that compounds the criticality of device reliability because, in many cases, if one device fails, the entire system is compromised. This forces designers to consider previously trivial design stresses, such as time-dependent dielectric breakdown (TDDB), and learn how to analyze and account for these effects. This expected life also puts a strain on new technologies that don’t yet have a longevity track record.

In addition to environmental variability and cumulative system reliability, there is variability in the breadth of the complexity between designs. At the high end, there is the in-vehicle infotainment (IVI) market, which is simply defined as combining information and entertainment for the benefit of both the driver and the passenger. IVI brings together video display, audio, touchscreens, and connections to other devices such as smartphones and media players. The controlling systems or host processor in IVI typically utilize the latest semiconductor technology to deliver the required functionality.  Memory chips, especially NAND flash, are another important semiconductor component in navigation and IVI systems.

At the low end, established technologies are known and proven for such items as safety (e.g., air bags), braking systems, power train operations, and ignition system control. The need for these chips is a major driver (along with the Internet of Things) of capacity at established nodes. This market demand puts pressure on designers to ensure they consistently maximize both yield and reliability even in these long-established designs.

Reliability Drivers

There are two major areas of reliability that must be considered during the design and verification process—electrical performance and manufacturing optimization. These two reliability-related issues have both unique requirements and overlaps. One of the biggest overlaps is the eco-system required to deliver a complete design solution, which includes the foundry, design team, and electronic design automation (EDA) solution providers. The foundry has in-depth knowledge about the manufacturing process, and can link a layout configuration to yield/reliability/robustness by putting this knowledge into a rule deck.  The EDA providers supply automated functionality that allows designers to analyze their design against this rule deck to find out what and where changes can improve their design, either for electrical performance or manufacturing optimization. Now that designers have an automated solution that helps improve design reliability, they can put it to good use on their designs. In addition to improving the yield/reliability/robustness score for each design, they can use this capability to establish best practices across the company. By comparing scores from different design groups, they can determine what design techniques to use going forward. Standardizing on the best flows for their company helps improve the quality of all designs.

Designers have the responsibility of ensuring that their designs are reliable by verifying electrical performance before tapeout.  The AEC electrical component qualification requirements identify wearout reliability tests, which specify the testing of several failure mechanisms:

  • Electromigration
  • Time-dependent dielectric breakdown (or gate oxide integrity test) — for all MOS technologies
  • Hot carrier injection — for all MOS technologies below 1 micron
  • Negative bias temperature instability
  • Stress migration

Design verification against these failure factors ensures that the actual device electrical performance will meet reliability expectations. However, traditional IC verification flows leveraging design rule checking, layout vs. schematic, and electrical rule checking techniques may have trouble validating these requirements, because these tools each focus on one specific aspect of design verification. New EDA tools like Mentor’s Calibre® PERC™, which provides the ability to consider not only the devices in a design, but also the context in which they are used, as well as their physical implementation, can help designers understand weaknesses in their designs from a holistic approach. This “whole problem” view of a design provides visibility to interoperability issues of intellectual property (IP) used in the design.

Manufacturing reliability is driven by what is commonly referred to as design for manufacturing (DFM).  DFM is about taking manufacturing data and presenting it to designers so they can improve the yield/reliability/robustness of their designs by eliminating known manufacturing issues. The most effective way to make this work is to have the same type of eco-system used to improve electrical reliability, where the participants include the foundry, designers and EDA providers.  Manufacturing reliability checks are an extension of the rule deck, such as the manufacturing analysis and scoring (MAS) deck developed by Samsung and GLOBALFOUNDRIES for use with Mentor’s Calibre YieldAnalyzer™ tool.  A key element in creating a functional eco-system is to provide the feedback from actual manufacturing results, so the designers understand why a particular layout structure is not suitable for complying with reliability requirements. This feedback is especially critical for those that are new to the automotive market and its additional reliability requirements. A productive solution is much more than just providing a DFM score for a layout—designers need to recognize the most important and relevant geometries, and what changes will return the greatest improvements in reliability. The ability to prioritize design work is critical to producing designs that are both cost-efficient and successful.


There is no doubt that electronics are impacting the automotive market, and this trend is expected to continue increasing.  As companies move into the market to take advantage of the opportunities they see, they will need to understand how layout variabilities relate to design quality and reliability requirements. Foundries can provide the relationship between the layout and the reliability, while EDA providers supply the tools that present this data to designers in an easy-to-use automated system. As the final piece of the eco-system, designers must understand both the requirements and the solutions  to ensure the design meets the stringent electronic reliability requirements while remaining profitable to manufacture.

Additional Resources

Understanding Automotive Reliability and ISO 26262 for Safety-Critical Systems

Migrating Consumer Electronics to the Automotive Market with Calibre PERC

Enhancing Automotive Electronics Reliability Checking


Jeff Wilson is a DFM Product Marketing Manager in the Calibre organization at Mentor Graphics in Wilsonville, OR. He has responsibility for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Jeff previously worked at Motorola and SCS. He holds a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon. Jeff may be reached at

Interconnect Robustness Depends on Scaling for Reliability Analysis

May 25th, 2016

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

The safety net of design margins that were once available to designers has disappeared. Whether you’re implementing a new design start at your “next” node or an established node, the desire for greater functionality has eroded what margins used to exist. This tightening of design margins is further exacerbated by an increasing industry-wide focus on reliability, driven by both consumer demand and an expanding array of standards for performance-critical electronics. This focus seems to be landing equally on both devices and interconnect. Gone are the days when (rough) hand calculations or visual inspection of designs were sufficient to provide the level of confidence needed to proceed against time-sensitive tapeout schedules and tight time-to-market windows.

Now present in both digital and analog designs is the need to validate interconnect robustness, or resistance to failure. The old technique of “counting squares,” where each “square” of a specific size was given a resistance value for each metal layer, and other manual methods seldom provide the necessary accuracy.

For a design to be “LVS clean,” all that’s required is a single connection. Not a great way forward if you are expecting to shunt any reasonable current through those connections. The same is true for blocks connecting to wide power busses, with slender metallization. Figure 1 shows several examples of LVS-clean layouts with very low robustness, and how they could be improved.

Figure 1. Inadequate via and interconnect connections within layers.

Parallel paths and unexpected layer transitions make point-to-point resistance (P2P) simulations an invaluable tool for validating that low resistance paths between design elements exist. Current density (CD) simulations provide more detail, and not only allow designers to consider the suitability of the metal width, but also provide an opportunity for detailed analysis of layer transitions.

Early interconnect evaluation

Validation of individual intellectual property (IP) blocks before final integration into the system-on-chip (SoC) provides an early look at possible robustness issues. Far too often, design teams feel the need to wait until final chip assembly to validate full path interconnects. While this is an important task that must be completed, validating each of the IP blocks early in the design process, when changes can more easily be made, provides important feedback on what to expect in the final design. In addition to focusing on each IP block, designers must also consider functional assemblies, even before they actually exist. Where will the electrostatic discharge (ESD) protection blocks be integrated? How will the lower levels of IP be validated for interoperability? These are all important design flow considerations.

At smaller process nodes, particularly those using FinFETs, ESD circuits require a larger number of (often interdigitated) devices to provide adequate protection. The ESD target levels that you design to can greatly impact the area and number of these devices. Verification of these structures, particularly the interconnect to clusters of these devices, is of critical importance. Validation at the lowest design level possible, as early in the design process as possible, enables efficient design flows for each technology node. Depending on the design style and its robustness/reliability requirements, it may be necessary to critically look at detailed combinations of input/output (IO) pads to power clamp devices. This type of analysis may require a significant number of individual simulations to capture all combinations of IO1 through each of the power clamps (Figure 2).

Figure 2. Multiple simulations are needed to capture all combinations of IO1 through each of the 3 power clamps.

Full chip evaluation

In addition to this focused analysis at the IP level, understanding the context of IP use in the full-chip SoC is also an important consideration. As with validating the IP-level interconnect, full-chip evaluation requires a strategy that matches your workflow. Do you only need to validate interconnect to the ports of your IP, or must you go all the way to the device level?

As is standard in LVS full-chip runs, designers performing interconnect robustness analysis may exercise their verification tools for P2P and CD simulations at the device level. Leaving nothing to chance, this evaluation looks at the entire full-chip path, often looking at different combinations of ESD protection paths. If you use a comprehensive verification toolset, the good news for all these simulation paths is that you can parasitically extract all of the pin-pairs that need to be evaluated at the same time. The combinations that must be simulated can re-use these parasitics to perform the next simulation (Figure 3). This re-use is critical for minimizing turnaround time (TAT) while scaling to the number of simulations required for detailed analysis.

Figure 3. Scaled simulations are essential to minimizing TAT while ensuring accurate and complete analysis.


The need to validate interconnect robustness is now a given at advanced nodes. However, accepting simulation runtimes that take days, or even weeks should be a thing of the past. With interconnect robustness a critical aspect of reliability, fast simulation and parasitic extraction is essential for both schedule and market success. Early analysis within the design flow helps alleviate last-minute discovery of critical errors, providing the opportunity for fixing without significant adverse impacts to product schedules. Detailed analysis of interconnect, particularly for P2P and CD in ESD environments, with a reliability verification tool capable of quickly performing complex simulations, provides both accuracy and the necessary coverage in an acceptable timeframe. The early discovery of interconnect robustness issues, combined with the ability of your verification tools to easily and efficiently scale from IPs to SoCs, can ensure timely design completion while enhancing design reliability, a combination that can provide a new safety net—for your bottom line.

Collaborative SoC Verification

March 23rd, 2016

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics

With the widespread use of system-on-chip (SoC) designs, efficient integrated circuit (IC) design and validation is now a team sport. In many cases, long gone are the days where a single person was charged with responsibility for the entire design. Extensive intellectual property (IP) use, design re-use, and re-design from both internal and external sources have made successful IC design as much about efficient IP management and integration, as it is about creating new blocks and functionality.

A lot of attention is paid to the top-level integration tasks of final assembly and full-chip verification, but these tasks happen towards the end of your IC design journey. While it is important to validate the correct interconnects and top-level assembly of each of your blocks in the design as a whole (Figure 1), how those blocks get there, bug-free and operationally correct, is an important aspect of meeting your design timelines.

Figure 1 - Multiple IP blocks comprise the top-level design, which must be validated as a whole.

Bottom-up design flows

Designing each IP block in isolation provides a great deal of autonomy, if isolation can actually be achieved. Issues such as interface definitions, as well as compliance to I/O switching and power consumption requirements, all pose challenges throughout the design flow. Validating individual IP blocks as you go, fixing each one as issues are found, provides a methodical and scalable workflow that accepts design growth and the addition of more functional blocks with relative ease. Understanding the context in which your IP will be used is an important aspect of the verification methodology that you employ. Interconnects must be robust, able to handle not only the internal voltage and currents that will be generated, but also to cope with the intended stresses of the final design assembly. On an IP block level that you control, this verification is probably a manageable task to ensure that your block either complies with the requirements and rule checks provided for validation, or that you have waiver documents in place for any outliers.

Top-down verification

Top-down full-chip verification is the most reliable methodology by far, when all the pieces are in place. However, that reliability comes at a cost. Waiting until all of the constituent IP blocks and elements are in place puts you towards the end of the project schedule. Time is short, schedules often slip, and final verification becomes a challenging and stressful period. Pulling in pre-verified IP blocks can limit the introduction of any newly-found violations to the integration process. How these blocks are connected, their implementation in the context of the larger design, and the application of previously created waivers can play a significant role in determining how challenging final verification is. A well thought-out verification flow can help immensely in the closing hours, but it’s not a one-person job when design issues are found, particularly those that span multiple IPs. The challenge is to effectively engage all team members, each with specific knowledge, in a collaborative manner across the whole chip.

Waiver flows need to be collaborative, too

Once “obvious” errors have been eliminated, the subtle job of understanding the interactions and nuances of the system being created falls to those who created it. Many times, a robust framework of IC validation checks can focus attention on those final few issues that will probably need specific IP knowledge to either waive or fix.

Many traditional waiver flows rely on a static model of verification results, and a single user wading through all results, for all IP blocks. While conceptually simple, this model creates a significant bottleneck in today’s large IP-based designs. With a high degree of IP re-use, the IP owner is best suited to validate the context of a flagged issue for that IP. The challenge, however, is to allow multiple IP owners to review, waive, and interact with the results for the entire design at the same time. Their efforts need to be collaborative and additive. Fighting for a “timeshare” on a design and asking others to stop working is not a productive solution. Moving forward, existing automated waiver management technology can and should be employed to support simultaneous waiver analysis and identification for multiple IP.


The ways we design and validate the complex interactions in designs with significant IP content have evolved over time to accommodate the changing requirements of such designs. However, waiver methodologies have lagged behind, creating potential bottlenecks. Validating IP blocks in isolation (including waiver annotation) as they are being designed can help, as can employing automated waiver management at different levels of design integration. Waiver flows that we have become accustomed to using for individual IP must evolve to accommodate multiple IP owners and the specific knowledge they hold for how these blocks are used in the context of larger SoC designs.

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at

System-Level MEMS Design: An Evolutionary Path to Standardization

February 16th, 2016

By: Qi Jing, Technical Marketing Engineer, Mentor Graphics Corporation


Successful design of highly-integrated IoT systems (Figure 1) requires simulating MEMS components together with the peripheral circuitry. However, MEMS devices are traditionally designed using CAD tools that are completely different from IC design tools. In the past two decades, both academia and industry have been seeking new methodologies and have chosen to implement multi-disciplinary MEMS design within the IC design environment. Performing MEMS-IC co-simulation in IC design environment allows designers to take advantage of advanced analog circuit solvers and the system verification capabilities that IC tools offer.

Figure 1: Typical IoT design.

A good system-level design methodology should facilitate MEMS device models and structure representations that are compatible with the IC design flow, and provide simulation accuracy and speed that are comparable or superior to typical analysis tools in the appropriate physical domains. It should also provide broad coverage of physical effects, and be able to support large systems. The three methodologies in use today for system-level MEMS modeling and simulation are:

  • Lumped-element modeling with equivalent circuits
  • Hierarchical abstraction of MEMS and analytical behavioral modeling
  • MEMS behavioral modeling based on Finite Element Analysis (FEA) and Boundary Element Analysis (BEA)

Lumped-Element Modeling with Equivalent Circuits

To implement SPICE-compatible modeling and simulation for MEMS, the most straightforward method is to create equivalent circuits for MEMS based on lumped-element modeling. For example, Figure 2(a) shows a spring-mass-damper system.  A formal analogy can be derived between the mechanical and electrical elements, leading to an equivalent circuit “in series” topology as Figure 2(b) shows. Similarly, an “in parallel” circuit analogy can be derived as Figure 2(c) shows.

Figure 2: (a) A spring-mass-damper system (b) Equivalent “in series” circuit topology (c) Equivalent “in parallel” circuit topology.

Although the equivalent-circuit methods appear straightforward, designers must be aware of their viability and limitations. First, analogies shown in Figure 2 are based on the assumption that MEMS structure can be significantly simplified into a spring-mass-damper system and that the effective mass, stiffness, and damping factor can be derived. This is only suitable for simple MEMS devices. For complex devices, the derivation could be too complicated and thus impractical to perform.

Secondly, the equivalent circuits are not easy to extend. Designers have to re-derive new models in order to account for additional physical effects or to adapt to changes in geometry, topology, or boundary conditions of the design.

Therefore, it is not uncommon for designers to determine that equivalent-circuit methods are too difficult or impossible to implement. More advanced methodologies are needed.

Hierarchical Abstraction of MEMS and Analytical Behavioral Modeling

In IC design, complex systems are built up hierarchically using building blocks at different abstraction levels. Hierarchical schematics are created to represent systems as structural networks comprising instances of these building blocks, connected together based on design topologies. Similar ideas have been explored and applied to MEMS design.

Figure 3 provides an example of the hierarchical abstraction of a folded-flexure resonator that contains a MEMS transducer and an electrical interface circuit. The MEMS transducer is an electrostatic device that is hierarchically built using a set of functional-level elements, each of which are further decomposed into atomic-level elements.

Figure 3: Hierarchical abstraction of a folded-flexure resonator.

Behavioral models for MEMS elements can be written in analog hardware description languages such as Verilog-A, Verilog-AMS, and VHDL-AMS. Resulting models are compatible with SPICE simulators, thus serve well for co-simulation purposes. Analytical behavioral models for MEMS contain the following:

  • Definition of terminals, with the associated physical disciplines specified.
  • Definition of model parameters, including material and process properties as well as geometric sizing and layout orientation parameters.
  • Description of model behavior using a series of Differential Algebraic Equations (DAEs) that govern the relationship between, across and through variables of the terminals, with coefficients formed by parameters and internal variables.

It’s crucial to obtain precise values of the material and process parameters in order for the models to match silicon. For standardized MEMS designs, foundries have started to develop and offer MEMS PDKs. For novel MEMS designs, designers have to fabricate test structures first then extract the parameters from lab measurement results.

After models are ready, they form model libraries that can be used for many designs in the appropriate design space. For example, atomic-level elements shown in Figure 3 not only serve as the foundation for folded-flexure resonators, but also work for many other typical suspended MEMS designs, such as accelerometers, gyroscopes, resonator filters, micro mirrors, and RF switches. Model libraries make it possible for people unfamiliar with MEMS to use the models for system integration, and help protect MEMS IP.

Due to the large variety of MEMS designs in underlying physics, fabrication processes and design styles, no model library can be a universal solution that fits all. If the device employs unique, irregular geometries, or if the device involves physics mechanisms that are not well-understood, a new model has to be developed from scratch.

MEMS Behavioral Modeling Based on FEA/BEA

Because geometry shapes supported by analytical models are discrete and limited, MEMS designers sometimes resort to Finite Element Analysis (FEA) and Boundary Element Analysis (BEA) tools. FEA/BEA tools use conventional numerical analysis methods for simulations in mechanical, electrostatic, magnetic, and thermal domains. They often rely on auto-meshers to partition a continuum structure into a mesh comprised of low-order finite elements. The tools then construct system matrices based on the meshing and solve the matrices within boundary conditions.

Efficient simulation of coupled physical domains is often a challenge to FEA/BEA-based tools. For example, to model the interaction between mechanical and electrostatic domains, some FEA/BEA tools must perform analyses for each domain separately and iteratively until a converged solution is found. Superior tools can simulate coupled domains all-together, but the simulation is computationally expensive and may result in unacceptable run times.

To alleviate limitations of FEA/BEA-based methods, while still utilizing their strength, Reduced Order Modeling (ROM) has been deployed, effectively bridging the gap between traditional FEA/BEA tools and electrical circuit simulators. ROM is a numerical methodology that attempts to reduce the degrees of freedom within system matrices to create macro models for MEMS devices. The resulting models can be constructed in languages like Verilog-A, then exported into SPICE simulators for co-simulation.

Up-to-date ROMs can be built not only from FEA/BEA results, but also from user-defined analytical equations and experimental data. Parameters in the reduced models can be preserved, so that design variations can be evaluated without going through the FEA and model order reduction process again. This enhances the coverage and efficiency of model libraries based on FEA/BEA and ROM.

Like all modeling methodologies, FEA/BEA-based methods cannot fully cover the entire MEMS design space either. Physical effects, as well as design and process imperfections, must be pre-defined in the original FEM/BEM model in order to be captured. In addition, creation of accurate models not only requires solid understanding of the underlying physics of MEMS devices, but also knowledge in both FEA/BEA tools and the model order reduction process.


To meet the need for MEMS-IC co-simulation, multiple modeling and simulation methodologies have been proposed, explored, and developed over the past two decades. Equivalent-circuit methods, structural analytical behavioral modeling, and reduced-order modeling based on FEA/BEA, are all effective methods and each has its own advantages and limitations. Knowing when to use which type of modeling method is important:

  • When the design is small and simple, equivalent-circuit methods are the most straightforward.
  • When the design is decomposable and the geometry, process, and dominant physical effects are close to what was used in the creation of primitive model libraries, hierarchical analytical modeling and structural system composition are the best choice.
  • For unique designs using complex geometries, ROM methods based on FEA/BEA are more flexible and powerful.

For IC design, it took decades of academia and industrial endeavors for models, SPICE simulators, and foundry PDKs to emerge, mature, and converge into well-adopted industry standards. The MEMS modeling and simulation counterparts need to go through the same evolutionary path. This path has even more challenges than IC design, due to the much broader multi-physics coverage of MEMS and the diversity of MEMS manufacturing processes, applications, and design styles. Joint effort from design companies, foundries, and EDA tool vendors is required to enable this evolution. For more information about system-level MEMS modeling and simulation, download the whitepaper “System-Level MEMS Design – Exploring Modeling and Simulation Methodologies”.

Five Steps to Double Patterning Debug Success

January 26th, 2016

By David Abercrombie, Program Manager, Advanced Physical Verification Methodology, Mentor Graphics

Has debugging double patterning (DP) errors got you pulling your hair out, or wishing you had pursued that career in real estate, like your mom suggested? Now you can unlock the secrets of DP debugging in five easy steps! Once you learn these steps, you’ll be the envy of your team, as you deliver clean DP designs on schedule, and still have time to eat lunch each day!

So, what are the five steps of successful DP debugging? Are you alone? Okay, lean in and listen closely…There are five types of errors you typically find in a DP design layer (excluding any errors associated with using stitches), and the order in which you debug them can make the difference between success and an endless insanity loop of debug-fix-check. I hope you’re taking notes, because here are the five steps in which you should debug your DP errors…

1. Debug all minimum opposite mask spacing errors first.

This condition is the most fundamental DP error you will encounter. Minimum opposite mask spacing errors, just like traditional design rule checking (DRC) spacing errors, involve only two polygons and the space between them. However, there is no coloring solution that resolves the error. In addition, violating a minimum spacing constraint can create other misleading DP errors, as shown in Figure 1.

Figure 1: Minimum opposite mask spacing errors can generate unnecessary odd cycle DP errors.

When these two polygons violate the minimum opposite mask spacing constraint, they also create a diagonal tip to tip separator constraint in the layout, which leads to two odd cycle violations between the original two polygons and the two adjacent polygons. Because designers often assume the best way to fix an odd cycle is to adjust any of the spaces involved in the odd cycle, they can end up making two corrections to fix these odd cycle errors, without even correcting the original minimum spacing violation. However, if you fix the minimum spacing violation first, the odd cycles don’t even occur, so you fix both issues at once.

2. Correct all self-conflict same mask spacing errors.

These errors consist of single polygons that have notch spaces between themselves that violate minimum same-mask spacing constraints. This error type is also isolated to a single polygon, but when this polygon interacts with other polygons, other error types can occur. Fixing this error eliminates these secondary errors (Figure 2).

Figure 2: Self-conflict same mask spacing error causing unnecessary odd cycle DP errors.

The red polygon is in conflict with itself. This error is usually flagged by highlighting the polygon. The separator constraints that form in this layout example create an odd cycle error of one. Again, fixing the self-conflict error fixes the odd cycle error as well.

3. Next, resolve all anchor self-conflict errors.

Anchor self-conflict errors are the result of conflicting anchor requests associated with a single polygon. Depending on the automated coloring solution your DP tool selects, an anchor path error may or may not be created. Resolving these errors removes that uncertainty (Figure 3).

Figure 3: Anchor self-conflict errors can potentially cause anchor path errors.

The layout contains a single polygon with two color anchor markers. The separator interactions with other polygons create a path from this polygon down to the bottom polygon. Due to the marker conflict, the DP tool has no guidance, so it randomly decides which color to assign to the polygon. If the tool selects the green anchor, no anchor path error is created, but if the tool chooses the blue anchor, an anchor path error to the green anchored polygon at the bottom is created. However, if you eliminate all anchor self-conflict errors first, any anchor path errors you encounter will be deterministic, rather than random and unpredictable.

4. Fix all odd cycle errors.

Because odd cycle errors can lead to an anchor path error (Figure 4), fix all odd cycle errors next.

Figure 4: Odd cycle errors can lead to anchor path errors.

Due to the separator interactions with other polygons, the odd cycle interacts with two anchored polygons at the top and bottom, creating an anchor path error. By adjusting any one of the spacings in the odd cycle, both the odd cycle error and the anchor path error are fixed.

5. Finally, fix the anchor path errors.

Why save these for last? If you try to fix the anchor path error in Figure 4 before looking at the odd cycle error, you might decide to adjust the space between the top anchor and the middle polygon, or the space between the bottom anchor and the middle polygon. Both of those corrections fix the anchor path error, but leave the odd cycle error in place. Correcting all of your odd cycle errors first can save you a lot of debugging time by making some of those anchor path errors simply vanish.

Following these five steps won’t magically make all your double patterning errors disappear. But they will help you avoid making unnecessary design changes, as well as reduce your overall debugging cycle time. Double patterning design is challenging enough; don’t allow error complexity to make it any harder. Try following these five debugging steps on your next layout, and I think you’ll be pleasantly surprised.

For more information about double patterning debugging, watch “Why IC Designers Need New Double Patterning Debug Capabilities at 20nm” with Jean-Marie Brunet of Mentor Graphics.

David Abercrombie is the Program Manager for Advanced Physical Verification Methodology at Mentor Graphics. Since coming to Mentor, he has driven the roadmap for developing new and enhanced EDA tools to solve the growing challenges in advanced physical verification and design for manufacturing (DFM). Most recently, he has directed the development of solutions for multi-patterning decomposition and checking. Prior to joining Mentor, David managed yield enhancement programs in semiconductor manufacturing at LSI Logic, Motorola, Harris, and General Electric. He is extensively published in papers and patents on semiconductor processing, yield enhancement, and physical verification. David received his BSEE from Clemson University, and his MSEE from North Carolina State University. He may be reached at

Electromigration and IC Reliability Risk

December 10th, 2015

By Dina Medhat, Mentor Graphics

Electromigration (EM) is the transport of material caused by the gradual movement of the ions in a conductor, due to the momentum transfer between conducting electrons and diffusing metal atoms (Figure 1). The EM effect is important in applications where high direct current densities are used, such as in microelectronics and related structures. As the structure size in electronics such as integrated circuits (ICs) decreases, the practical significance of the EM effect increases, decreasing the reliability of those ICs.

Figure 1: EM is caused by the momentum transfer from electrons moving in a wire. (source: Wikipedia)

EM can cause the eventual loss of connections, or failure of an entire circuit. Since reliability is critically important for applications such as space travel, military systems, anti-lock braking systems, and medical equipment and implanted devices, and is a significant consumer demand in personal systems such as home computers, entertainment systems, mobile phones, and the like, the reliability of ICs is a major focus of research efforts in the semiconductor industry.

Reliability risk goes beyond that of physical device reliability (a challenge unto itself), extending to interconnects and their susceptibility to EM effects. Failure analysis techniques can identify failure types, locations, and conditions, based on empirical data, and use that data to re­fine IC design rules.

Let’s look at one approach using the Calibre® PERC™ reliability solution. The Calibre PERC tool can perform topology identification for pins/nets of interest, run parasitic extraction and static simulation, compare the results against EM constraints, then present violations for debugging using the Calibre RVE™ results viewing environment (Figure 2).

Figure 2: Automated EM analysis flow.

With basic EM analysis explained, let’s discuss in greater detail some selected EM analysis techniques, such as current density analysis, Blech Effect analysis, and hydrostatic stress analysis. Current density analysis seeks to identify the maximum current any piece of metallization can sustain before failing. Current densities below this threshold can be used to predict EM effects over time. Blech Length is a process- and layer-defi­ned wire length at which EM effects are unlikely to occur. By fi­nding these short wires, designers can quickly eliminate error results representing false violations. Hydrostatic stress analysis derives the degradation of the electrical resistance of interconnect segments from the solution of a kinetics equation describing the time evolution of stress in the interconnect segment.

A toolset that can combine geometrical and electrical data, like the Calibre PERC™ logic-driven-layout framework, can dynamically and programmatically target reliability checks to specifi­c design features and elements. This flexibility allows designers to selectively target and dynamically con­figure EM analysis to those specifi­c interconnect wires that are most critical, or most susceptible to EM failure. This design-context-aware interconnect reliability technology provides a scalable, full-chip EM analysis and veri­fication solution that considers interconnect resistance, the Blech Effect, and nodal hydrostatic stress analysis for failure prediction. It also allows designers to apply EM analysis techniques to a broad range of designs and process technologies, with only minor adjustments to the setup and con­figuration.

Although fi­xed constraints work well in most IC verification cases, EM analysis and verifi­cation requires a much more flexible constraint mechanism. In current density analysis, allowing current density constraints to be a function of properties of the parasitic resistor (such as the length and width of the resistor) enables layouts to contain resistors with a smaller length and width and a higher current density. The dynamic constraint infrastructure allows adjustments to the current density constraint based on the parasitic resistor properties.

In Blech Effect analysis, the Calibre PERC solution provides access to the measured EM length for any interconnect tree. If the longest path of the interconnect tree is less than the Blech Length, the tool returns a current density constraint of some very large value, which acts as a constraint waiver for this resistor with a segment on an immortal interconnect tree.

Hydrostatic stress analysis must be performed on each interconnect tree. For each node, the Calibre PERC tool compares σi to σcrit. For any interconnect tree where σi ≥ σcrit , the interconnect tree and its individual nodes can then be highlighted in a layout viewer, as well as possible EM failure locations. The determination of σcrit is a function of process technology and segment geometry, and ideally should be provided by the foundry.

Once the EM analysis is complete, an importantaspect of ensuring reliability is debugging any errors or issues. Figure 3 demonstrates the debugging of EM violations by grouping and sorting them, then using colormaps to see current density violations/severity on the layout.

Figure 3: Debugging EM violations

Combining hydrostatic stress analysis with Blech Effect and current density analysis provides a well-rounded platform for the prediction of EM failure, allowing designers to filter out trees that are considered immortal. With the knowledge gained from such analyses, design rules can be modified to eliminate or minimize EM conditions in future designs. Using a reliability analysis tool like the Calibre PERC solution, designers can be more confident that their layouts are resistant to the long-term effects of EM, and will perform as designed for the intended lifetime of the product.

Dina Medhat is a technical lead for Calibre Design Solutions at Mentor Graphics. She has been with Mentor Graphics for ten years in various product and technical marketing roles. She holds a BS and an MS from Ain Shames University in Cairo, Egypt. She can be reached at

Next Page »