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Archive for July, 2013

Still a Tale of Two Paths: Highlights of Lithography Panel from SEMICON West 2013

Tuesday, July 23rd, 2013

 

This year, I moderated the industry’s Lithography Panel during SEMICON West 2013 to a standing room only crowd. This interest in Litho was not a surprise as Litho is the key enabler of Moore’s Law.

Currently, both 193 immersion multiple patterning (193i MP) and EUV Lithography (EUVL) are the leading contenders for next generation lithography for the 10 nm node and below. The SEMICON West 2013 panel was great as we had speakers on both 193i MP (Nikon and Synopsys) as well as EUVL (SEMATECH and ASML). TEL talked about directed self assembly (DSA) applicable to both approaches. Nowadays all large workshops and symposia have separate tracks that focus on one or the other, so it was good to have both of them together. The title of the lithography panel was “Still a Tale of Two Paths” and both sides essentially talked about the merits of their own approach and issues with the other’s approach. (ASML makes both EUVL and 193i scanners while Nikon makes only 193i scanners. Synopsys supports both approaches via their modeling software and TEL makes tracks for both types of scanners.)

The lithography session underscored the issues that we are having in the search for next generation lithography (NGL) technology. There were “two elephants” in the room that all speakers tried to ignore: 1) the cost, complexity and possible technical impossibility of 193i MP below 10 nm, and 2) delays for EUVL due to lack of source power.  The “elephants” were not discussed but their presences were very much felt. 193i MP is getting very expensive and complicated and may not be able to support patterning below the 10 nm node without additional complexity that chipmakers are not willing to adopt. EUV lithography right now still remains in the pilot line due to lack of adequate power. Hence, if scaling required by Moore’s Law is no longer supported soon, there will be an historic cost increase. Before I give my opinion on what I think may happen, let me first summarize what I heard from speakers and otherwise at SEMICON West 2013.

Talk Summary

Nikon titled its first talk “EUV Revolution Has Been Postponed” and then described how to move forward with 193i MP. It is the most probable route if EUVL is absent in HVM to provide resolution scaling, control of CD uniformity and overlay, and flexibility with design and cost. However, it is known that flexibility is reduced in MP with design restrictions and I pointed out during Q & A that Nikon’s comparison of MP with EUVL was not correct. The cost for 193i MP must include all equipment needed to support this technique. A scanner in MP is not just a scanner but a “large composite tool” that contains tools for deposition, etch, ash and metrology, and cost of all these must be included. However, in the absence of EUVL in HVM, 193i MP remains the main choice for chip makers.

In the next talk, Stefan Wurm of SEMATECH pointed out the readiness of EUV resists for EUVL introduction. EUV resists have been ready in part due to the testing infrastructure provided by SEMATECH and other consortia. His consortium is now focused on getting EUV mask blanks ready for HVM introduction of EUVL. The next set of challenges is to reduce pits, bumps and scratches in the substrate, focus on mask lifetime issues during cleaning and handling and reduce damage of backside coatings. In response to a question, Stefan pointed out that an EUVL mask should be able to go through 100 clean cycles, compared to today’s performance of 30 to 40 cleans.

Skip Miller of ASML presented data on the progress of EUVL scanners. He reported the shipment of two NXE3300B scanners to customers. He pointed out 30-70 percent lower cycle time via EUVL scanners compared to 193i based scanners and a large process window for 14nm node and below. He also pointed out that at 10nm node EUVL allows 50 percent scaling, while only 25 percent is possible with 193i MP. Even for grided SRAM chip makers will prefer EUVL, as limited overlay makes MP very difficult. For NXE3300B, throughput targets are 50-125 WPH, based on indications that his power vs. throughput curve will correspond to 68 – 250 W of source power. Currently 40-50 W of sources have been run with good dose repeatability of <0.5 percent for total run time of 20 hours, consisting of many hourly runs. I am not sure if runs were at 100% duty cycle. The target for these scanners in 2014 is for 70 WPH, and he expects 250 W source power to be achieved in 2015.  

Mike Rieger of Synopsys described the role of electronic design automation (EDA) in enabling scaling via 193i MP. Scaling is possible without EUVL but will entail increasing cost, process complexity and design rules restriction. He pointed out need to keep cost under control for these options.

Ben Rathsack of TEL presented collaborations in the area of directed self-assembling (DSA), an emerging technology area that can help 193i MP as well as EUVL. He described his collaboration efforts in the area of defect reduction metrology via continued research with universities and consortia as well as chip makers.

The EUV revolution has not been postponed – it is delayed. The advantages of EUVL due to relaxed k1 and cost competitiveness are well known to chipmakers and what they want are tools that can support HVM, and those are delayed due to low source power.

Industry’s Position and Critical Questions

“Lithography is one of the highest priorities of our industry” and “EUVL must happen” were some of the comments we heard from consortia leaders at SEMICON West in other panel discussions in the meeting. These industry consortia have a combined budget of few hundred million per year and most of it is focused on EUVL. They have done a wonderful job of supporting mask and resist research. As they are funded by chipmakers and some government support, one can assume the view of the consortia is the position of chipmakers as well.

“Suppliers will deliver the EUV sources” has long been repeated by all consortia and they reiterated their position in this meeting as well.  Currently consortia support all but EUV source projects, while EUVL continues to slip due to lack of adequate source power. In the end it is the chip makers who pay for the delay and the consortia reflect their strategy, so one wonders why this is so. Perhaps human psychology it is at work here. People do what they are comfortable doing and generally avoid trying new things unless calamity strikes. Mask and resist is something chip makers know how to deal with and have experience in developing these technologies. However, they do not have a team of plasma experts or source experts to guide them. Neither do consortia, so one has to go with what suppliers can provide. It is interesting that we are ready to bet the future of Moore’s Law rather than do something to hedge our risk. Year after year source power roadmaps slip, but no additional action is taken except to wait for new supplier source power roadmaps that we know will slip again.

Some point out to me is that the critical question today for the industry is, “If EUV Sources will be ready, will mask infrastructure be ready?” I agree that this is an important point and will address it below briefly. However, I think the most important question is, “What we will do with ready EUVL masks and EUV resists, if sources delay EUVL sufficiently to push it out further on roadmaps?”

EUVL mask infrastructure challenges (as detailed in the 2013 EUVL Workshop by Intel, Toshiba and GlobalFoundries) are certainly very difficult but do not look like showstoppers. They can be addressed with significant efforts and investment. What is lacking in the mask area is the consensus on key topics such as choice for masks for High NA tools, need for pellicles, how to inspect patterned masks during manufacturing, and need for various mask metrology tools during manufacturing, usage and maintenance of masks. Mask defect metrology tools are still not ready mostly due to lack of high brightness (not high power) EUV sources. In the upcoming 2013 Source Workshop, I expect more discussions and ideas presented on how to advance source technology for metrology sources.

My Predictions

I may be biased toward EUVL, but 193i MP will get more expensive and complex than EUVL at every next node, but EUVL is not yet ready so chip makers have no choice but to go with what is available. ASML announced in their presentation that two NXE3300B tools have been shipped and nine more are on their way to chipmakers. I think 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question.

With 73 WPH, one can start with EUVL in HVM, as that cost is going to be better than for multiple pattering. Below 10nm nodes, the cost for 193i MP is high due to 4x or 8x patterning and for EUVL due to lower throughput due to low source power. I am not as concerned about 450mm transition for EUVL tools. EUV sources will have to deliver 2.5 x source power to keep the same throughput as 300mm tools, and that does not seem to be out of question by 2018, when the competition will be 4x patterning with extreme design rule limitation.

Another question to ask is how far you can scale with 193i MP and what are the cost implications. If EUVL is still not ready in few years and 193i MP is not feasible due to cost and complexity, what do we do? Both are projection lithography and rate of transfer of information from mask to wafer cannot be beaten by direct write techniques? This topic needs continued discussion.

Epilogue

Getting out of SEMICON for my next meeting, I was stopped by a colleague, who reminded me that EUVL was dead. Of course, he has been telling me the same thing since 2006, even while his own NGL approaches have gone bust. It appears that industry has been split into pro- and anti-EUVL camps for some time. It is becoming something like a religious war and there is less of a dialogue between these two camps. EUVL has been proven to be capable but it is delayed and will not be ready for HVM for a few more years. 193i MP is getting to be very complicated and expensive so chip makers have to have a backup, and that is EUVL. In the end it may be a mix of EUVL and 193i MP that will enable continuation of feature size scaling. The industry must continue to follow Moore’s Law and will do whatever it takes to keep up the scaling, so NGL will remain a hot topic for many years to come.

“Taming of Pele – the Fire Goddess”: 2013 EUVL Workshop Highlights

Monday, July 15th, 2013

Keynote talks

The sixth EUVL workshop was held June 11, 14 in Maui, HI with participants from the US, Korea, Taiwan, Japan, Europe and China.

The first keynote talk was delivered by Sam Sivakumar, who is leading the EUVL pilot line for Intel Corporation. He showed the yield data from his EUVL pilot line, obtained since his SPIE Advanced Lithography symposium presentation, that lead him to believe that there appears to be no fundamental roadblock to EUV achieving yield parity with 193i;  any qualifying issues, he said, are not related to EUVL.  In Sivakumar’s opinion, we must make progress on key issues of source power and mask defectivity in the next 1- 1.5 years. Although power delivery is getting better for the ASML’s NXE3100 scanner being used in his fab, source power remains the main impediment to EUVL being placed in HVM.

Tatsuhiko Higashiki (Toshiba) in the second keynote talk emphasized that at nodes 1x nm and below, non EUVL choices are not only unattractive – they are, in fact, scary!  EUVL remains the only alternative, supplemented by double patterning (DP) and directed self-assembly (DSA). He also cautioned that in comparing EUVL to other lithography options, one needs to think about not only cost but also cycle time – something many comparisons do not do include in their cost of ownership calculations, even though increased cycle time is inherent in double patterning techniques and adds significant cost to that technology.

Panel Discussion: EUVL Readiness and Insertion Timeline

Following the keynote talks, panelists gave their opinions on what will be available to support lithography in the near future and related challenges. Sivakumar pointed out that EUV is currently targeted as the primary option for the 7nm node (2015 development, 2017 high volume manufacturing [HVM]) by Intel.

Sushil Padiyar of Applied Materials (AMAT) pointed out for the 12- 8nm nodes, choices are 13.5nm with double patterning (DP), 13.5 nm with hyper NA, or going with 6.x nm.  The 13.5nm with DP option seems to be the best candidate, as its feasibility has been already demonstrated.  The best guesses for 5-7nm are EUV with self aligned DP, and a combination of 193i multi-patterning and EUV. He pointed out the current positional accuracy for DSA is ~ 3nm, so the 193i /EUV combination will most probably need to be teamed with a self aligned (SA) process.

Tatsuhiko Higashiki (Toshiba) said that the semiconductor business will mature if lithography and mask cost reduction is not achieved. He believes that 9 inch masks are preferred by memory makers and EUV and DSA combinations will be the leading choices for lithography in the future.

Pawitter Mangat of GlobalFoundries pointed out the urgent need for EUVL readiness in the next two years. In his opinion, the industry needs to decide soon on masks for high NA scanners due to long lead times for developing this technology.

In a survey distributed to workshop attendees on EUVL readiness and technical challenges, most respondents predicted HVM insertion in the 2015-17 timeframe. Source power, mask defect and pellicle readiness were considered to be the leading challenges.

Workshop highlights

Workshop presentations focused on R&D topics, with the following highlights:

Greg Denbeaux of the University at Albany described his experimental design to study electron chemistry of secondary electrons. This setup will allow direct measurement of electron penetration depth and direct measurement of electron blur. Results will be used to improve resist modeling software to enhance our understanding of the functioning of EUV resists.

Grace Ho of NUK University, Taiwan described “Outgassing, Photoablation and Photoionization of Organic Materials by the Electron-impact and Photon-impact Methods.” The question of equivalence of resist outgas testing via electron beam vs. EUV photons is still not fully answered and in some cases, per her work, one can get different outgassing results for these two methods. As the basic physics of these two processes is different, this is not a surprise. As e-beam testing is frequently conducted to qualify new EUV resists, this topic needs to be continued to be evaluated to ensure the accuracy of assessments.

Cameron Moore of XEI Scientific described damage to various EUV specific materials under plasma cleaning. As dry plasma cleaning shows advantages over wet cleaning of EUV related contamination due to reduced damage to EUV components, we need to understand the effects of plasma cleaning on various vacuum components as well.

Yuriy Platonov of RIT described results of normal incidence collector optics for laser produced plasma (LPP) with average collector reflectivity of 54.3 percent. He also reported that for his Illuminator optics, the central wavelength is within +/-0.8 percent for all five optics sets. For collector refurbishment, he has demonstrated loss of only ~1 percent after two refurbishment cycles. Increased collector reflectivity and stable central wavelength is essential for increasing EUVL scanner throughput. Moving forward, we can see an increased demand for refurbication of normal incidence collectors for Sn Laser produced plasma (LPP) sources, so these were important results.

The meeting included six representatives from China, reflecting that nation’s increasing efforts in EUVL R&D. Prof. Yanqiu Li of Beijing Institute of Technology showed her modeling efforts for 0.3 NA EUVL scanners.

Performance of Cymer sources was presented in the US region review by Greg Denbeaux of U Albany. Sn LPP source now has power of 50 W with 0.5 percent stability for master oscillator power amplifier (MOPA) operation with prepulse. These results were from several continuous one-hour runs, and operation time is expected to rise soon. Denbeaux also presented results from SEMATECH and CXRO, among others, actively involved in EUVL related research. Overall, six EUVL regional overviews were presented from the US, Europe, Taiwan, China, Korea and Japan, demonstrating strong commitment in development of EUVL infrastructure and R&D. However, R&D for the most critical issue of HVM sources is still mostly absent due to lack of funding.

Padraig Dunne of University College Dublin (UCD) pointed out that 6.x nm emission from gallium (Ga), which is a liquid at 30° C, and germanium (Ge) is possible with electron temperature of 50-60 eV. This is significant as 110 eV plasma is needed for gadolinium (Gd), a material currently being considered for light sources for 6.x nm based lithography.  As the temperature of Ge plasma is less than that of Gd plasma, it will take less laser power for Ge based 6.x nm sources. In addition, he suspects that conversion efficiency (CE) may be greater for Ga and Ge plasma than that for Gd.

Akira Sasaki of JAEA pointed out that Sn mist targets, an alternative tin delivery system being currently considered for Sn LPP sources, will require new modeling techniques and shared initial results of his modeling. Modeling work is certainly needed to ensure that maximum benefit for CE increase is obtained with this new method.

Energetiq, ETH Zurich (together with their spin-off company, Adlyte) and NewLambda shared their continued efforts on development of metrology sources for supporting mask defect detection metrology tools. Currently, Energetiq’s sources are used in the first generation of mask defect metrology tools under development.  ETH Zurich has started a new facility (ALPS II) for further development of their metrology sources.

Addressing the topic of Mask infrastructure readiness, Pawitter Mangat of GlobalFoundries pointed out that zero defect printability is not same as zero defectivity on masks. He presented an excellent summary of mask challenges, actions needed to address them and new opportunities of thinner absorber and pellicle development.

Hiroto Kudo of Kansai University described molecular resists based on Noria derivatives (Oligomer derivatives) for EUV resists. A smaller line edge roughness (LER) as compared to current resists is expected in future through use of these polymers.

Yoshi Hishiro, JSR Micro Inc., shared a wide variety of improvements achieved by his company in EUV resists for 16nm node. One example is LER improvement via shorter acid diffusion length and development of EUV topcoat to remove out of band radiation (OOB). As OOB increases LER of printed features from 4.6 to 6.8nm, topcoat was able to bring LER down to 5.0nm.  He showed that firm rinse reduces pattern collapse and decreases LER by 15 percent. In the results on use of DSA, an EUV+DSA approach allowed an increase in sensitivity of resist and improved the CD uniformity (CDU) of patterning, resulting in 14nm line and spaces (L/S) and 18nm contact holes (CH).

Takahiro Kozawa of Osaka University gave an excellent talk on stochastic effects in chemically amplified resists for EUVL. In his study, he determined that  the amount of chemical reaction required at 16nm half-pitch (HP) increases by 74 percent compared to 60nm HP, and the optimum diffusion length for 16nm L/S pattern is ~ 10nm.  Such fundamental work provides insight into the working of EUVL resists will enable development of newer resists to reduce LWR.

Take Watanabe of Hyogo University presented his analysis using synchrotron radiation  (SR) based absorption spectroscopy for the chemical reaction analysis for EUV resist to explain the difference in resist sensitivity of various EUV resists from increase the acid yield.

Sushil Padiyar of AMAT presented results of 9nm CH and 8nm L/S via EUV DP. This work emphasizes the role of DP in the extension of EUVL.

Awards

The workshop attendees voted to award Best Oral Paper to Prof. Takeo Watanabe of Hyogo University for his invited presentation, “Recent Activities of the Actinic Mask Inspection using the EUV Microscope at Center for EUVL.

The audience also posted decisions for the best poster papers, with these awards limited to students this year. First place went to SeongChul Hong of Hanyang University, South Korea for his paper titled, “Attenuated PSM for mitigating PSN effect in EUVL.” He is a graduate student of Prof.  Jinho Ahn.  

Second place poster award was given to Hung-M. Lin of NUK, Taiwan for her paper, “Quantitative Outgassing Study of Photosensitive Films upon Irradiation at 13.5 and 6.7nm.” She is a graduate student of Prof. Grace Ho.

Summary

EUV source power is showing progress but remains the main issue for HVM insertion. Without innovations, progress in this critical area may remain slow. Intel plans pilots in 2015 and 2017 HVM at the 7 nm node. Mask issues still require industry coordination, but the industry can be expected to address them with significant efforts. EUV DP, maybe with help from DSA, seems to be the choice for going below 10nm node and remains preferred by chip makers over 193nm immersion multipattern based approaches. EUV Resist is showing good progress.

Prologue – Taming of Pele – the Fire Goddess

Looking at the history of optical projection lithography, it appears we have learned how to manipulate photons well but not how to generate them effectively from hot plasmas for plasma machines that can operate 24 x 7 at a power level that we need in factories. We do not know if we can support the levels of power that we will need in the near future via our current approach. We need new ideas and we need to think out of the box to improve current technology and identify strong alternative candidates. It comes down to learning more about the taming of hot plasma.

In Maui, site of the EUVL Workshop, there are stories about the taming of Pele – mythical goddess of fire – who with burning lava (the geological version of hot plasma) created the islands of Hawai’i, with controlling force delivered by the surrounding sea. Hawaiian poetry also tells us that the the same force also tamed her:

Huaka’i ihola ‘o Pelehonuamea i ke kai Ko’olau

ma’e’ele ‘o Pele i ke kai kapu o Kamohoali’l

Pele, who gave birth to the reddish earth, flows like the ocean to Ko’olau

But she is benumbed by Kamohoali’I’s sacred seas.

[Hawaiian poetry and translation taken from Na Wahi Kapu o, a beautiful book of photographs of  Maui and poetry by Kapulani Landgraf, Native Books, 2003.]

As we lithographers struggle to transform hot tin plasmas into useful servants that will help us print circuits night and day, let us be guided by the tenacity of the Hawaiian seas, which tamed the seemingly uncontrollable energies of Pele herself!