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Further Thoughts from the 2017 SPIE AL EUV Lithography Conference

March 20th, 2017

By Vivek Bakshi, EUV Litho, Inc.

Stochastics, Lent, Reporting on Conferences, Reality of Things, and a New SEMATECH

In the previous blog, I listed technology status and would now like to discuss a couple of topics in detail. During last year’s SPIE AL conference, the message for EUVL was “Not If, but When.” This year the message was “Not If, but When and How Much Volume.” It was nice to see the technology that I bet on so long ago coming so far and doing so well.

Stochastics and LWR – Why This is not the End of EUVL and Optical Projection Lithography

The stochastics of photons and material were in the focus during the conference. One presenter even called it the cause of the “end of EUV and lithography.” Line width roughness (LWR), or the non-uniform and wiggly shapes of lines that form tiny electrical wires, affects the electrical properties of the circuits that we are working to produce in the end. Although these properties are better for circuits made with EUV compared to multiple patterning, EUV has a serious stochastics challenge as there are 14x fewer photons. I believe that that stochastics will be addressed in some ways and we must remind ourselves that our goal is not “patterns on resists,” which is an intermediate step, but to make “tiny patterns” in the material under the resist. We can beat the apparent limit of physics in how nicely we can transfer the image from mask to resist by finding solutions after the intermediate steps, as I elaborate on below.

First, LWR is not a new story. Back in the nineties, when 193 nm lithography was being developed, I was working in the ATDF fab at SEMATECH developing etch processes. I was told by many that LWR would kill 193 nm litho, as printed lines indeed looked terrible on resist, as well as when those images were transferred to the material below to form lines and contacts. I went to the library (yes, in those days you actually went to the library) trying to figure out the source of this problem, but did not get any clues. In the end by trial and error, I found that a special post-resist patterning etch, initiated before the main etch, could clean up the pattern and drastically reduce LWR. I published a paper on it and did not think much of it at that time. This post-processing of resist patterns, now combined with post-litho rinses, new underlayers, new resist chemistries, litho- dep- etch optimization, flexible pupil illuminations, and innovative mask optical proximity correction (OPC) tricks, are among several knobs available to turn down LWR. Again, remember that resist image is only an intermediate step to what we are trying to do.

At this point, we need to remind ourselves that the Rayleigh criterion of resolution limits how small we can print using a given wavelength. However, we would not be printing what we can today if we had stopped at this resolution criterion. We have been overcoming this limit via OPC and other tricks, and the factor that quantifies our capability to print smaller is called k1. A whole industry emerged around how to take k1 as low as possible. When we approached the diffraction limit of 0.25 for k1 value, it was overcome by multiple patterning and the process continued. Eventually, to continue to print smaller and smaller in the quest toward atomic-level patterning, Litho needs to work together with deposition, etch and metrology. This is already happening, as demonstrated by several papers that showed joint development with etch suppliers.

I propose that the industry develop another factor like k1 (maybe call it s1) to measure how much we can reduce the effect of stochastics, with our goal being low s1 processes.

It is worthwhile to say a few things about Moore’s Law and its projected end by many. I believe that Moore’s Law in its true spirit is not only about physical scaling of the transistors, but also about the scaling of technology to allow ever-increasing information processing. I see transistors as “units of information processing.” We will get to the limits of the current mode of scaling at atomic level patterning with circuit parameters that cannot be gainfully further improved, but that is not an end to scaling of the speed of information processing. In the end, we must switch to different technologies like quantum computing to continue the pace. However, I see no end in the next decade for the current form of scaling. Let us not forget that developing technology for scaling is not cheap, and not without lots of effort.

Lent 

Ash Wednesday usually falls during the SPIE AL conference. Cathedral Basilica of St. Joseph is around the corner from the Fairmont in San Jose, where I usually stay. It has a beautiful interior and is worth a visit. I usually walk the blocks around the church until I get my required steps on Fitbit, and ponder on what I am going to give up this Lent – things that I very much enjoy and have not worked for me. This year, it surprisingly appeared to me that the trade press was also observing Lent and had given up mockery and negative coverage on EUVL, which usually starts on Sunday after Nikon’s Lithovision meeting, even before the start of the actual SPIE AL conference. It was unusually quiet this year on reporting. 

Reporting on Conference News

Toward the end of the week, there were some press reports which contained some inaccuracy. During the conference, one keynote speaker complained to me that he was incorrectly quoted by the media. Another keynote speaker was widely quoted as saying something that was not said in the presentation.

I do not blame the press fully for this, as there is an inherent difficulty in news reporting of technical conferences. Those who are familiar with scriptures know this is a challenge that humanity has faced since ancient times –reporting on complicated things from a distance. The Bhagwat Gita starts with the inquiry of the blind king Dhritrashtra, who asks an expert, Sanjay, to report on what is happening in the far away battlefield (dhramshetra kurushetekimkurvat Sanjaya – in the battlefield at Kurushetra, dear Sanjay, tell me what happened?). It’s interesting to note that Sanjay himself was not at the battle and had to rely on other means to tell the story – such is the case for many of us who are basing their reports on what is being told by someone in the conference. I cannot blame the press too much, having myself missed on a couple of points now and then. 

Reality of things – Lessons from Zen with Relevance to our Industry

As my Zen teacher says, We like the idea of things but not the reality of things. Ordinary coping is an attempt to shape our experience to always match our idea of things. If our experience maps onto our precious idea of things, this is called ‘happiness’ or ‘satisfaction’— getting what we want. This, we are taught, is the purpose of our lives and where we will find real meaning— it is the foundation for enjoying success.” In Zen training we practice turning toward and engaging with the bare reality of things. He further adds, “We are not continually trying to shape ourselves or the world to fit our idea of things. We are meeting things just as they are and yet working with them as skillfully as we can. Zen practice encourages and supports this skillfulness.”

When the industry got to immersion lithography, the biggest challenge was how to get rid of bubbles in the water. We certainly need to do a lot more and solve problems on many technical and infrastructure fronts. EUVL indeed is complicated, as it not only involves a new type of scanner but also changing the infrastructure for mask, resist and modeling. Materials, high temperature plasmas, lasers, contamination, fabrication and metrology— you name it. Moore’s Law did not say that scaling is going to be easy or inexpensive– it just said that it will happen.

I may be the only person in the world who believes that “EUVL IS NOT LATE,” and that “WE HAVE DONE WELL” with EUV technology development. Let us not forget how much time it took us to get immersion fully working, even though we had many fewer problems. The investment now is going to pay off. Chip makers know best, and so have decided on EUVL.

New SEMATECH

One last thing. During the conference I ran into Mark Melliar-Smith, ex-CEO of SEMATECH. it was a nice surprise, as I thought he had retired some time ago. I had just finished putting up an award on my office wall that I got from him many years ago. Seeing him reminded me of good old days of the semiconductor industry, when companies got together to address infrastructure challenges and consider technical challenges where success was not guaranteed. We saved money and tackled big challenges. It had to be done then, and later on we got away from the idea. It may be time to think about a new SEMATECH regarding efforts to extend Moore’s Law. In my previous blog, I listed many things that a New SEMATECH (if we ever have it again) could do, like considering stochastics at the 5 and 7 sigma levels, new resist chemistries, and new types of sources such as those proposed by PSI. We will not get zero defect mask blanks without considering new materials, ultrafine polishing techniques and contamination control options. Chip makers (it is usually Intel which spends more than others) cannot do this alone, and suppliers cannot afford to look at these challenges on their own, either. If we want to pursue new frontiers to continue pushing Moore’s Law forward, we need a new consortium like SEMATECH. I do not mind wishing for things, as that is the first step for things to happen! I leave you with a favorite quite from the Persian poet Hafez:

“I should not make any promises right now,
But I know if you
Pray
Somewhere in this world -
Something good will happen.”
― Hafez

 

2017 SPIE Advanced Lithography – EUVL Conference Update

March 13th, 2017

By Vivek Bakshi, EUV Litho, Inc.

To simplify the vast amount of information from the 2017 SPIE AL EUVL Conference for my blog, I have adopted a new format. It includes a short summary of EUVL Status, a list of notable updates, and additions to the current list of EUVL Challenges (previously published on this site). An additional commentary will follow this blog.

  1. Current EUVL Status 

Source: Current power of 148 W corresponding to 104 wafers per hour (WPH) scanner throughput in-house at ASML. Stable 130 W noted in field. 375 W in lab EUV sources in burst mode at 50 KHz. 200 W of stable power is possible in field in 2017. Source power now meeting requirements for introduction of NXE3400. Current source availability at 75%, needed at >90%. Droplet generators and collector lifetime improving but need further improvement.

Scanners: Fourteen EUVL scanners in field. Four shipped in 2016. 0.3 nm critical dimension uniformity (CDU) and 1.8 nm overlay. 148 W and 104 WPH with increase of 8 wafers per hour (WPH) achieved via increase of stage speed at the same source power.

Masks: Mask blank defects acceptable for now via defect avoidance and repair.

Mask Pellicles: Mask defect addition during manufacturing is still a concern for chip makers. Pellicles are at 125 W and need to be ready for 250 W by 2H 2017. 

Mask Defect Inspection: Samsung has made its own AIMS tool and plans to use it for high volume manufacturing (HVM). Tool is using HHG based EUV source and a scanning zone plate. Zeiss is now shipping its first AIMS tool. Actinic Patterned Mask Inspection (APMI) tool still missing. Mask defect inspection via wafer inspection for now, at a cost and with lower yield. APMI is only red flag item for 7 nm insertion of EUVL. 

Resist: Lots of talk about stochastics, but I believe it will be addressed and it is not a showstopper. Important to note that resist image is only an intermediate step and there are still several knobs available to improve the performance of the final circuit – which is what matters.

  1. Notable Updates 

Scanner and imaging

  • Increase of throughput by 8 WPH via greater stage speeds is first such increase, with more to come. Now expect source power of 210 W to give 125 WPH instead of 250 W (increase in throughput via stage speed improvement)
  • Extension of EUVL to low k1 may be more difficult than for 193i. Discussion of various factors and how to address them has started.
  • More enthusiasm for high NA scanner, as it can help with line width roughness (LWR) and extension to lower k1. Detailed checklist of High NA challenges from Samsung.
  • Data showing that around 5 sigma errors deviate from standard distribution. We do not understand error distribution behavior at 5 to 7 sigma (it is no longer a normal distribution). We now need to print one trillion vias in one exposure with no open! 3 sigma is no longer enough.
  • Closer cooperation among litho, etch and deposition is the way to reduce EPE and address stochastics. Work has already started.
  • Scanner to scanner variation higher for EUVL than for 193i. How to address this in optical proximity correction (OPC)? Will this lead to scanner specific EUV masks?

Source

  • Need to better understand source power requirements for 3 nm and beyond. How much additional help we will get from scanner for increasing throughput? Is 500 W enough? Will we need additional power?
  • Power scaling to 500 W is still lots of work and not a done deal as conversion efficiency decreases at higher pulse energy (favored method for power scaling). 

Resist

  • Introduction at 7 nm planned at 20 mJ dose
  • Micro bridging (aka nano bridging) of resist is a new challenge reported by several people. Its relationship to dose, type of resist and LWR is not clear. Some said that this may become bigger than LWR issue. Papers showing OPC and Litho- etch optimization can help reduce this effect.
  • Continued work on chemically amplified resists (CAR), metal based inorganic resists and molecular resists to support 7 nm and beyond.
  • Out of Band (OOB) filter in now in scanner that also acts to keep resist outgassing products out.
  • Sigma alone may be insufficient to characterize LWR. New additional variables needed? 

Mask

  • Replacement of current mask absorbers by Ni to improve imaging. Continued review of new mask structures with improved imaging potential, but patterning challenges exist for these new stacks.
  • Need source mask optimization to address 3D mask effects.
  • High sensitivity to Pellicles defects for small pupil fills imaging
  • Need for further analysis and reduction of defects in the scanner, that end up on masks, generated during manufacturing.
  • Current fixed pellicle design needs to evolve to provide future solutions.
  • New carbon nanotube based pellicles from IMEC
  • New APMI design from PSI/ETH, supported by small synchrotron based EUV source.

New terms heard at SPIE AL

  • Etch Color, CD healing, Black Swans (at seven sigma), Vote-taking Lithography (resurrection of a 1986 idea to move away from 100% defect free mask requirements), nano bridging and micro bridging of resists, and Tone inversion.

Most Interesting Papers

  • Couple of papers on stochastics – Line edge roughness (LER) performance targets for EUVL (10143-10) by Tim Brunner of GlobalFoundries and Lithographic Stochastics – extrapolating to 7 sigma (10143-31) by Robert Bristol of Intel.
  1. Additions to existing list of challenges for EUVL

7 nm

Nothing new

5 nm

Micro bridging of resists

Error distribution at 5-7 sigma 

3 nm

Power scaling to 500 W and beyond

Micro bridging of resists

Error distribution at 5-7 sigma

Areas of Focus and List of Challenges for EUV Lithography at 7nm, 5nm and 3nm Nodes

February 22nd, 2017

By Vivek Bakshi, EUV Litho, Inc.

As we look forward to 2017 SPIE Advanced Lithography Conference in San Jose next week, the focus once again will be on EUV Lithography, its readiness for manufacturing and plans of chip makers for starting to use EUVL in their fabs.

Insertion is planned from 7 to 5nm nodes by chip makers in coming years. The areas of focus at 7nm are mostly related to productivity and uptime goals of sources in addition to pellicle. The 5nm insertion has few other areas come into focus where more work is needed like actinic inspection, resist readiness and mask blank defectivity – although none of them is a showstopper.

List of challenges pick up lot more at 3nm node, as we consider high NA scanner, corresponding newer design for EUV masks and need to for upto 500 W of source power. A detailed list of these challenges is worth a review and is now published at the website www.euvlitho.com as topics for 2017 EUVL Workshop in June 2017. I will be updating this list after as well as sharing my opinion on the latest with EUVL in coming weeks after this year’s SPIE AL meeting.

Bringing you Holiday Cheers – Courtesy of Moore’s Law

December 21st, 2016

Vivek Bakshi, EUV Litho, Inc.

Author’s preface: This article is a departure from my usual high-tech language, because I think our industry needs to do more to educate non-technical readers about how their treasured electronic devices got to be so cheap and powerful. Our success in realizing Moore’s Law has been one of the greatest achievements in modern science, and we must continue doing all we can to continue that progress. Please feel free to share this essay as a holiday gift to anyone in your life who benefits from the achievements of lithography.

For many, our Christmas holiday cheer is wrapped around getting the latest gadget that brings us more power to do things than we had the year before ‒ be it a new iPhone, iPad, laptop or some other high-tech gizmo. Added to this annual ritual, which we now intuitively expect but do not quite notice, is that we pay less or the same for these gadgets than we did in previous years – even though they may run twice as fast and store three times as many photos and videos. At the heart of this happy surge are the computer chips that grow more powerful every year without increasing their price. I would like to tell you how we in the computer chip industry do this, and what it will take to continue this trend in the coming decades.

Technology was not always like this. Growing up in the early 80s in India, where my dad worked for the telephone company, I remember that when we got a new phone it was the same rotary dial model with just a new exterior body, and maybe a new color. If today’s technology were moving at the same speed as then, we would only be getting a new cover for our iPhone or a new computer mouse for Christmas, and not more powerful gadgets.

To understand this phenomenon, we need to look at the leading-edge computer chips that are the heart of all these tools, made by leading chipmakers like Intel, Samsung and others. Inside these microchips are tiny transistors and other circuit elements that do the work. The reason these devices can deliver more power every year at lower cost is because the advancement of computer technology is guided by Moore’s Law, named after Gordon Moore, co-founder of Intel Corporation. Moore proposed this law in 1965, saying that number of transistors per square inch would double every two years or so.

We have been able to follow Moore’s Law so far by making transistors and other circuit elements smaller every year. Making computer chips takes many steps, the most critical of which are embodied in a process called Lithography, which involves printing the images of circuits. To print smaller and smaller transistors, we need to be able to resolve the printed images. British physicist Lord Rayleigh (1842-1919) pointed us to “knobs” that we can turn to resolve ever-smaller images. Prominent knobs are color of the light for printing (wavelength), design of optics (numerical aperture) and printing under something more dense, like water. We also have also learned lots of tricks (called optical proximity corrections and multiple patterning) that let us keep on printing smaller and smaller features.

The current technology of choice for advanced printing of computer chips is called 193 nm optical projection lithography, which involves a zillion optical tricks and repeats the printing process three or four times to make one image. However, 193 nm has been running out of steam for some time. This means that either we cannot make computer chips more powerful by just shrinking the size of features, or the cost of doing so will be a lot more. Neither of these are acceptable solutions, and that is where Extreme Ultraviolet Lithography (EUVL) comes into play.

EUVL promises to extend Moore’s Law by changing the color of light used for printing – from current 193 nm light from excimer lasers to 13.5 nm light from plasma sources. Alas, we cannot see either wavelength with our unaided eyes. This switch of color came with big physics challenges as EUV Light, with its photons of 14x energy, interacts with matter very differently than photons from excimer light. This change has resulted in a massive amount of work over many decades on light sources, optics and photo-sensitive chemicals for developing images. For these reasons, EUVL has taken many decades of worldwide effort and investment and is now expected to be used by leading chipmakers by 2018- 2020 time frame.

We would certainly be lost without the ever-more powerful computer chips that we are now used to having at our disposal every year. So now you know whom to thank for your new holiday gadgets, and you can rest assured that they will keep on working to ensure the benefits of Moore’s Law will continue for years to come.

Highlights from 2016 EUV Source Workshop – Work on Conversion Efficiency of EUV Sources and Continued Progress in Source Technology

December 19th, 2016

By Vivek Bakshi, EUV Litho, Inc.

The 2016 Source Workshop was held Nov 7-9, 2016 at ARCNL, Amsterdam, The Netherlands. During the workshop we received new information about EUV source power, updating what we learned at the EUVL Workshop in June. ASML now has 125 W sources in field with their uptime improving, and 210 W dose controlled sources in lab, with 5.5 % conversion efficiency (CE). This leads me to predict that we will be able to have 250 W in field by 2018, which will be needed to support manufacturing at 125 wafers per hour. Another piece of good news on the high power source front is the continued solid progress by the second-largest supplier of HVM EUV sources, Gigaphoton. They now have 100 W @ 5% CE, with 95% duty cycle for 5 hours of continuous operation.

There were reports of continued progress on EUV metrology sources, but they are still years away from being integrated into the next generation of mask defect inspection tools. In the workshop, I heard that Zeiss is now working closely with suppliers to evaluate their EUV metrology sources for their next generation AIMS tool. We also need patterned mask inspection (PMI) tools to be ready sooner than later, and I was happy to see a presentation by KT on the status of the source for their PMI tool. However, when and if this tool will become reality is still unknown, while these tools will be needed at 5 nm application of EUVL in fabs.

This year there were several papers (experimental and theoretical) on how to increase CE of sources by looking deeper into the working of EUV sources. In EUV sources, the laser energy (which is at 10 micron wavelength) is converted into 13.5 nm photon. Current reported CE is 5.5 to 6%. Can we can get more efficient?

We learned, via plasma measurements, how we can better tweak the delay and shape of laser pre-pulses (Kyushu University papers) and were told about development of pre-pulse lasers to enable the delivery of those optimum pulses (work from HiLase).

I found interesting the work of Hanneke Gelderblom, Univ. of Twente and Dmitry Kurilovich, ARCNL. They are using “water drops as scale model for tin” to understand the scalability of hydrodynamic stability of droplets interacting with lasers. They found that they can adjust parameters to work in regions to avoid drop breakups during interaction of laser with droplets, while looking for greater laser absorption to increase CE. It was a good example of how we can use learnings from other disciplines to improve the functionality of EUV sources.

Gerry O’Sullivan of UCD pointed to the need for maximizing the line emission by reducing opacity and reducing recombination. He noted that plasma density has a “sweet spot” for a maximum CE and optimized CE. He also described his wedged target colliding plasma that can be better matched to CO2 for increasing CE.

A most interesting CE paper to me was one by Mikhail Basko. He pointed out that in principal, 20% CE is possible (based on 40% spectral efficiency calculations) but in reality only 9% CE can be achieved. He pointed that 2.5% of CE is lost as the kinetic energy of plasma flow, while rest of CE is dissipated due to non-uniformity of temperature across the “working” zone and in-band reabsorption. We need to find ways to achieve this optimum density profile in our tin targets to get to 9%.

There were several interesting papers on modeling efforts to improve CE (LLNL, ISAN, Cymer) and generation of fundamental data to improve modeling. Such efforts are going to be important as we run out of knobs readily available to us today to improve CE, and we must look deeper into the working of plasma sources to squeeze those additional EUV photons out of plasma and search for stable operational modes for sources that can be sustained in factories around the clock.

We had many excellent papers on XUV sources and their applications to support manufacturing in the semiconductor industry and beyond. Hans Hertz in his keynote speech described his water window microscope, which with a 200 W laser of 600 picosecond pulse operating at 2 kHz gives an early synchrotron level of brightness. It can now do 3D tomography with a 10s exposure. These developments were possible due to a new multilayer mirror with >4% reflectivity (optiXfab) at water window wavelengths. He had reported the development of these new multilayer mirrors in last year’s source workshop, and decided to incorporate them in his tool to achieve this progress.

This year’s workshop had the highest attendance ever. I was happy to see continued work by the research community and suppliers to better understand the working of EUV sources, so that we can achieve those 500+ W sources that can operate 24/7 in fabs with 80-90% uptime.

Pushing Frontiers of EUV Source Technology – 2016 Source Workshop (November 7-9, 2016)

October 20th, 2016

By Vivek Bakshi, EUV Litho, Inc.

EUV Sources remain the key component for ensuring EUV Lithography’s entry into fabs for high-volume manufacturing. Two big factors that have enabled dramatic progress in source readiness are related to improvements in source power and source lifetime. Now the question is how far we can push source power and lifetime, and what is needed to enable continued progress.

For answers, we need to look into the fundamentals of plasma based EUV sources, as well new engineering designs. The present conversion efficiency (CE) of sources is a couple of percent, while the theoretical maximum approaches 8%. If we are at 2.5% CE today, it means we can get ~ 3 times more EUV photons from the same level of energy input, if sources could be operated closer to 8% CE. The lifetime (optics and fuel delivery system) also needs to be such that 90% uptime goals of tools can be met.

During the upcoming 2016 Source Workshop, we will have papers taking a closer look at these topics. There are several papers on how to increase the CE of sources to allow us to get more source power. There will be another session on plasma dynamics of EUV source to further our understanding and enable newer designs of sources that will help bring about better CE and longer source lifetimes.

Another important topic is EUV sources for metrology. Low power but brighter EUV sources than those available today are needed for actinic inspection of masks. We will have new potential designs from five suppliers for actinic EUV sources, as well as papers on high harmonic generation (HHG) and free electron laser (FEL) based sources for EUVL. In addition, we will have sessions on XUV sources and their application in patterning and other industrial application like water window microscopy.

I look forward to these new ideas and updates in the EUV and XUV source technology area. The Source Workshop this year is in Amsterdam, The Netherlands, held in conjunction with ARCNL. Dates are November 7-9, 2016 and additional information is available at www.euvlitho.com.

Update from EUVL Workshop in Berkeley

July 22nd, 2016

By Vivek Bakshi, EUV Litho, Inc.

The 2016 EUVL Workshop was held last month at LBL in Berkeley, where we heard the latest news on EUV Lithography R&D development topics. The keynote talks were given Harry Levinson (GlobalFoundries), Britt Turkot (Intel) and Igor Fomenkov (Cymer/ASML). There were progress reports on the current technical areas of focus that I will talk about below. However, I would like to point out first that since the Workshop ended, both TSMC and Samsung have announced plans to use EUV Lithography in production at the 7 to 5 nm node. Both expect to receive the NXE3400 production-level EUVL scanner during the first half of next year, which they will adapt for 7 nm node products. This speaks for itself in terms of EUVL readiness for production.

EUV source power continues to make progress, with meaningful demonstration of >200 W by both Cymer (an ASML company) and Gigaphoton. Both suppliers now think that 500 W EUV power is feasible. Not long ago, sources appeared to be the main obstacle to the introduction of EUVL into commercial production. However, presenters from Cymer (Igor Fomenkov) and Gigaphoton (Hakaru Mizoguchi) convinced me that 250 W (and hopefully 500 W) are achievable. For this reason, both Igor and Mizoguchi-san deserve to be called the “Saviors of EUVL.” Of course, they each represent a large group of multi-disciplinary teams, who have achieved a goal that many thought impossible. True, sources still need to meet operational cost and uptime goals in order to satisfy manufacturing requirements. However, steady progress is being made on this front, as pointed out by Intel in their keynote talk. I also expect 200+ W to be achieved in fabs sometime in 2017.

Although chip makers have figured out how to live with mask defects for now via defect avoidance and repairs, mask defect reduction is certainly on the wish list. Patterned mask defect inspection (PMI) is being done in different ways, with wafer inspection being one of them. Alternate PMI techniques were discussed in the presentations as well during the Workshop. Lack of a specific PMI tool remains a key issue for cost-effective, EUVL based manufacturing. I believe that lack of commercial metrology EUV sources that meet brightness requirements to support PMI and other actinic inspection tools remains a big gap, but no one seems to be coming forward and addressing this deficiency. We know we need it, so why not work on it? It is going to get more expensive without a PMI tool and other inspection tools with low throughput in the absence of a bright EUV metrology source.

Pellicles to protect masks can now withstand 125 W of thermal load, with 250 W as the present goal. I see progress, but we are not at 250 W yet.

The Industry is finally realizing that in order to make substantial progress in developing EUV resists, we need to get back to basics and better understand how they work. As EUV resists operate differently than 193 nm resists (via secondary electrons), there’s a lot that we still need to understand. There was a good set of papers on this topic, led by Frank Ogletree of LBL and others. I certainly hope that we will see lots of industry support for his work, as the return on investment on such basic research is sure to be huge.

The Workshop was moved to CXRO, LBL in Berkeley, CA this year. This year’s Workshop, the ninth to date, was the best- attended yet and offered the most papers ever. Participants found the new location very convenient with regard to travel logistics and access to area colleagues working on EUVL. CXRO continues to be a leader in EUVL R&D and has recently announced a new consortium, EUREKA, that will support continued EUVL development.

The Workshop proceedings can be downloaded at www.euvlitho.com.

Latest on EUVL Development to be Discussed in EUVL Workshop in Berkeley

June 6th, 2016

By Vivek Bakshi, EUV Litho, Inc.

During this year’s SPIE Advanced Lithography conference in San Jose, there was a definite switch to optimism about EUVL from all keynote speakers. The message of “Not if, but when” for EUVL ‒ with early adoption expected in coming years ‒ was clearly heard from leading-edge chip makers and EUVL suppliers. With demonstration of 200 W source in the lab and steady progress on source power and availability, the focus has now shifted to fab productivity, mask, pellicles and resists.

This year’s 2016 EUVL Workshop is being held in Berkeley, CA, organized in cooperation with CXRO. With keynotes from Intel, GlobalFoundries and ASML, along with 45 speakers and about 50 papers, we expect to hear a good bit of new information on these topics and stimulating discussion of R&D topics. In addition, we will hear about alternate actinic inspection techniques and fundamentals of EUV resists. For EUV resist, where the chemistry is dominated by secondary electrons, researchers are looking into understanding chemical reactions in this new realm to develop resists that pattern better at EUV wavelengths.

I am looking forward to finding out the latest on EUVL in this workshop. The final agenda and abstract book is available at www.euvlitho.com

2015 Source Workshop – What we expect to hear

November 2nd, 2015

By Vivek Bakshi, EUV Litho, Inc.

EUV Sources remain the key enabler to move EUVL into manufacturing, and we look forward to the upcoming 2015 Source Workshop (November 9-11, 2015, Dublin, Ireland) for the latest developments and status of EUV Source technology. Both high-volume manufacturing (HVM) level and metrology EUV sources are needed for chip manufacturing using EUVL. For HVM sources, power level and availability are needed to generate cost effective throughput.

We expect to hear from the user (Intel) as well as source makers (ASML and Gigaphoton) on the latest performance of these sources. At last summer’s 2015 EUVL Workshop we learned that 80 W sources are in the field, but availability needs to improve. So we look forward to finding out the latest performance results from users and suppliers. We will also have a session of FEL-based EUV sources in this workshop. FEL is currently being explored as a technology option for 1000 W and higher EUV sources.

Metrology sources are equally important as they support mask defect metrology tools. Our agenda includes all current EUV metrology source suppliers as well as most research organizations that are working to develop these types of sources. For metrology sources, brightness, stability and source availability are the key matrix of performance.

2015 EUVL Workshop Update

I usually take a week or two to summarize the workshops that I organize or attend, as I am not a reporter but more of an analyst. However, I did not get to report on the highlights from the EUVL Workshop, as I was out on paternity leave. However, proceedings were made available after the workshop, as always.

Although much interest has been shown over the last year in the high absorbing EUV resists – which can reduce the source power requirements for HVM scanner – we learned in the 2015 EUVL Workshop that they are not ready (and may not be ready for many years to come) for commercial use. Hence, the pressure remains for source power scaling, as it will continue to be primary enabler of increased throughput in the near future.

Earlier this year, KLA-Tencor put the patterned mask defect metrology development on the back burner. We need this mask defect metrology tool for patterned wafers for manufacturing via EUVL. Hopefully, their planned merger with LAM will revitalize this program. In any case, the performance (throughput) of this and other mask defect metrology tools still depends on the metrology sources. We expect to hear about the status of these sources in the 2015 Source Workshop.

EUV Lithography – What is Next and When?

June 8th, 2015

By Vivek Bakshi, EUV Litho, Inc.

This year started with an announcement, during the SPIE AL Conference, of the achievement of 100 W+ power from high volume manufacturing (HVM) EUV sources in the fab. One hundred watts at intermediate focus has been a long-standing benchmark and is a definite success, and we also can be sure that source power and availability will increase this year. The focus will now change to addressing the remaining challenges of EUVL, with questions turning on what comes next and when, as the industry prepares to deploy EUVL into HVM.

During the 2015 EUVL Workshop (June 15-19, 2015), we expect to get answers to these questions in the various keynote and invited talks. And to make sure the best information is available, we are also having a panel discussion that will address the following questions:

1. When do you expect the industry to insert EUVL into high volume manufacturing (year and process node)?

2. What are the top three challenges (technical and business) that need to be addressed to ensure readiness of EUVL for HVM? (Some examples of technical challenges are source power and availability, pellicles, mask inspection infrastructure and high absorption resists. An example of a business challenge is readiness of PMI tools.)

3. How will the industry achieve the following targets for EUV Source power: 250 W, 500 W and 1000 W?

4. When do you think that HVM worthy EUV resists with sensitivity of <5 mJ will be ready?

5. For extension of EUVL to smaller nodes, what are the pros and cons of High NA vs. Double Patterning?

6. If the industry had to start all over again to develop EUVL for HVM, what are the top three things you think should be done differently?

We hope you will join us in the Workshop as experts present their responses on these topics and answer  questions from the audience. More information on the Workshop, including the agenda and abstract book, is available on our website www.euvlitho.com.

The EUVL Workshop will be relocated from Maui to the U.S. mainland in 2016.

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