Part of the  

Solid State Technology

  Network

About  |  Contact

Posts Tagged ‘SPIE-AL’

Flagello to receive Zernike Award at SPIE Advanced Lithography

Friday, February 24th, 2017

Flagello-DonisDonis Flagello, president, CEO, and COO of Nikon Research Corporation of America (NRCA), will be presented with the 2017 Frits Zernike Award for Microlithography on Monday 27 February during SPIE Advanced Lithography in San Jose, California. The award, presented annually for outstanding accomplishments in microlithography technology, recognizes Flagello’s leading role in understanding and improving image formation in optical lithography for semiconductor manufacturing.

A prominent member of the industry since the early 1980s and a longtime SPIE Fellow, Flagello has primarily focused on the rigorous application of physics to lithography modeling and problem solving. Early in his career, while at IBM T.J. Watson Research Center, he developed the first practical test for measuring flare in optical lithography tools and made major contributions to high numerical aperture (NA) modeling including vector and polarization effects, and radiometric correction. At ASML he played an important role in providing analysis of aberrations for new systems and high-NA imaging effects due to polarization.

Another notable aspect of his career, Flagello’s presentations at lithography conferences and papers in various journals have inspired a better understanding of optics and resist behavior and helped drive optical lithography forward, colleagues said. “His presentations are known for their combination of humor with a deep understanding of the complex interactions between physical optics and lithographic process technology,” said David Williamson, an NRCA Fellow and previous Frits Zernike Award winner. “His combined theoretical and practical production experience and knowledge are rare in this field.”

—E.K.

SAQP Specs for 7nm finFETs

Friday, March 11th, 2016

As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

  • 7.0nm Critical Dimension (CD) after etch,
  • 0.5nm (3sigma) CD uniformity (CDU), and
  • <1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Litho becomes Patterning

Thursday, February 25th, 2016

Once upon a time, lithographic (litho) processes were all that IC fabs needed to transfer the design-intent into silicon chips. Over the last 10-15 years, however, IC device structural features have continued to shrink below half the wavelength of the laser light used in litho tools, such that additional process steps are needed to form the desired features. Self-Aligned Double Patterning (SADP) schemes use precise coatings deposited as “spacers” on the sidewalls of mandrels made from developed photoresist or a sacrificial material at a given pitch, such that after selective mandrel etching the spacers pitch-split. SADP has been used in HVM IC fabs for many years now. Self-Aligned Quadruple Pattering (SAQP) has reportedly been deployed in a memory IC fab, too.

An excellent overview of the patterning complexities of SAQP was provided by Sophie Thibaut of TEL in a presentation at SPIE-AL on “SAQP integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications.” Use of a spacer-on-spacer process flow—enabled by clever combinations of SiO2 and TiO2 spacers deposited by Atomic Layer Deposition (ALD)—requires the following unit-process steps:
1 193i litho,
2 ALD spacers,
2 wet etches, and
4 plasma etches.

Since non-litho processes dominate the transfer of design-intent to silicon, from first principles we should consider such integrated flows as “patterning.” Etch selectivity to remove one material while leaving another, and deposition dependent on underlying materials determine much of the pattern fidelity. Such process flows are new to IC fabs, but have been used for decades in the manufacturing of Micro-Electrical Mechanical Systems (MEMS), though generally on a patterning length scale of microns instead of the nanometers needed for advanced ICs. R&D labs today are even experimenting with Self-Aligned Octuple Patterning (SAOP), and based on the legacy of MEMS processing it certainly could be done.

—E.K.


Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.