MPU Cores and Legal Boors
As reported by The Register, AMD has been sued by a customer who claims that the number of Bulldozer cores in some Opteron and FX microprocessor (MPU) chips are fewer than advertised. The claim is based on the argument that a “real” MPU core has it’s own floating point unit for calculations, and that consumers were misled by product claims. I am not a lawyer (IANAL) and have no connections to either side in this case, but AMD’s website (http://www.amd.com/en-us/products/processors/desktop/fx#) now clearly indicates that cores share a Floating Point (FP) scheduler.
The Figure shows that the confusion is due to the design of the Bulldozer microarchitecture wherein a pair of cores is called a module, and each pair shares a branch prediction engine, an instruction fetch and decode stage, a floating-point math unit, a cache controller, a 64K L1 instruction cache, a microcode ROM, and a 2MB L2 cache. The lawsuit claims, “Because AMD did not convey accurate specifications, tens of thousands of consumers have been misled into buying Bulldozer CPUs that do not conform to what AMD advertised, and cannot perform the way a true eight core CPU would (i.e., perform eight calculations simultaneously).”
This is analogous to someone buying a car with a V8 internal combustion engine, and then suing the manufacturer because there are only 4 fuel injectors and not all cylinders fire simultaneously. The claim that “true” multi-cores must be capable of functioning simultaneously is like claiming that “true” multi-cylinder engines must be capable of all cylinders firing simultaneously. AMD has officially responded with the statement that, “We believe our marketing accurately reflects the capabilities of the Bulldozer architecture which, when implemented in an 8-core AMD FX processor, is capable of running eight instructions concurrently.” There seems to be little legal difference between “simultaneously” and “concurrently” but IANAL.
Sure, there’s a technical difference and likely a slight performance benefit to direct fuel injection into each cylinder, but raw performance is only one aspect of the design trade-offs between performance and cost and reliability. Sharing 1 fuel injector between 2 cylinders often provides an optimum of performance/cost/reliability in internal combustion engines. Sharing 1 FPU between 2 logic cores seemingly provides an optimum of performance/cost/reliability in CPUs.