Part of the  

Solid State Technology

  Network

About  |  Contact

Bottoms-up ELD of Cobalt Plugs

As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and contacts. The unit-process is intended to be integrated into flows to produce scaled interconnects for logic and DRAM ICs at the 7nm node and below. Co-incidentally at IITC this year, imec and Lam also presented on a new ELD copper (Cu) process for micron-plus-scale through-silicon vias (TSV).

The bulk resistivities of metals commonly used in IC fabrication are as follows (E-8 Ω⋅m):
Cu – 1.70,
Al – 2.74,
W – 5.3, and
Co – 5.8.
Of course, the above values for bulk materials assume minimal influence of grain sizes and boundary layers. However, in scaled on-chip interconnect structures using in today’s advanced ICs, the resistivity is dominated by grain-boundaries and interfacial materials. Consequently, the resistivity of vias in 7nm node and beyond interconnects may be similar for Cu and Co depending upon the grain-sizes and barrier layers.

The melting temperatures of these metals are as follows (°C):
Al – 660,
Cu – 1084,
Co – 1495, and
W – 3400.
With higher melting temperature compared to Cu, Co contacts/plugs would provide some of the thermal stability of W to allow for easier integration of transistors and interconnects. Seemingly, the main reason to use Co instead of W is that the latter requires CVD processing that intrinsically does not allow for bottom-up deposition.

—E.K.

Leave a Reply


Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.