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Cross-point ReRAM Integration Claimed by Intel/Micron

July 29th, 2015

The Intel/Micron joint-venture now claims to have successfully integrated a Resistive-RAM (ReRAM) made with an unannounced material in a cross-point architecture, switching using an undisclosed mechanism. Pilot production wafers are supposed to be moving through the Lehi fab, and samples to customers are promised by end of this year.
HP Labs announced great results in 2010 on prototype ReRAM using titania without the need for a forming step, and then licensed the technology to Hynix with plans to bring a cross-point ReRAM to market by 2013. SanDisk/Toshiba have been working on ReRAM as an eventual replacement for NAND Flash for many years, with though a bi-layer 32Gb cross-point ReRAM was shown at ISSCC in 2013 they have so far not announced production.
Let us hope that the folks in Lehi have succeeded where HP/Hynix and SanDisk/Toshiba among others have so far failed in bringing a cross-point ReRAM to market…so this may be a “breakthrough” but it’s by no means “revolutionary.” Until the Intel/Micron legal teams decide that they can disclose what material is changing resistance and by what mechanism (including whether an electrical “forming” step is needed), the best we can do is speculate as to even how much of a breakthrough this represents.
—E.K.

Single-electron Molecular Switch 4nm Across

July 22nd, 2015

A molecule rotating on the surface of a crystal can function as a tunnel-gate of a transistor, as shown by researchers from the Paul-Drude-Institut für Festkörperelektronik (PDI) and the Freie Universität Berlin (FUB), Germany, the NTT Basic Research Laboratories (NTT-BRL), Japan, and the U.S. Naval Research Laboratory (NRL). Their complete findings are published in the 13 July 2015 issue of the journal Nature Physics. The team used a highly stable scanning tunneling microscope (STM) to create a transistor consisting of a single organic molecule and positively charged metal atoms, positioning them with the STM tip on the surface of an indium arsenide (InAs) crystal.
Dr. Stefan Fölsch, a physicist at the PDI who led the team, explained that “the molecule is only weakly bound to the InAs template. So, when we bring the STM tip very close to the molecule and apply a bias voltage to the tip-sample junction, single electrons can tunnel between template and tip by hopping via nearly unperturbed molecular orbitals, similar to the working principle of a quantum dot gated by an external electrode. In our case, the charged atoms nearby provide the electrostatic gate potential that regulates the electron flow and the charge state of the molecule.”

(Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics) (Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics)

The Figure shows that the diameter of the device is ~4nm, so by conservative estimation we may take this as the half-pitch of closest-packed devices in IC manufacturing, which leads to pitch of 8nm. As a reminder, today’s “22nm- to 14nm-node” devices feature ~80nm transistor gate pitches (with “10nm node” planning to use ~65nm gate pitch, and “5nm node” ICs expected with ~36nm gate pitch). Thus, these new prototypes prove the concept that ICs with densities 100x more than today’s state-of-the-art chips could be made…if on-chip wires can somehow connect all of the needed circuitry together reliably and affordably.
—E.K.

Electronic Materials Specifications and Markets

June 30th, 2015

At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.

Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.

As in prior years, SEMICON West includes many free and paid technology sessions and workshops, the Silicon Innovation Forum and other business events, as well as a profusion of partner events throughout the week.

—E.K.

Nakamura on blue light history and future

June 26th, 2015

Nobel Laureate Shuji Nakamura provided the keynote address to the attendees at the 57th annual Electronic Materials Conference held this week in Columbus, Ohio. His talk on “The History and Developments of InGaN-based LEDs and Laser Diodes” informed and entertained the audience of materials researchers, particularly since he followed first-principles of materials science and his natural inspiration to create the world’s first commercially viable blue LEDs over 20 years ago.
Nakamura-sensei is now legendary for showing excellent GaN-based blue LED functionality in an era when ZnSe was the main material explored by almost all scientists in the world due to six orders of magnitude superior defectivity level for the latter material (due to near zero lattice mismatch between ZnSe and GaAs, instead of the extreme mismatch between GaN and sapphire). In the 57th EMC keynote, he confessed that the only reason he began work on GaN was that almost everyone else was ignoring it so he could easily get papers published on the way to earning a Ph.D., and he initially had no plans to try to create a blue LED with the material.
However, when he bought a new MOCVD reactor to grow GaN on sapphire substrates he found the capabilities of the tool to be lacking so he began daily hardware modifications and test runs, and after some months began to get surprisingly strong data. Soon his group at Nichia was reporting world record GaN optoelectronic properties, and had developed both n- and p-type GaN. However, from first principles it was known that a double-heterojunction (DH) structure would allow for band-gap and hence wavelength tuning, so he then developed the world’s first useful InGaN MOCVD process and by 1993 was able to issue a press release claiming 1000 mcd LED output. “Indium gallium nitride is the most important material, but the Nobel committee didn’t say anything about Indium gallium nitride,” reminded Nakamura.
Most of the rest of the story is well known by now, including his precedent-setting lawsuit with Nichia, move to UCSB, and founding of Soraa.
Nakamura’s vision for the the future of blue (and through integration with phosphors “white”) light can be summed up as LEDs are good but lasers are better. Relatively speaking, with lasers the current density can by many times higher, and BMW and Audi have prototype laser headlamps that can reach 2-3x farther down the road compared to the best lamps today. The challenges today are to improve efficiency and cost. Efficiency for blue LEDs are now 50-60% while lasers are only ~30%. Also, blue laser production cost is now ~10x higher than that for blue LEDs.
—E.K.

ALD of Crystalline High-K SHTO on Ge

May 31st, 2015

Alternative channel materials (ACM) such as germanium (Ge) will need to be integrated into future CMOS ICs, and one part of the integration was shown at the recent Materials Research Society (MRS) spring meeting by John Ekerdt, Associate Dean for Research in Chemical Engineering at the University of Texas at Austin, in his presentation on “Atomic Layer Deposition of Crystalline SrHfxTi1-xO3 Directly on Ge (001) for High-K Dielectric Applications.”

Strontium hafnate, SrHfO3 (SHO), and strontium titanate, SrTiO3 (STO), with dielectric constants of ~15 and ~90 (respectively) can be grown directly on Ge using atomic layer deposition (ALD). Following a post-deposition anneal at 550-590°C for 5 minutes, the perovskite films become crystalline with epitaxial registry to the underlying Ge (001) substrate. Capacitor structures using the crystalline STO dielectric show a k~90 but also high leakage current. In efforts to optimize electrical performance including leakage current and dielectric constant, crystalline SrHfxTi1-xO3 (SHTO) can be grown directly on Ge by ALD. SHTO benefits from a reduced leakage current over STO and a higher k value than SHO. By minimizing the epitaxial strain and maintaining an abrupt interface, the SHTO films are expected to reduce dielectric interface-traps (Dit) at the oxide-Ge interface.

Much of the recent conference has been archived, and can now be accessed online.

—E.K.

Bottoms-up ELD of Cobalt Plugs

May 21st, 2015

As reported in more detail at Solid State Technology, during the IEEE IITC now happening in Grenoble, imec and Lam showed a new Electroless Deposition (ELD) cobalt (Co) process that is claimed to provide void-free bottoms-up pre-filling of vias and contacts. The unit-process is intended to be integrated into flows to produce scaled interconnects for logic and DRAM ICs at the 7nm node and below. Co-incidentally at IITC this year, imec and Lam also presented on a new ELD copper (Cu) process for micron-plus-scale through-silicon vias (TSV).

The bulk resistivities of metals commonly used in IC fabrication are as follows (E-8 Ω⋅m):
Cu – 1.70,
Al – 2.74,
W – 5.3, and
Co – 5.8.
Of course, the above values for bulk materials assume minimal influence of grain sizes and boundary layers. However, in scaled on-chip interconnect structures using in today’s advanced ICs, the resistivity is dominated by grain-boundaries and interfacial materials. Consequently, the resistivity of vias in 7nm node and beyond interconnects may be similar for Cu and Co depending upon the grain-sizes and barrier layers.

The melting temperatures of these metals are as follows (°C):
Al – 660,
Cu – 1084,
Co – 1495, and
W – 3400.
With higher melting temperature compared to Cu, Co contacts/plugs would provide some of the thermal stability of W to allow for easier integration of transistors and interconnects. Seemingly, the main reason to use Co instead of W is that the latter requires CVD processing that intrinsically does not allow for bottom-up deposition.

—E.K.

CMP Slurry Trade-offs in R&D

April 30th, 2015

As covered at SemiMD.com, the CMP Users Group (of the Northern California Chapter of The American Vacuum Society) recently held a meeting in Albany, New York in collaboration with CNSE, SUNY Polytechnic Institute, and SEMATECH. Among the presentations were deep dives into the inherent challenges of CMP slurry R&D.
Daniel Dickmann of Ferro Corporation discussed trade-offs in designing CMP slurries in his presentation, “Advances in Ceria Slurries to Address Challenges in Fabricating Next Generation Devices.” Adding H2O2 to ceria slurry dramatically alters the zeta-potential of the particles and thereby alters the removal rates and selectivities. For CMP of Shallow Trench Isolation (STI) structures, adding H2O2 to the slurry allows for lowering of the particle concentration from 4% to <2% while maintaining the same removal rate. Reducing the average ceria particle size from 130nm to 70nm results in a reduction in scratch defects while maintaining the same removal rate by tuning the chemistry, but the company has not yet found chemistries that allow for reasonable removal rates with 40nm diameter particles. The ceria morphology is another variable that must be controlled according to Dickmann, “It can seem counter-intuitive, but we’ve seen that non-spherical particles can demonstrate superior removal-rates and defectivities compared to more perfect spheres.”
Selectivity is one of the most critical and difficult aspects of the CMP process, and arguably the key distinction between CMP and mere polishing. The more similarity between the two or more exposed materials, the more difficult to design high selectivity in a slurry. Generally, dielectric:dielectric selectivity is difficult, and how to develop a slurry that is highly selective to nitride (Si3N4) instead of TEOS-oxide (PECVD SiO2 using tetra-ethyl-ortho-silicate precursor) was discussed by Takeda-san of Fujimi Corporation. In general, dielectric CMP is dominated by mechanical forces, so the slurry chemistry must be tuned to achieve selectivity. Choosing <5 pH for the slurry allows for reducing the oxide removal rate while maintaining the rate of nitride removal. Legacy nitride slurries have acceptable selectivities but unacceptable edge-over-erosion (EOE) – the localized over-planarization often seen near pattern edges. Reducing the particle size reduces the mechanical force across the surface such that chemical forces dominate the removal even more, while EOE can be reduced because negatively charged particles are attracted to the positively charged nitride surface resulting in local accumulation.
—E.K.

Batteries? We don’t need no stinking batteries.

February 28th, 2015

We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources. At ISSCC2015 in San Francisco last week, there were several presentations on novel chip designs that run on mere milliWatts (µW) of power, and the most energy efficient circuit blocks now target nanoWatt (nW) levels of power consumption. Two presentations covered nW-scale microprocessor designs based on the ARM Cortex-M0+ core, and a 500nW energy-harvesting interface based on a DC-DC converter operating from 1µm available power was shown by a team from Holst Centre/imec/KU Leuven working with industrial partner OMRON.

Read more on this in MicroWatt Chips shown at ISSCC available at SemiMD.

—E.K.

Oscar for DMD Inventor Hornbeck

February 10th, 2015

Texas Instrument Oscars 1Kudos to Dr. Larry J. Hornbeck, the extended team at Texas Instruments (TI) that has worked on Digital Micromirror Device (DMD) technology, and to the TI executives who continued to fund the R&D through years of initial investment losses. Hornbeck has been awarded an Academy Award® of Merit (Oscar® statuette) for his contribution to revolutionizing how motion pictures are created, distributed, and viewed using DMD technology (branded as the DLP® chip for DLP Cinema® display technology from TI).

The technology now powers more than eight out of 10 digital movie theatre screens globally. Produced with different resolutions and packages, DLP chips also see use in personal electronics, industrial, and automotive markets. The present good-times with DMD are enjoyed only because TI was willing to make a major long-term bet on this novel way to modulate pixel-arrays, which required building the most complex Micro-Electro-Mechanical System (MEMS) the world had ever seen.

Development of the DLP chip began in TI’s Central Research Laboratories in 1977 when Hornbeck first created an array of “deformable mirrors” controlled with analog circuits. In 1987 he invented the DMD, and TI invested in developing multiple money-losing generations of the technology over the next 12 years. Finally, in 1999 the first full-length motion picture was shown with DLP Cinema technology, and since then TI claims that the technology has been installed in more than 118,000 theaters around the globe. We understand that TI now makes a nice profit from each chip.

“It’s wonderful to be recognized by the Academy. Following the initial inventions that defined the core technology, I was fortunate to work with a team of brilliant Texas Instruments engineers to turn the first DMD into a disruptive innovation,” said Hornbeck, who has 34 U.S. patents for his groundbreaking work in DMD technology. “Clearly, the early and continuing development of innovative digital cinema technologies by the DLP Cinema team created a definitive advancement in the motion picture industry beyond anyone’s wildest dreams.”

—E.K.

Micro-Buckled 3D Silicon Scaffolds

January 31st, 2015

3Dsilicon_CompressiveBucklingA new silicon microstructural solution announced this month is so powerful in creating 3D patterns from 2D surface machining that I just have to share. The figure shows 3D silicon microstructures formed by compressive buckling. The method can be used to create objects with features as small as 100 nm that could be useful for developing new technologies for medicine, energy storage and even brain-like electronic networks. Note that the silicon is surface-machined using standard MEMS processes, and that all manner of silicon circuitry and thin-film sensors could be integrated into this silicon.

Colleagues from the University of Illinois at Urbana-Champaign, Northwestern University, Zhejiang University, East China University of Science and Technology, and Hanyang University created the new 2D-to-3D fabrication technique. Their trick is that after all other surface machining they chemically modify the square anchors in the surface pattern such that they are sticky. After the 2D pattern is released it is transferred onto a sheet of stretched silicone rubber. Allowing the rubber to relax back to its natural shape draws the squares toward each other, while the rest of the silicon buckles upwards. Using this type of controlled buckling, the team managed to produce a variety of elaborate 3D shapes.

The researchers even produced structures with multiple levels of elevation by designing shapes in which the relief of stress in the initial 2D shape would create further buckling, raising another part of the shape further. John Rogers of the University of Illinois at Urbana-Champaign, who is part of the micro-buckling team looks forward to an electronic cell or tissue scaffold, “A lot of the people that we talk to are enthusiastic about what you can do when you go from a passive scaffold to something that embeds full electronic functionality.”

The research is published in Science.

—E.K.

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