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XMC becomes YRST or Changjiang Storage

January 19th, 2017

As reported by Digitimes, a major enterprise in Wuhan, China has broken ground on the first of three mega-fabs to produce 3D-NAND chips. The final fab name-plate may ultimately read XMC or YMTC or YRST or possibly Changjiang Storage (not to be confused with GuangDong ChangJiang Storage Battery), but it is over half owned by the Chinese government’s Tsinghua Unigroup.

Total investment in XMC/YRST by Tsinghua Unigroup is reported by Digitimes to be US$24 billion. In 2015 Tsinghua Unigroup bid US$23 billion to buy Micron Technology Corp, but the company was not for sale.

In 2013 as reported at EETimes, the fab re-branded itself as XMC from the former Wuhan XinXin Semiconductor Manufacturing (WXIC). Dr. Simon Yang was CEO of WXIC/XMC from 2012 to last November when he resigned to become the CEO of Yangtze Memory Technologies Co. Ltd.

Two months later the new company is reportedly to be called Yangtze River Storage Technology (YRST), according to DIGITIMES. Meanwhile, Nikkei Asian Review reports that YRST is also known as Changjiang Storage.

High-Volume Manufacturing (HVM) in the first fab is planned for 2018, and the third fab on the campus is expected to bring 300k 300mm wafer-starts-per-month online by 2020. Rick Tsai the ex-CEO of Taiwan Semiconductor Manufacturing (TSMC) and Shih-Wei Sun the ex-CEO of United Microelectronics (UMC) have both reportedly joined Tsinghua Unigroup.


China to be 15% of World Fab Capacity by 2018

November 29th, 2016

Currently there are eight Chinese 300mm-diameter silicon IC fabs in operation as 2016 comes to a close. Chinese IC fab capacity now accounts for approximately 7% of worldwide 300mm capacity, as reported by VLSIresearch in a recent edition of its Critical Subsystems report ( This will expand rapidly, as ten are now under construction and two more have been announced. China’s 300mm fabs are located in ten cities.

“Total Chinese capacity is expected to be around 13 million by end 2018,” said John West of VLSI Research. Worldwide 300mm wafer fabrication capacity will exceed 85 million wafers per year in 2018, putting China in control of 15% of worldwide 300mm capacity in 2018. While new Chinese fabs have yet to prove they can produce leading edge silicon ICs with high yields, it should be only a matter of time before they prove they stand among the world’s great semiconductor production regions.

West recently presented a China market outlook for semiconductors, original equipment manufacturers (OEM), and critical subsystems at the recent Critical Materials Council (CMC) Seminar ( held in Shanghai. At the same event, representatives from Intel and TI discussed supply-chain dynamics in China, and Secretary General Ingrid Shi of the Integrated Circuit Materials Industry Technology Innovative Alliance (ICMITIA) presented on “The China Materials Supply Consortium and China’s 5 Year Technology Plan.”

The 2016 CMC Seminar also saw a presentation of China’s first semiconductor-grade 300mm silicon wafer supplier:  the recently unveiled Zing Semiconductor ( Founder and CEO Richard Chang, co-founder of SMIC, has assembled a team and funding to start creating wafers in the Pudong region of Shanghai. He showed a photo of his company’s first 300mm silicon boule at the event.

[DISCLOSURE:  Ed Korczynski is also Marketing Director for TECHCET CA, an advisor firm that administers the Critical Materials Council and CMC events.]


Reliable ICs from unreliable devices

November 10th, 2016

In an article published in the most recent issue of imec’s online magazine ( titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec) Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.


CSP Market Forecast – Strong

October 29th, 2016

Chip-Scale Packages (CSP) continue to be in strong demand for IC needing the smallest form-factors for applications including automotive, industrial applications to mobile phones and wearable electronics, according to leading market research firm TechSearch International. TechSearch’s latest CSP market forecast shows a 8% CAGR from 2015 to 2020, despite a slowing growth rate for smartphones.

One of the categories with the strongest growth is the quad flat no-lead (QFN) package with a CAGR of 8.6%. QFNs are a low-cost, low-profile package found in a wide range of products from automotive and power devices. An analysis of the Out-Sourced Assembly and Test (OSAT) market in China provides insight into expansion plans and market shares.

Fan-Out Wafer-Level Packages (FO-WLP) with many variations are now winning slots in many new mobile devices. New advanced packages such as JCAP’s FO-WLP are highlighted in the latest Advanced Packaging Update, along with the use of TSMC’s FO-WLP for Apple’s A10 application processor. The report also examines trends in stacked die CSPs, laminate-substrate CSPs, and package-on-package (PoP) with a market forecast for each. See:  http//


Dan Rose departs material realm

October 14th, 2016
Daniel J. Rose, Ph.D. November 7, 1937 – September 20, 2016 Daniel J. Rose, Ph.D.
November 7, 1937 – September 20, 2016

With sadness I post that Daniel J. Rose, Ph.D.—founder of Rose Associates—passed away on September 20, 2016, due to complications of Alzheimer’s disease. Dan Rose received a Ph.D. in materials engineering from the University of British Columbia, and subsequently spent five years managing packaging manufacturing operations at Fairchild Semiconductor. He worked with and become friends with industry luminaries such as Intel’s founder Robert Noyce, and National Semiconductor’s founder Charlie Sporck.

In February of 1970, he founded Rose Associates, which initially provided engineering and manufacturing support to the semiconductor industry, establishing factories in the US and assembly plants in the Far East. In 1977, Rose Associates began conducting market research in electronic materials. In January of 1985, Rose Associates began publishing the Electronic Materials Report (EMR) monthly newsletter, and In 1986 held its first annual Electronic Materials Conference.

Dan Tracy, Ph.D.— SEMI Senior Director, Industry Research & Statistics—was one of Rose’s associates who joined the trade organization in 2000 when it acquired Rose Associates’ business. Tracy wrote a wonderfully heartfelt remembrance as a LinkedIn Pulse article (


Fish-Scale Piezo Generators

September 26th, 2016

Piezoelectric generators are based on thin-films of structured materials that can convert pressure into electricity. Inorganic crystals such as aluminum-nitride (AlN) barium titanate (BT) and lead-zirconium-titanate (PZT) have long been explored as piezoelectric films for various applications. Now researchers Sujoy Kumar Ghosh and Dipankar Mandal at the Jadavpur University in Kolkata, India have shown that fish scales (FSC) can be used to build a flexible bio-piezoelectric nanogenerator (BPNG) capable of producing a maximum output power density of 1.14 μW/cm2 under repeated compressive normal stress of 0.17 MPa.

Fabrication of flexible (BPNG) from bio-waste fish-scale (FSC) a) photographs of the bio-waste raw FSC, and demineralised FSC, b) flexibility of the BPNG shown by human fingers, and c) schematic diagram of simple BPNG device structure. (Source: APL) Fabrication of flexible (BPNG) from bio-waste fish-scale (FSC) a) photographs of the bio-waste raw FSC, and demineralised FSC, b) flexibility of the BPNG shown by human fingers, and c) schematic diagram of simple BPNG device structure. (Source: APL)

As recently published in Applied Physics Letters with the title, “High-performance bio-piezoelectric nanogenerator made with fish scale,” the Figure shows that they started with the skin trimmings of Indian carp (Catla catla), that were acid washed and demineralized to extract collagen of nominal thickness ∼250 ± 10 μm, which is then sandwiched between 90nm thick sputtered gold electrodes, followed by lamination with polypropylene (PP) film ∼125 μm thick.
Energy harvesting is enabled by the self-assembled and ordered collagen nano-fibrils, which exhibit intrinsic piezoelectric strength of −5.0 pC/N.

…the most abundant piezoelectric biomaterial present in animal tissues such as skin, tendon, cartilage, bone, and even in human heart, is the type I collagen, which is a biocompatible and biodegradable polymer enabling fabrication of the flexible BPNG. The cost effective collagen source is the fish constituents such as skin, fins, maws, and swim bladder which are mainly treated as “bio waste” materials because different fish species are consumed daily in large quantities worldwide. The disposal of these bio-wastes causes an increasing environmental pollution. The recycling of the fish by-products into the BPNG via one step process is a promising solution for the development of value-added products and also to reduce the e-waste elements.

The BPNG is able to convert several forms of mechanical energy into electricity. For example, gentle press-hold-release motions of a single human finger (∼3.75 kPa and strain rate of 0.017% s−1) results in ∼680 mV output voltage with perfect switching of polarity. It scavenges mechanical energy from high level vibration from machines and also from very low level vibration, arises from sound (∼0.2–2.0 Pa) and wind motions (∼3.6 m/s). When slapped repeatedly by a human hand (∼ 0.17 MPa with 0.77% s−1 strain rate) this BPNG generates a rectified open circuit voltage (Voc) of 4 V, and multiple layers can be stacked to multiply the Voc. Due to high sensitivity, good stability, and efficient piezoelectric power-generating performance, these BPNG may open a new era in sustainable energy harvesting.


Patterning with Films and Chemicals

August 24th, 2016

Somewhere around 40nm is the limit on the smallest half-pitch feature that can be formed with a single-exposure of 193-nm wavelength laser light using water immersion (193i) lithography. While multiple-patterning (MP) is needed to achieve tighter half-pitches, smaller features at the same pitch can be formed using technology extensions of 193i. “Chemistry is key player in lithography process,” is the title of a short video presentation by Dow Electronic Materials corporate fellow Peter Trefonas now hosted on the SPIE website (DOI: 10.1117/2.201608.02).

Trefonas as been working on chemistries for lithography for decades, including photoresists, antireflectant coatings, underlayers, developers, ancillary products, and environmentally safer green products. He is an inventor on 61 US patents, has over 25 additional published active U.S. patent applications, is an author of 99 journal and technical publications, and is a recipient of the 2014 ACS Heroes of Chemistry Award and the 2013 SPIE C. Grant Willson Best Paper Award in Patterning Materials and Processes. Now a Senior Member of SPIE, he earned his Ph.D. in inorganic chemistry with Prof. Robert West at the University of Wisconsin-Madison in 1985.

Trefonas explains how traditional Chemically-Amplified (CA) resists are engineered with Photo-Acid Generators (PAG) to balance the properties for advanced lithography. However, in recent years the ~40-nm half-pitch resolution limit has been extended with chemistries to shrink contact holes, smooth line-width roughness, and to do frequency-multiplication using Directed Self-Assembly (DSA). All of these resolution extension technologies rely upon chemistry to create the final desired pattern fidelity.


ASM’s Haukka ALD Award

August 1st, 2016

Dr. Suvi Haukka, executive scientist at ASM International, located in Finland, was awarded the ALD Innovation prize at the ALD 2016 Ireland conference (Figure), as chosen by the conference chairs. Haukka has had a lifetime career in Atomic Layer Deposition (ALD), starting at Microchemistry Ltd. with ALD pioneer Dr. Tuomo Suntola in 1990, and now holding over 100 patents.

Conference co-chairs Simon Elliott, Tyndall National Institute of Ireland (left) and Jonas Sundqvist, Lund University of Sweden (right) acknowledge Suvi Haukka from ASM International N.V. (center) as recipient of the "ALD Innovation Prize" at the 16th International Conference on Atomic Layer Deposition (ALD 2016) held last month in Dublin, Ireland. (Source: ALD 2016) Conference co-chairs Simon Elliott, Tyndall National Institute of Ireland (left) and Jonas Sundqvist, Lund University of Sweden (right) acknowledge Suvi Haukka from ASM International N.V. (center) as recipient of the “ALD Innovation Prize” at the 16th International Conference on Atomic Layer Deposition (ALD 2016) held last month in Dublin, Ireland. (Source: ALD 2016)

Since ASM bought Microchemistry in 1999, Haukka has worked on the manufacturability of ALD processes for the semiconductor industry. Today, ALD technology is essential for the high-volume manufacturing (HVM) of advanced ICs, with growing demand for the fabrication of nanoscale 3D devices such as finFETs and 3D-NAND Flash cells.

As reported by Riikka Puurunen in his ALD History Blog, Haukka joins a short list of technology luminaries who have been previous recipients of the prize:
* 2011 Roy Gordon (Harvard University),
* 2012 Markku Leskelä (University of Helsinki),
* 2013 Steven George (University of Colorado),
* 2014 Hyeongtag Jeon (Hanyang University), and
* 2015 Gregory Parsons (North Carolina State University).

More on the ALD 2016 conference can be read in the travel report blog.

[DISCLAIMER:  Ed Korczynski and Jonas Sundqvist also work for TECHCET CA, and were co-chairs of the 2016 Critical Materials Conference.]


The Last Technology Roadmap

July 25th, 2016

After many delays, the last ever International Technology Roadmap for Semiconductors (ITRS) has been published. Now that there are just a few companies remaining in the world developing new fab technologies in each of the CMOS logic and memory spaces, each leading-edge company has a secret internal roadmap and little motivation to compare directions within fiercely competitive  commercial markets. Solid State Technology Chief Editor Pete Singer covered these developments in his blog post early last year.

Rachael Courtland at IEEE Spectrum provides a great overview of the topic and interviews many of the key contributors to this last global effort. The article provides a nice graph to show how the previously predicted (in the just-prior ITRS 2013 edition) continued physical gate length reduction of CMOS transistors is now expected to stop in 2020. Henceforth, 3D stacking of transistors—perhaps built with arrays of Gate-All-Around NanoWires (GAA-NW)—will be the only way to get more density in circuitry but it will come with proportionally increasing cost.

As Gary Patton, CTO and SVP of Worldwide R&D for GlobalFoundries, mentioned during the 2016 Imec Technology Forum in Brussells, “We will continue to provide value to our customers to be able to create new products. We’re going to innovate to add value other than simple scaling.”

The 17 International Technology Working Groups (ITWGs) were replaced in 2015 by 7 Focus Teams in the last ITRS:  System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectivity, More Moore, Beyond CMOS and Factory Integration. The final reports from each Focus Team are available for free download from Dropbox.

The IEEE Rebooting Computing Initiative, Standards Association, and the Computer Society announced a new International Roadmap for Devices and Systems (IRDS) on 4th of May this year. Paolo Gargini is leading this work that began with the partnership between the IEEE RC initiative and the ITRS, with aspiration to build “a comprehensive end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software.”

In parallel to the IRDS efforts, the Heterogeneous Integration Roadmap activities will continue as sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI  and the IEEE Electron Devices Society (EDS). Bill Bottoms is leading this collaboration with other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.


Broadening Scope of SEMICON

June 30th, 2016

Once upon a time, SEMICONs were essentially just for semiconductor manufacturing business and technology, and predominantly CMOS ICs. Back when we followed public roadmaps for technology to maintain the cadence of new manufacturing nodes in support of Moore’s Law, it was sufficient to focus on faster transistors connected with tighter wires. Now in an era that is at least partially “More-than-Moore”—as we like to refer to heterogeneous integration of non-CMOS technologies into commercial ICs—SEMICON West 2016 will focus on technologies beyond silicon CMOS such as MEMS and flexible organic semiconductors.

Alissa Fitzgerald, founder and managing member of AM Fitzgerald & Associates, will present on some of these themes Wednesday afternoon during the “What’s Next in MEMS and Sensors: Innovations to Drive the Next Generation of Growth” session (Track 2) of SEMICON’s Advanced Manufacturing Forum. Much of that growth is expected to be in sensors, microprocessors, ultra-low-power supplies, and communications chips to support the Internet of Things (IoT) connected by high-speed 5G data networks.

Flexible/Hybrid Electronics Forum at SEMICON West this year includes two full days of excellent presentations on new technologies that include thinned device processing, device/sensor integrated printing and packaging, and reliability testing and modeling. The following is the full list of forums this year:

  • Advanced Manufacturing,
  • Advanced Packaging,
  • Extended Supply-Chain,
  • Flexible/Hybrid Electronics,
  • Silicon Innovation,
  • Sustainable Manufacturing,
  • Test, and
  • World of IoT.

Partner programs include focused forums discussing trends in technology, markets, and the business of commercial IC fabrication. The industry’s default center of “More Moore” R&D is now imec in Belgium, and invited attendees of the imec technology forum (ITF) in San Francisco happening on July 11th the day before the start of SEMICON West will learn about the latest results in CMOS device shrinking from finFETs to nanowires. The next evening, French R&D and pilot manufacturing center CEA-Leti will lead a workshop detailing how to partner with the organization to bring sensor-based “More-than-Moore” technologies to market. Thursday morning will feature the Entegris Yield Breakfast Forum discussing the need for new materials handling solutions due to “Yield Enhancement Challenges in Today’s Memory IC Production.”

As the official event website summarizes:  We’ve deepened our reach across the full electronics manufacturing supply chain to connect you with more key players — including major industry leaders like Cisco, Samsung, Intel, Audi, Micron, and more. New players, demand generators, systems integrators, and emerging industry segments — all connecting in one place. Keynote presentations will be provided by Cisco Systems, Kateeva, and Oracle.


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