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Omhi kept us Ultra-Clean

April 28th, 2016

OhmiSadly, I just recently learned from the UCPSS 2016 website that Ohmi-sensei—Professor Doctor Tadahiro Ohmi—passed away in Sendai on 21 February 2016. As the guru of ultra-clean technology, he established the global Ultra Clean Society in 1988, founded the International Symposium of Semiconductor Manufacturing (ISSM) in 1992, served as program committee member of the UCPSS between 1992 and 2006, and was an IEEE Fellow. Ohmi was a Professor of New Industry Creation Hatchery Center at Tohoku University, after serving as a Professor at the Electronic Engineering Department, School of Engineering at Tohoku U.

Ohmi was most famous for asserting that IC manufacturing yield could be 100% if only every tool and tube in the fab were built with ultra-clean surfaces, and if all direct-materials and fluids flowing in the fab were ultra-clean. In the 1980s when IC designs and fab processes were relatively simple and HVM yields were in the 30-60% range, huge improvements came from removing “random” particles from dirty surfaces. Soon enough by the mid-1990s  “clean enough” was found to be the pragmatic response to the experience of diminishing returns after yields were in the 90% range. Most famously for posterity, in 1993 Ohmi edited “Ultraclean Technology Handbook: Ultrapure Water, Vol.1”.

I first met him when UltraClean Technology, Inc. (UCTT) was founded in California in 1996 to weld ultra-clean steel from parent company Mitsubishi in a Class-1 cleanroom, and he was the genius bringing his vision of a better world to the rest of us. However, eventually UCTT separated from Mitsubishi and added Class-100 and Class-1000 assembly areas to provide “clean enough” technology…heresy to the Guru of ultra-clean; I never met him again when I worked for the company as a product manager in 2004.

As covered by EETimes in 2002, Ohmi could clearly see that something new was going to be needed in fab technology, but his vision for a way forward was an unrealizable dream:

Ohmi said his comprehensive process, from design through chip making, would create devices with 10 times better performance than today’s chips. At the same time, he said, it would squeeze design and production time to 1/40, clean room space to 1/5 and production cost to 1/10 of what’s now required.

Throughout his career he continued to look for breakthroughs to enable new generations of semiconductor manufacturing technology, recently supervising a project to develop a “next-generation flat panel display.”

An extraordinarily prolific inventor, his name is on an astonishing 592 issued US patents, based on 795 US applications filed, the most recent on December 21st of last year.

—E.K.

Andy Grove blessed us all

March 22nd, 2016

andrew-grove_1-150x150Andy Grove, the man who codified the commercial IC industry dynamic as “Only the Paranoid Survive” died yesterday at the age of 79. His instinctive paranoia derived from his tragic experiences while growing up in Hungary, as referenced by Wikipedia in the prolog to “Swimming Across: a Memoir”:

By the time I was twenty, I had lived through a Hungarian Fascist dictatorship, German military occupation, the Nazis’ “Final Solution,” the siege of Budapest by the Soviet Red Army, a period of chaotic democracy in the years immediately after the war, a variety of repressive Communist regimes, and a popular uprising that was put down at gunpoint. . . [where] many young people were killed; countless others were interned. Some two hundred thousand Hungarians escaped to the West. I was one of them.

Grove was responsible for guiding Intel in the 1980s through the amazingly risky yet ultimately wildly successful strategy of abandoning memory chip production as part of a diversified product portfolio to “bet the company” on microprocessors. In the September 1997 issue of Solid State Technology, I wrote an article titled “DRAM fab strategies in Asia” that summarizes why and how US companies like Intel strategically abandoned DRAM production:

In the 1960s, US companies created the IC manufacturing industry and enjoyed virtually unchallenged world dominance through the 1970s. Japanese IC companies, though at first the junior companies in low-margin and foundry partnerships, rose to challenge the more senior US companies in the 1980s. By the latter half of the 1980s, Japan effectively owned the DRAM business and Japan`s outstanding success in IC production can be directly traced to early US manufacturing partnerships. One strategy played out by US companies with portfolios of memory chip designs was outsourcing of DRAM production to Korean companies. In so doing, US companies committed their futures to non-DRAM products such as microprocessors, DSPs, and ASICs.

Few executives have sufficient vision while leading a work-force with sufficient discipline to be able to re-invent a company in such a way. The capital equipment investments needed to create a leading-edge IC fab have always been daunting, and as Intel employee #3 who had led engineering Grove was able to see a way to leverage strategic R&D to ensure that leading-edge IC product functionalities would pull in sufficient demand to keep the fabs full. Not only did the fabs stay full, but the x86 microprocessor profit margins allowed Intel to grow to annual sales of $25 billion by the time he was replaced as CEO by Craig Barrett in 1998.

The San Jose Mercury News and EETimes have published wonderful additional remembrances of his life. Andy Grove blessed our industry by being a living example of engineering excellence and legit leadership.

—E.K.

SAQP Specs for 7nm finFETs

March 11th, 2016

As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

  • 7.0nm Critical Dimension (CD) after etch,
  • 0.5nm (3sigma) CD uniformity (CDU), and
  • <1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Litho becomes Patterning

February 25th, 2016

Once upon a time, lithographic (litho) processes were all that IC fabs needed to transfer the design-intent into silicon chips. Over the last 10-15 years, however, IC device structural features have continued to shrink below half the wavelength of the laser light used in litho tools, such that additional process steps are needed to form the desired features. Self-Aligned Double Patterning (SADP) schemes use precise coatings deposited as “spacers” on the sidewalls of mandrels made from developed photoresist or a sacrificial material at a given pitch, such that after selective mandrel etching the spacers pitch-split. SADP has been used in HVM IC fabs for many years now. Self-Aligned Quadruple Pattering (SAQP) has reportedly been deployed in a memory IC fab, too.

An excellent overview of the patterning complexities of SAQP was provided by Sophie Thibaut of TEL in a presentation at SPIE-AL on “SAQP integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications.” Use of a spacer-on-spacer process flow—enabled by clever combinations of SiO2 and TiO2 spacers deposited by Atomic Layer Deposition (ALD)—requires the following unit-process steps:
1 193i litho,
2 ALD spacers,
2 wet etches, and
4 plasma etches.

Since non-litho processes dominate the transfer of design-intent to silicon, from first principles we should consider such integrated flows as “patterning.” Etch selectivity to remove one material while leaving another, and deposition dependent on underlying materials determine much of the pattern fidelity. Such process flows are new to IC fabs, but have been used for decades in the manufacturing of Micro-Electrical Mechanical Systems (MEMS), though generally on a patterning length scale of microns instead of the nanometers needed for advanced ICs. R&D labs today are even experimenting with Self-Aligned Octuple Patterning (SAOP), and based on the legacy of MEMS processing it certainly could be done.

—E.K.

3D XPoint uses PCM Material in ReRAM Device

January 31st, 2016

IM Flash pre-announced “3D XPoint”(TM) memory for release later this year, and lack of details has led to widespread confusion regarding what it is. EETimes has reported that, “Chalcogenide material and an Ovonyx switch are magic parts of this technology with the original work starting back in the 1960’s,” said Guy Blalock, co-CEO of IM Flash at the 2016 Industry Strategy Symposium hosted by the SEMI trade group. However, contradicting industry terminology conventions, in another article EETimes reported that a spokesperson for Intel has said that, “3D XPoint should not be described as ReRAM.”
First promoted by the master of materials solutions-looking-for-problems Sanford Ovshinsky under the name “Ovonic” trademark, chalcogenide materials form glassy structures with meta-stable properties. With proper application of heat and electrical current, chalcogenides can be made to switch between low-resistivity crystalline and high-resistivity amorphous phases to create Phase-Change Memory (PCM) arrays in silicon circuit architectures. Chalcogenides can also function as the matrix for the diffusion of silver ions in a cross-point device architecture to create a digital “Resistive RAM” (or “ReRAM” or “RRAM”), or create an analog memristor for neuromorphic applications as explored by Prof. Kris Campbell of Boise State in collaboration with Knowm.

Hitachi and Renesas Technology developed Phase-Change Memory (PCM) cell technology employing Ta2O5 interfacial layer to enable low-power operation. (Source: Hitachi) Hitachi and Renesas Technology developed Phase-Change Memory (PCM) cell technology employing Ta2O5 interfacial layer to enable low-power operation. (Source: Hitachi)

The Figure shows a schematic cross-section of a typical PCM cell. From a scientific perspective, we could say that any memory cell that relies upon a change in material phase to encode digital data should be termed a PCM. However, due to the history of this specific type of PCM device being the only architecture explored for decades (and commercialized for limited niche sub-markets), and due to the fundamentally different circuit architectures, it is reasonable to categorically deny that any cross-point device is a “PCM.”
However, any cross-point memory device based on a resistance change has to be a ReRAM regardless of the switching phenomenon:  phase-change, filament-growth, ion-diffusion, etc. So we could say that this new chip uses PCM material in a ReRAM device.
—E.K.

Controlling Polymers to Tune TFTs

January 16th, 2016

Thin-film transistors (TFT) created using only additive process steps could create new low-cost ICs with functionalities beyond silicon, but only if we understand how to control structures at the molecular level. Thin films of conjugated polymers such as poly(3-hexylthiophene) (P3HT) can provide useful conductivity when the electron mobilities are controlled within as well as between molecules. In producing TFTs using such organic macromolecules, we must rigorously control the deposition and annealing processes so that the right molecules line up in the right order.
Peter F. Green, Professor of Chemical Engineering, Macromolecular Science and Engineering at the University of Michigan, and his team fabricated ~55 nm thin films of P3HT using resonant-infrared matrix-assisted pulsed laser evaporation (RIR-MAPLE), as well as conventional spin-casting. The films produced by MAPLE show a higher degree of structural disorder, with localized trap sites that reduce mobility out-of-plane by an order of magnitude compared to spin-cast films.

(Source: Peter Green, University of Michigan) (Source: Peter Green, University of Michigan)

The Figure shows that despite the disorder of MAPLE-deposited P3HT, enhanced carrier density at the dielectric interface allows TFTs to exhibit similar in-plane mobilities to those built using conventionally spin-coated films. TFTs were top-contact, bottom-gate designs on 300nm thermal oxide on highly doped silicon. In-plane carrier mobilities of MAPLE-deposited versus spin-cast films were 8.3 versus 5.5 (×10 -3 cm2/V/s). In principle, the ability to independently control in- and out-of-plane mobilities allows for the fine tuning of TFT parameters for different applications.
—E.K.

CMOS-Photonic Integration Thermally Sensitive

December 31st, 2015

As published in the journal Nature, CMOS transistors have been integrated with optical-resonator circuits using complex on-chip sensors and heaters to maintain temperature to within 1°C. While lacking the laser-source, these otherwise-fully-integrated solutions demonstrate both the capability as well as the limitation of trying to integrate electronics and photonics on a single-chip. The Figure shows a simplified schematic cross-section of the device.

Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. The minimum separation between transistors and waveguides is <1 μm, set only by the distance at which evanescent light from the waveguide begins to interact with the structures of the transistor. Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. (Source: Nature)

Lead author Chen Sun—affiliated with UC Berkeley and MIT, as well as with commercial enterprise Ayar Labs, Inc.—developed the thermal tuning circuitry, designed the memory bank, implemented the ‘glue-logic’ between various electronic components, and performed top-level assembly of electronics and photonics. The main limitation is the temperature control, since deviation by more than 1°C results in loss of coupling that otherwise provides for P2M/M2P transceivers:

* Waveguide Loss – 4.3 dB/cm,
* Tx and Rx Data Rate – 2.5 Gb/s,
* Tx Power – 0.02 pJ/bit,
* Rx Power – 0.50 pJ/bit, and
* Ring Tuning Control Power – 0.19 pJ/bit, so
* Total power consumption = 0.71 pJ/bit.

The Register reports that this prototype has a bandwidth density of 300 Gb/s per square millimetre, and needs 1.3W to shift a Tb/s straight from the die to off-chip memory. A single chip integrates >70 million transistors and 850 photonic components to provide microprocessor logic, memory, and interconnect functions.

—E.K.

Apple Fab Speculation

December 18th, 2015

Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small as 90nm device features. Formerly owned and operated by Maxim, the US$18.2M purchase reportedly includes nearly 200 working fab tools. Some people outside the industry have speculated that Apple might use this fab to do R&D on the A10 or other advanced logic chips, but this old tool-set is completely incapable of working on <45nm device features so it’s useless for logic R&D.

As reported at EETimes, this old fab could be used for the R&D of “mixed-signal devices, MEMS and image sensors and for work on packaging.” Those who know do not speak, while those who speak do not know…I do not know so I’m free to join the public speculation. Mixed-signal and MEMS processing would require major re-tooling of the line, but this 15-20 year-old tool-set is nearly turn-key for wafer-level packaging (WLP). With minimal re-tooling, this line could produce through-silicon vias (TSV) or through-mold vias (TMV) as part of Fan-Out WLP (FO-WLP).

Our friends at ChipWorks have published a detailed tear-down analysis of the System-in-Package (SiP) used in the first generation Apple Watch; it contains 30 ICs and many discretes connected by a 4-layer printed circuit board (PCB). Significant power and performance improvements in mobile devices derive from stacking chips in such dense packages, and even greater improvements can found in replacing the PCB with a silicon interposer. With Apple pushing the limits on integrating new functionalities into all manner of mobile devices, it would be strategic to invest in WLP R&D in support of application-specific SiP design.

—E.K.

MPU Cores and Legal Boors

November 30th, 2015

As reported by The Register, AMD has been sued by a customer who claims that the number of Bulldozer cores in some Opteron and FX microprocessor (MPU) chips are fewer than advertised. The claim is based on the argument that a “real” MPU core has it’s own floating point unit for calculations, and that consumers were misled by product claims. I am not a lawyer (IANAL) and have no connections to either side in this case, but AMD’s website (http://www.amd.com/en-us/products/processors/desktop/fx#) now clearly indicates that cores share a Floating Point (FP) scheduler.

The Figure shows that the confusion is due to the design of the Bulldozer microarchitecture wherein a pair of cores is called a module, and each pair shares a branch prediction engine, an instruction fetch and decode stage, a floating-point math unit, a cache controller, a 64K L1 instruction cache, a microcode ROM, and a 2MB L2 cache. The lawsuit claims, “Because AMD did not convey accurate specifications, tens of thousands of consumers have been misled into buying Bulldozer CPUs that do not conform to what AMD advertised, and cannot perform the way a true eight core CPU would (i.e., perform eight calculations simultaneously).”

AMD_Bulldozer_floorplan
This is analogous to someone buying a car with a V8 internal combustion engine, and then suing the manufacturer because there are only 4 fuel injectors and not all cylinders fire simultaneously. The claim that “true” multi-cores must be capable of functioning simultaneously is like claiming that “true” multi-cylinder engines must be capable of all cylinders firing simultaneously. AMD has officially responded with the statement that, “We believe our marketing accurately reflects the capabilities of the Bulldozer architecture which, when implemented in an 8-core AMD FX processor, is capable of running eight instructions concurrently.” There seems to be little legal difference between “simultaneously” and “concurrently” but IANAL.

Sure, there’s a technical difference and likely a slight performance benefit to direct fuel injection into each cylinder, but raw performance is only one aspect of the design trade-offs between performance and cost and reliability. Sharing 1 fuel injector between 2 cylinders often provides an optimum of performance/cost/reliability in internal combustion engines. Sharing 1 FPU between 2 logic cores seemingly provides an optimum of performance/cost/reliability in CPUs.

—E.K.

Thermoplastically Deformable Electronic Circuits

November 27th, 2015

Philips is testing a technology developed by imec and CMST (imec’s associated lab at Ghent University) to create low-cost 3D LED packages. As shown at last month’s International Microelectronics Assembly and Packaging Society (IMAPS 2015) meeting, these thermoplastically deformable electronic circuits are already being integrated by Philips into LED lamp carriers, a downlight luminaire, and a omnidirectional light source.

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec) Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

The technology is based on meander-shaped interconnects, which are patterned using  standard printed circuit board (PCB) production equipment and then sandwiched between 2D thermoplastic polymer (e.g. polycarbonate) sheets. The Figure shows one example in final form after vacuum thermoforming into a 40mm half-sphere mold.
This is a glorious example of “elegant engineering” where a clever combination of materials and processes has been integrated with highly desirable characteristics:  low tooling cost, low direct material cost, easily scalable from lab to fab, low product weight, and high product resilience. This seems to represent almost a new industrial product category that combines a “package” and a PCB.

 

—E.K.

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