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MEMS Mirrors for LIDAR

April 24th, 2017

Clever integration of new microelectronic/nanoelectronic technologies will continue to provide increased functionalities for modern products. Light Imaging, Detection, And Ranging (LIDAR) technology uses lasers to see though fog and darkness, and smaller less expensive LIDAR systems are needed for autonomous driving applications now being developed by dozens of major companies around the world. A significant step in the right direction has been taken by the US government’s Lawrence Livermore National Laboratory (LLNL) after working with AMFitzgerald on a MEMS mirror Light-field Directing Array (LDA) prototype.

In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.) In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.)

For the past several years, AMFitzgerald has been developing the fabrication process for a novel MEMS micro-mirror array designed by Dr. Robert Panas’s research group at LLNL, as shown in this video. The technology has been developed specifically to serve LIDAR, laser communications, and other demanding applications where existing MEMS mirror array technologies are insufficient. The novel design offers exceptional speed and tilt range, with three axes (tip-tilt-piston), feedback control, and 99% fill factor. The technology is available for license from the LLNL Industrial Partnerships Office.

At the upcoming MEMS & Sensors Technical Congress, on May 11, Dr. Carolyn D. White will present a case study on how she developed this complex prototype and leveraged AMFitzgerald’s ecosystem of partners to integrate specialty processes. Dr. Alissa Fitzgerald—founder and principle of AMFitzgerald leading the development of innovative MEMS and sensor solutions for specialty applications—will be giving a keynote address on “Next Generation MEMS Manufacturing” at 9:10am May 17 during The ConFab. Dr. Fitzgerald has unparalleled expertise in how to best design MEMS for different fab lines, and is a speaker not to be missed.

—E.K.

Moore’s Law Smells Funny

April 1st, 2017

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” – Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct:  “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.

—E.K.

EUVL Masks may need to be Tool-Specific

March 7th, 2017

Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).

—E.K.

Flagello to receive Zernike Award at SPIE Advanced Lithography

February 24th, 2017

Flagello-DonisDonis Flagello, president, CEO, and COO of Nikon Research Corporation of America (NRCA), will be presented with the 2017 Frits Zernike Award for Microlithography on Monday 27 February during SPIE Advanced Lithography in San Jose, California. The award, presented annually for outstanding accomplishments in microlithography technology, recognizes Flagello’s leading role in understanding and improving image formation in optical lithography for semiconductor manufacturing.

A prominent member of the industry since the early 1980s and a longtime SPIE Fellow, Flagello has primarily focused on the rigorous application of physics to lithography modeling and problem solving. Early in his career, while at IBM T.J. Watson Research Center, he developed the first practical test for measuring flare in optical lithography tools and made major contributions to high numerical aperture (NA) modeling including vector and polarization effects, and radiometric correction. At ASML he played an important role in providing analysis of aberrations for new systems and high-NA imaging effects due to polarization.

Another notable aspect of his career, Flagello’s presentations at lithography conferences and papers in various journals have inspired a better understanding of optics and resist behavior and helped drive optical lithography forward, colleagues said. “His presentations are known for their combination of humor with a deep understanding of the complex interactions between physical optics and lithographic process technology,” said David Williamson, an NRCA Fellow and previous Frits Zernike Award winner. “His combined theoretical and practical production experience and knowledge are rare in this field.”

—E.K.

Photoelectric measure of atomically thin stacks

February 17th, 2017

A team led by researchers at the University of Warwick have discovered a breakthrough in how to measure the electronic structures of stacked 2D semiconductors using the photoelectric (PE) effect. Materials scientists around the world have been investigating various heterostructures to create different 2D materials, and stacking different combinations of 2D materials creates new materials with new properties.

The new PE method measures the electronic properties of each layer in a stack, allowing researchers to establish the optimal structure for the fastest, most efficient transfer of electrical energy. “It is extremely exciting to be able to see, for the first time, how interactions between atomically thin layers change their electronic structure,” says Neil Wilson, who helped to develop the method. Wilson is from the physics department at the University of Warwick.

Wilson formulated the technique in collaboration with colleagues at the University of Warwick, University of Cambridge, University of Washington, and the Elettra Light Source in Italy. The team reported their findings in Science Advances (DOI: 10.1126/sciadv.1601832).

—E.K.

XMC becomes YRST or Changjiang Storage

January 19th, 2017

As reported by Digitimes, a major enterprise in Wuhan, China has broken ground on the first of three mega-fabs to produce 3D-NAND chips. The final fab name-plate may ultimately read XMC or YMTC or YRST or possibly Changjiang Storage (not to be confused with GuangDong ChangJiang Storage Battery), but it is over half owned by the Chinese government’s Tsinghua Unigroup.

Total investment in XMC/YRST by Tsinghua Unigroup is reported by Digitimes to be US$24 billion. In 2015 Tsinghua Unigroup bid US$23 billion to buy Micron Technology Corp, but the company was not for sale.

In 2013 as reported at EETimes, the fab re-branded itself as XMC from the former Wuhan XinXin Semiconductor Manufacturing (WXIC). Dr. Simon Yang was CEO of WXIC/XMC from 2012 to last November when he resigned to become the CEO of Yangtze Memory Technologies Co. Ltd.

Two months later the new company is reportedly to be called Yangtze River Storage Technology (YRST), according to DIGITIMES. Meanwhile, Nikkei Asian Review reports that YRST is also known as Changjiang Storage.

High-Volume Manufacturing (HVM) in the first fab is planned for 2018, and the third fab on the campus is expected to bring 300k 300mm wafer-starts-per-month online by 2020. Rick Tsai the ex-CEO of Taiwan Semiconductor Manufacturing (TSMC) and Shih-Wei Sun the ex-CEO of United Microelectronics (UMC) have both reportedly joined Tsinghua Unigroup.

—E.K.

China to be 15% of World Fab Capacity by 2018

November 29th, 2016

Currently there are eight Chinese 300mm-diameter silicon IC fabs in operation as 2016 comes to a close. Chinese IC fab capacity now accounts for approximately 7% of worldwide 300mm capacity, as reported by VLSIresearch in a recent edition of its Critical Subsystems report (https://www.vlsiresearch.com/public/csubs/). This will expand rapidly, as ten are now under construction and two more have been announced. China’s 300mm fabs are located in ten cities.

“Total Chinese capacity is expected to be around 13 million by end 2018,” said John West of VLSI Research. Worldwide 300mm wafer fabrication capacity will exceed 85 million wafers per year in 2018, putting China in control of 15% of worldwide 300mm capacity in 2018. While new Chinese fabs have yet to prove they can produce leading edge silicon ICs with high yields, it should be only a matter of time before they prove they stand among the world’s great semiconductor production regions.

West recently presented a China market outlook for semiconductors, original equipment manufacturers (OEM), and critical subsystems at the recent Critical Materials Council (CMC) Seminar (http:cmcfabs.org/seminars) held in Shanghai. At the same event, representatives from Intel and TI discussed supply-chain dynamics in China, and Secretary General Ingrid Shi of the Integrated Circuit Materials Industry Technology Innovative Alliance (ICMITIA) presented on “The China Materials Supply Consortium and China’s 5 Year Technology Plan.”

The 2016 CMC Seminar also saw a presentation of China’s first semiconductor-grade 300mm silicon wafer supplier:  the recently unveiled Zing Semiconductor (www.zingsemi.com). Founder and CEO Richard Chang, co-founder of SMIC, has assembled a team and funding to start creating wafers in the Pudong region of Shanghai. He showed a photo of his company’s first 300mm silicon boule at the event.

[DISCLOSURE:  Ed Korczynski is also Marketing Director for TECHCET CA, an advisor firm that administers the Critical Materials Council and CMC events.]

—E.K.

Reliable ICs from unreliable devices

November 10th, 2016

In an article published in the most recent issue of imec’s online magazine (http://magazine.imec.be/) titled “Chips must learn how to feel pain and how to cure themselves,” researchers Francky Chatthoor and Guido Groeseneken discuss how to build reliable “5nm-node” ICs out of inherently unreliable transistors. Variability in “zero time” and “over time” performance of individual transistors cannot be controlled below the “7nm-node” using traditional guard-banding in IC design.

“Maybe it means the end of the guard-band approach, but certainly not the end of scaling,” says Groeseneken in the article. “In our research group we measure and tried to understand reliability issues in scaled devices. In the 40nm technology, it is still possible to cope with the reliability issues of the devices and make a good system. But at 7nm, the unreliability of the devices risks to affect the whole system. And conventional design techniques can’t stop this from happening. New design paradigms are therefore urgently needed.” These researchers predict that industry will have to manufacture self-healing chips by the year 2025.

Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec) Self-healing chips could use the workload variation of the system for their benefit. Based on a deterministic predictor of the future, future slack is determined and used to compensate for the delay error and mitigate at peak load. (Source: imec)

The ultimate goal of imec and its academic partners is to develop a fully proactive parametric reliability mitigation technique with distributed monitors, a control system and actuators, fully preventing the consequence of delay faults and potentially also of functional faults. Said Catthour, “the secret to the solution lies in the work load variation of the system. Based on a deterministic predictor of the future, you determine future slack and use this to compensate for the delay error at peak load. Based on this info on the future, you change the scheduling order and the assignment of operations.” The Figure shows how self-healing chips can use future slack to compensate for delay error and mitigate at peak load.

—E.K.

CSP Market Forecast – Strong

October 29th, 2016

Chip-Scale Packages (CSP) continue to be in strong demand for IC needing the smallest form-factors for applications including automotive, industrial applications to mobile phones and wearable electronics, according to leading market research firm TechSearch International. TechSearch’s latest CSP market forecast shows a 8% CAGR from 2015 to 2020, despite a slowing growth rate for smartphones.

One of the categories with the strongest growth is the quad flat no-lead (QFN) package with a CAGR of 8.6%. QFNs are a low-cost, low-profile package found in a wide range of products from automotive and power devices. An analysis of the Out-Sourced Assembly and Test (OSAT) market in China provides insight into expansion plans and market shares.

Fan-Out Wafer-Level Packages (FO-WLP) with many variations are now winning slots in many new mobile devices. New advanced packages such as JCAP’s FO-WLP are highlighted in the latest Advanced Packaging Update, along with the use of TSMC’s FO-WLP for Apple’s A10 application processor. The report also examines trends in stacked die CSPs, laminate-substrate CSPs, and package-on-package (PoP) with a market forecast for each. See:  http//www.techsearchinc.com.

—E.K.

Dan Rose departs material realm

October 14th, 2016
Daniel J. Rose, Ph.D. November 7, 1937 – September 20, 2016 Daniel J. Rose, Ph.D.
November 7, 1937 – September 20, 2016

With sadness I post that Daniel J. Rose, Ph.D.—founder of Rose Associates—passed away on September 20, 2016, due to complications of Alzheimer’s disease. Dan Rose received a Ph.D. in materials engineering from the University of British Columbia, and subsequently spent five years managing packaging manufacturing operations at Fairchild Semiconductor. He worked with and become friends with industry luminaries such as Intel’s founder Robert Noyce, and National Semiconductor’s founder Charlie Sporck.

In February of 1970, he founded Rose Associates, which initially provided engineering and manufacturing support to the semiconductor industry, establishing factories in the US and assembly plants in the Far East. In 1977, Rose Associates began conducting market research in electronic materials. In January of 1985, Rose Associates began publishing the Electronic Materials Report (EMR) monthly newsletter, and In 1986 held its first annual Electronic Materials Conference.

Dan Tracy, Ph.D.— SEMI Senior Director, Industry Research & Statistics—was one of Rose’s associates who joined the trade organization in 2000 when it acquired Rose Associates’ business. Tracy wrote a wonderfully heartfelt remembrance as a LinkedIn Pulse article (https://www.linkedin.com/pulse/dr-daniel-j-rose-phd-dan-tracy?trk=hb_ntf_MEGAPHONE_ARTICLE_POST).

—E.K.

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