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Thermoplastically Deformable Electronic Circuits

November 27th, 2015

Philips is testing a technology developed by imec and CMST (imec’s associated lab at Ghent University) to create low-cost 3D LED packages. As shown at last month’s International Microelectronics Assembly and Packaging Society (IMAPS 2015) meeting, these thermoplastically deformable electronic circuits are already being integrated by Philips into LED lamp carriers, a downlight luminaire, and a omnidirectional light source.

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec) Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

The technology is based on meander-shaped interconnects, which are patterned using  standard printed circuit board (PCB) production equipment and then sandwiched between 2D thermoplastic polymer (e.g. polycarbonate) sheets. The Figure shows one example in final form after vacuum thermoforming into a 40mm half-sphere mold.
This is a glorious example of “elegant engineering” where a clever combination of materials and processes has been integrated with highly desirable characteristics:  low tooling cost, low direct material cost, easily scalable from lab to fab, low product weight, and high product resilience. This seems to represent almost a new industrial product category that combines a “package” and a PCB.



Nowhere Near Room Temp Superconductors

October 30th, 2015

On-chip metal interconnects limit IC speed in many advanced design today, and with signal delay proportional to the product of the resistance (R) of wires and the capacitance (C) of dielectric insulation, wires with R lower than that of copper (Cu) metal would significantly improve IC performance. We know of superconductors—materials with zero resistance to electrical current flow—but only at “critical temperature” (Tc) well below 77°K, and so there has been an ongoing quest by scientists to find a material with Tc above room temperature of 298°K.

Sadly, after 4 years and nearly 1000 materials tested, a team of 6 Japanese research groups led by Hideo Hosono from the Tokyo Institute of Technology found no room temperature superconductors. They did find 100 previously unknown superconductors with Tc <56°K, and they published crystal structures and phase diagrams of all materials studied to help other researchers avoid now known dead-ends (DOI: 10.1088/1468-6996/16/3/033503).

Other researchers continue to explore the possibilities of using one-dimensional (1D) carbon-based materials such as carbon-nano-tubes (CNT) or graphene as on-chip conductors. So far, there are extreme difficulties in controlling the growth of such 1D structures within interconnect patterns, and additional challenges with forming ohmic contacts between CNT and Cu lines across billions of connections in a modern IC. More science is seemingly needed to find new paths before the engineers can explore those paths to find better solutions. Meanwhile…for the next few years at least…expect Cu metal to be the continued choice for nearly all multi-level metal interconnects on chip.


EUV Cost at 1000 Daily Exposures

October 26th, 2015

On October 14, 2015, ASML Holding N.V. (ASML) published its 2015 third-quarter results:  Q3 net sales of €1.55 billion with gross margin of 45.4% (in line with guidance), and guided Q4 2015 net sales at approximately €1.4 billion and a gross margin of around 45%. Due to mismatched financial analyst expectations, Bloomberg reported that ASML’s stock price dropped ~7% in a single day of trading, despite the company also reporting upgrades to both the TWINSCAN NXT 193nm-immersion (193i) and the NXE Extreme Ultraviolet (EUV) tools. In particular, a new record of 1000 wafer exposures in a single day was set by one EUV tool.

The science of controlling the 13.54nm wavelength electromagnetic radiation that we like to call “Extreme Ultra-Violet” or “EUV” (instead of the colloquial scientific term “soft x-ray”) is inherently challenging. The engineering of EUV Lithography is not just challenging but bordering on inherently impossible:  from exploding tin plasma source, to all-reflective lenses that absorb energy, to the trade-offs in mask pattern protection. The team at ASML working on the exposure tool—along with the different specialist organizations still working on improved sources, masks, and resists—deserve the industry’s unwavering admiration for the important work they do every day.

In a prepared statement, ASML President and Chief Executive Officer Peter Wennink said, “We have proven the capability both to expose 1,000 wafers per day and, in a manufacturing readiness test, to expose 15,000 wafers in four weeks. We have also achieved a four-week average availability of more than 70 percent  at multiple customer sites. The first shipment of our fourth-generation EUV lithography system, the NXE 3350B, is in progress, with two more expected to ship in Q4.”

Still, progress along desired EUV roadmaps continues to be slow, and the competitive target shifts when the 193i exposure tool gains a 10% throughput improvement to 275 wafer-passes/hour (wph). When the 193i tool gains a 30% overlay improvement, that means double-patterning based on litho-etch-litho-etch (LELE) process flows gain in pattern fidelity. Since ASML provides both technologies, delays in orders for EUV just means more sales of 193i tools.

Let’s play with the numbers here…275 wph x 20 hours x 30 days = 165k wafer-passes/month for the NXT:1980. The NXE:3350B can current handle 15k wafer-passes/month. So even if the tools were equally priced, just based on tool depreciation each EUV exposure today costs >10x that of a 193i exposure, which is why pitch-splitting multi-patterning 193i continues to dominate.


Leti Shows MEMS on 300mm Wafers

September 30th, 2015

As reported by EETimes from the European MEMS Summit last month, French research institute CEA-Leti has manufactured accelerometer MEMS devices on 300mm-diameter wafers. This technology is currently being transferred to Tronics Microsystems SA (Grenoble, France), which currently only manufactures on 200mm wafers. Since CEA-Leti has long functioned as the R&D group for STMicroelectronics (ST), and previously led the way for ST to produce MEMS chips on 200mm-diameter wafers, we may expect that 300mm-wafer MEMS processing is now on ST’s internal roadmap.
Moving production to larger wafers makes sense when either the chip-size or the manufacturing volume increase in size. Much of the growth in demand for MEMS is for so-called “combo” sensors that combine multiple sensor technologies, such as CEA-Leti’s piezo-resistive silicon nanowire technology which allows the accelerometer, gyroscope, magnetometer, and pressure sensor capability to be integrated on the same chip.
The compatibility of Leti’s 200mm-developed technologies with 300mm wafer fabrication, “shows a significant opportunity to cut MEMS production costs,” said Leti CEO Marie Semeria in a press release. “This will be especially important with the worldwide expansion of the Internet of Things and continued growing demand for MEMS in mobile devices.” Sensors of all sorts will be needed for all of the different “Things” to be able to capture new useful information, so we may expect that demand for combo MEMS devices will continue to increase.

Silex’ Strategic Acquisition by China

September 25th, 2015

A secretive investment holding company out of Hong Kong named GAE Ltd has acquired 98% of the shares in Silex Microsystems AB (Jarfalla, Sweden). The transaction took place on July 13th of this year when the former major shareholders agreed to sell all of their respective holdings, while Silex founder and CEO Edvard Kalvesten retains 2% of the shares in the company and continues his role as CEO and board member of Silex. No changes are made to the organizational structure or business operations of Silex, while the new owners plan to build a new high-volume manufacturing line near Beijing that clones the equipment and processes in Sweden with first wafers out by mid-2017 (as reported at EETimes).

Silex claims to be the “world’s number one Pure Play MEMS Foundry”, has worked with AMFitzgerald&Assoc. on RocketMEMS shuttle wafers to reduce MEMS development time by 6-12 months, and has developed multiple Through-Silicon Via (TSV) technologies to allow for efficient 3D integration of MEMS and CMOS.

Almost lost as a footnote in the news is that Silex holds IP on lead-zirconium-titanate (PZT) thin-film technology that allows for efficient piezo-electric energy-harvesting chips. MicroGen Systems is currently in the market with aluminum-nitride (AlN) piezo-cantilever micro-power generator system to power IoT nodes by scavenging either single-frequency or multi-frequency vibrations, working with X-Fab in Germany as foundry partner. If PZT-based piezo-cantilever energy harvesters can compete with AlN-based devices then the former could constitute much of the product volume in the new Silex Beijing fab. In 2014, Yole Developpement forecast “the integration of IoT-dedicated electronic components to result in a market volume of 2B units for these devices by 2021;” if 30% will use energy harvesting then this represents 600M units globally.


300mm ams Fab Bet on IoT

August 31st, 2015

Leading-edge IC fab investments are multi-billion-dollar risky bets. Insufficient demand for ICs dooms the line to economic failure regardless of the quality of design and manufacturing. Thus, it is a big deal that Austrian-headquartered ams AG—world leader in production of IC sensors, RFID chips, and power-supplies—has announced plans to set up a new silicon wafer manufacturing line in up-state New York.
To date, ams’ leading fabs run 200mm diameter silicon wafers, while the new line that is planned for 2017 will run both 200mm and 300mm diameter. With ~2.4x more chips/wafer, the commitment to a 300mm line is a sign that ams expects a major increase in demand for certain products. The vision for the Internet of Things (IoT) is that ubiquitous “smart objects” will be able to connect and exchange useful information without human direction, and the foundation of smart is sensing combined with decision-making. While other companies provide logic chips to allow for decision making, ams provides chips that can sense the world in various ways.
The investment into Marcy, New York represents a bet that there will be sustained demand for analog and sensor chips to provide much of the “smarts” for the IoT. Thus ams is planning to spend >US$2 billion over the next 20 years on capital purchases, operating expenses, and other investments in the facility. Pete Singer provides all the details in his thorough report.

Cross-point ReRAM Integration Claimed by Intel/Micron

July 29th, 2015

The Intel/Micron joint-venture now claims to have successfully integrated a Resistive-RAM (ReRAM) made with an unannounced material in a cross-point architecture, switching using an undisclosed mechanism. Pilot production wafers are supposed to be moving through the Lehi fab, and samples to customers are promised by end of this year.
HP Labs announced great results in 2010 on prototype ReRAM using titania without the need for a forming step, and then licensed the technology to Hynix with plans to bring a cross-point ReRAM to market by 2013. SanDisk/Toshiba have been working on ReRAM as an eventual replacement for NAND Flash for many years, with though a bi-layer 32Gb cross-point ReRAM was shown at ISSCC in 2013 they have so far not announced production.
Let us hope that the folks in Lehi have succeeded where HP/Hynix and SanDisk/Toshiba among others have so far failed in bringing a cross-point ReRAM to market…so this may be a “breakthrough” but it’s by no means “revolutionary.” Until the Intel/Micron legal teams decide that they can disclose what material is changing resistance and by what mechanism (including whether an electrical “forming” step is needed), the best we can do is speculate as to even how much of a breakthrough this represents.

Single-electron Molecular Switch 4nm Across

July 22nd, 2015

A molecule rotating on the surface of a crystal can function as a tunnel-gate of a transistor, as shown by researchers from the Paul-Drude-Institut für Festkörperelektronik (PDI) and the Freie Universität Berlin (FUB), Germany, the NTT Basic Research Laboratories (NTT-BRL), Japan, and the U.S. Naval Research Laboratory (NRL). Their complete findings are published in the 13 July 2015 issue of the journal Nature Physics. The team used a highly stable scanning tunneling microscope (STM) to create a transistor consisting of a single organic molecule and positively charged metal atoms, positioning them with the STM tip on the surface of an indium arsenide (InAs) crystal.
Dr. Stefan Fölsch, a physicist at the PDI who led the team, explained that “the molecule is only weakly bound to the InAs template. So, when we bring the STM tip very close to the molecule and apply a bias voltage to the tip-sample junction, single electrons can tunnel between template and tip by hopping via nearly unperturbed molecular orbitals, similar to the working principle of a quantum dot gated by an external electrode. In our case, the charged atoms nearby provide the electrostatic gate potential that regulates the electron flow and the charge state of the molecule.”

(Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics) (Top) STM images of phthalocyanine (H2Pc) molecule rotated from a neutral (50 pA, 60 mV; left) to −1 charged states (50 pA, −60 mV; centre and right) on InAs(111) surface using a ~4nm across hexagonal array of charged indium adatoms surrounding the H2Pc to create rotational energy minima, and (Bottom) schematic model of H2Pc rotation relative to the InAs lattice resulting in the electrostatic gating of tunneling to an STM tip vertical to the device. (Source: Nature Physics)

The Figure shows that the diameter of the device is ~4nm, so by conservative estimation we may take this as the half-pitch of closest-packed devices in IC manufacturing, which leads to pitch of 8nm. As a reminder, today’s “22nm- to 14nm-node” devices feature ~80nm transistor gate pitches (with “10nm node” planning to use ~65nm gate pitch, and “5nm node” ICs expected with ~36nm gate pitch). Thus, these new prototypes prove the concept that ICs with densities 100x more than today’s state-of-the-art chips could be made…if on-chip wires can somehow connect all of the needed circuitry together reliably and affordably.

Electronic Materials Specifications and Markets

June 30th, 2015

At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.

Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.

As in prior years, SEMICON West includes many free and paid technology sessions and workshops, the Silicon Innovation Forum and other business events, as well as a profusion of partner events throughout the week.


Nakamura on blue light history and future

June 26th, 2015

Nobel Laureate Shuji Nakamura provided the keynote address to the attendees at the 57th annual Electronic Materials Conference held this week in Columbus, Ohio. His talk on “The History and Developments of InGaN-based LEDs and Laser Diodes” informed and entertained the audience of materials researchers, particularly since he followed first-principles of materials science and his natural inspiration to create the world’s first commercially viable blue LEDs over 20 years ago.
Nakamura-sensei is now legendary for showing excellent GaN-based blue LED functionality in an era when ZnSe was the main material explored by almost all scientists in the world due to six orders of magnitude superior defectivity level for the latter material (due to near zero lattice mismatch between ZnSe and GaAs, instead of the extreme mismatch between GaN and sapphire). In the 57th EMC keynote, he confessed that the only reason he began work on GaN was that almost everyone else was ignoring it so he could easily get papers published on the way to earning a Ph.D., and he initially had no plans to try to create a blue LED with the material.
However, when he bought a new MOCVD reactor to grow GaN on sapphire substrates he found the capabilities of the tool to be lacking so he began daily hardware modifications and test runs, and after some months began to get surprisingly strong data. Soon his group at Nichia was reporting world record GaN optoelectronic properties, and had developed both n- and p-type GaN. However, from first principles it was known that a double-heterojunction (DH) structure would allow for band-gap and hence wavelength tuning, so he then developed the world’s first useful InGaN MOCVD process and by 1993 was able to issue a press release claiming 1000 mcd LED output. “Indium gallium nitride is the most important material, but the Nobel committee didn’t say anything about Indium gallium nitride,” reminded Nakamura.
Most of the rest of the story is well known by now, including his precedent-setting lawsuit with Nichia, move to UCSB, and founding of Soraa.
Nakamura’s vision for the the future of blue (and through integration with phosphors “white”) light can be summed up as LEDs are good but lasers are better. Relatively speaking, with lasers the current density can by many times higher, and BMW and Audi have prototype laser headlamps that can reach 2-3x farther down the road compared to the best lamps today. The challenges today are to improve efficiency and cost. Efficiency for blue LEDs are now 50-60% while lasers are only ~30%. Also, blue laser production cost is now ~10x higher than that for blue LEDs.

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