EUV first drew the semiconductor industry’s attention in the late 1990s, as lithographers began to consider the “post-optical” future. At that time, the future was expected to arrive with the 100-nm technology node, by 2004. ArF lithography turned out to be far more extensible than anticipated, though, and is still going strong fifteen years later. Which is fortunate given that, as we now know, EUV lithography was not ready in 2004. Indeed the technology still is not ready for production in 2012.

Even at the time, many people felt the 2004 target was overly optimistic. Few would have expected EUV to still be “just around the corner” in 2012, however. Most would have guessed either that the technology would have reached production some years ago, or that it would have been abandoned as unworkable by now. EUV, as Winston Churchill famously said about democracy, appears to be the worst form of post-optical lithography except for all the others that have been tried. From 157-nm F₂ lasers to directed self-assembly, alternatives to EUV are proposed every few years, then drop back to the background as their limitations become evident. Meanwhile, EUV soldiers on, making slow but consistent progress.

For the short term, the EUV outlook remains grim. As my colleague Mark LePedus reported, Cymer was forced to delay deliveries of the company’s 20 watt EUV source. Originally expected in late 2011 or early 2012, this upgrade has been pushed out by at least a quarter. Such delays are especially worrisome because EUV source power remains far short of the 100 watts or more that even small-scale production would require. In the face of such delays, it’s easy to lose sight of the forest and miss the very substantial progress the technology has made. According to Mike Lercel, Cymer’s Senior Director of EUV product marketing, the company has demonstrated 50 watt average power in a continuously operating, production-style source. That result, and the imminent 20 watt upgrade to sources already in the field, represent dramatic improvements within the last year.

Similarly, Lercel said, Cymer has achieved a collector lifetime of approximately ten weeks. In a laser-produced plasma (LPP) source like Cymer’s, a laser pulse ionizes a droplet of tin. The resulting plasma emits EUV photons in all directions. To produce the directional beam needed for lithography, a mirror surrounding the plasma reflects these photons through an aperture and into the lithography system. Debris from the plasma gradually erodes the surface of this so-called “collector,” requiring its replacement. While a ten week lifetime is well short of the one year replacement interval that is Cymer’s ultimate goal, it still represents a 10-fold improvement over earlier designs.

Thanks to the collector lifetime increase and other improvements, Lercel reports that Cymer’s overall source availability now reaches 70%. Though not impressive by the standards of a production fab, 70% availability at 10 or more watts of source power is enough for device development. It’s enough to allow fabs to compare EUV and ArF-based process flows and imaging results. Based on these early results, Lercel said, process engineers like what they see.

At the 20-nm node and beyond, ArF-based lithography will be extremely difficult. Multiple patterning will be ubiquitous, with all the additional process steps and yield risk that implies. These challenges are why EUV has not yet been abandoned, and why the imaging results that are now becoming available are very exciting for lithographers. As Lercel explained, a big departure in 2012 relative to previous years is that people are starting to believe that EUV will really happen. “They’re more willing to invest; they want this technology in their fabs.”

It’s still not possible to say when, or even if, EUV-printed chips will start to make their way through production fabs. It’s not even clear that the glass is half full. But, finally, the level of liquid in the glass seems to be rising at a perceptible and reassuringly steady rate.

For a long time, semiconductor defect inspection focused on particles, and particle defects remain an important cause of yield loss. But as devices have become more complex, additional kinds of defects have drawn the attention of process engineers. Bridging, pattern collapse, and other resist defects have become particularly important in the sub-100 nm era. The introduction of CMP brought abrasive slurries, scratching, and dishing defects.

As defect concerns have evolved, so have the inspection tools available for process monitoring. Beyond particle scanners, we now have electron microscopes for CD inspection, broadband imaging for scratch and void detection. Still, all these tools use some form of imaging to identify physical defects in the structure of the device. They cannot capture another, increasingly important, class of defects: those that affect the chemical structure of the surface.

Such non-visual defects (NVDs), as they are called, can have as many root causes as physical defects. Metallic contaminants in a cleaning bath can coat a wafer with ions. A few monolayers of residue might be left behind by the post-etch clean. Any wet chemistry step might leave drying spots. Any of these defects can have a profound impact on device behavior.

Since optical inspection methods are ineffective for these defects, new inspection technologies must fill the gap. For example, the ChemetriQ technology from Qcept uses a scanning probe to measure changes in the work function of the wafer surface. As Robert Newcomb, Qcept’s Executive VP of operations explained, metallic contaminants generally increase the work function, while non-metallic materials usually decrease it. Although the system does not directly identify defect types, it can help process engineers decide where to look for problems. Furthermore, by inserting an inspection point after a short process loop, the system can identify defects that might otherwise go undetected until final electrical test.

In one case, Newcomb explained, an SRAM process produced chips with an unacceptable degree of speed variation, causing the end customer to reject the devices. These variations matched work function variations seen after the spacer etch and ash steps: when those processes were modified, the tighter speed distribution resulted in a 20% increase in salable die per wafer. Equally important, even before the problem was solved, being able to correlate observed NVDs with device performance helped the fab present a credible action plan to their customer.

While discussions of inspection technologies often focus on leading edge processes, each device category faces its own yield challenges. For example, rapid growth in wireless connectivity is creating new markets for analog devices. Particle specifications for these devices are somewhat relaxed due to their large size. Residues, on the other hand, can easily cover large areas, wiping out a substantial fraction of the wafer. One analog fab reported poor yield after lithography rework. While they suspected BARC residues might be responsible, optical and SEM defect data didn’t match the areas of poor yield. The ChemetriQ tool, on the other hand, found dramatic evidence of residue in the suspect area.

BARC residue remaining after an analog litho rework process. Image: Qcept Technologies

Sometimes, knowing that residues aren’t present can be as valuable as knowing when they are. The profitability of a fab, especially one using mainstream processes, depends on costs as well as yield. One such fab used NVD inspection to show that they could extend the life of an IPA cleaning bath without increasing defects. As a result, the fab saved $70,000 in chemical costs per month, while cutting IPA effluent in half.

In the semiconductor industry, it’s understood that each technology generation brings new processes and new materials. What’s less obvious is that each generation brings new defect mechanisms as well. Process engineers have a constant need to upgrade the “eyes” they use to watch over their processes.

O-ring seals are everywhere in a typical semiconductor fab. Any piece of vacuum equipment uses several of them to seal the openings where components of the process chamber fit together. Yet, as ubiquitous as they are, most process engineers don’t think about them very much. They buy the seal specified by the equipment vendor, from the supplier with the most attractive price, and pretty much leave it at that.

Dalia Vernikovsky, CEO of Applied Seals North America, is trying to change that. As she explained in a conversation at Semicon West, o-rings were originally invented in 1937, for use in engines, not vacuum chambers. Most commonly used testing methods reflect that heritage, focusing on tensile tests and pulling. In the semiconductor industry, however, o-rings are more likely to encounter twisting and grinding as the parts on either side of the seal move, or fatigue as fittings are tightened into place and loosened again. Moreover, even a seal that appears to remain intact can leak filler particles and other contaminants into the process chamber.

Meanwhile, feature sizes are shrinking, and new materials and process gases are being used in vacuum chambers. Often, Vernikovsky said, neither process engineers nor seal designers fully understand how the process will interact with the seal. While the process temperature is less important than sometimes believed — the seal doesn’t reach plasma temperature — process gases can leech out components of the seal polymer. Similarly, many purchasers specify that seals must contain “no metals,” even though many metals are quite stable in many process environments. Silica, a common alternative, is non-reactive but tends to agglomerate into clumps. Metrology that can see killer defects for sub-32 nm devices has only recently become available, so the extent of the seal contamination issue is only starting to be understood.

For instance, in research with Sematech, ASNA tested the cleanest available seal material for 45 nm node production, a silica-filled elastomer — in an MOCVD system for EUV mask blank deposition. Defect levels were unacceptably high, with especially high levels of contamination from the elastomer materials. Mask defects as small as 7 nm can still print, but 7 nm is smaller than typical filler materials and the same order of magnitude as many commonly used elastomer molecules.

Based on these results, Sematech proposed a fundamental study on particle generation from sealing materials. Among other things, ASNA is working to develop nanocomposite filler materials with sub-40 nm particle sizes, and to replace the Viton used in many o-rings with a low-carbon alternative. Separately, the company is leading efforts to form a SEMI task force to develop seal standards that more accurately reflect the specialized needs of the semiconductor industry.

I’m working on a longer article on low-k dielectric integration, but in the meantime I wanted to pass along an observation from Joubert Olivier of LTM-CNRS, in his presentation at the Materials Research Society Spring Meeting.

Asked about the prospects for low-k integration, he reminded the audience that even if an integration scheme is able to achieve good selectivity between the hard mask and the dielectric, and produce good sidewall profiles without pattern collapse, and prevent redeposition of etch by-products — all of which are significant challenges in themselves — even if all of these goals are achieved, the industry will still have to deal with the fundamental problems of increased leakage and dielectric constant increase due to plasma damage and post-etch cleaning.

None of these problems are new. The semiconductor industry has been struggling with them since the late 1990s, when porous dielectrics first began to appear in technology roadmaps. The lack of clear solutions more than ten years later prompted Olivier to suggest that maybe it’s time for a new strategy.

Other speakers at the MRS meeting suggested some possible alternatives. Sven Zimmerman of Fraunhofer ENAS, working in collaboration with Global Foundries, suggested a less damaging patterning regime based on a combination of CF₄ etch chemistry, cleaning solutions optimized for the specific plasma chemistry, and a surface repair process. Theo Frot and a team at IBM suggested infiltrating a polymer into the dielectric pores to add mechanical support during the etch process, then removing it to restore the desired structure. Results were promising, but these ideas are still at the laboratory stage. For manufacturing, porous low-k dielectric integration is already running years behind schedule.

It’s a central problem of integrated circuit scaling. While transistor delay goes down along with channel length, interconnect delay goes up. The 90 nm technology node featured a transistor delay of about 1.6 ps, while a 1 mm long interconnect wire added about 5×10² ps. For the 22 nm node, the ITRS estimates transistor delay at 0.4 ps, but interconnect delay at about 1×10⁴ ps.

Smaller transistors are faster, while interconnect resistance goes up as the cross section of the line goes down. Surface scattering, grain boundary scattering, and the higher resistance of the diffusion barrier all contribute to RC delay. Reduced interconnect length is often offered as a benefit of 3-D integration, but it’s important to consider whether we have reduced the length of board-level, or circuit-level interconnects.

3-D integration with through-silicon vias (TSVs) primarily affects the interconnects between chips, and therefore reduces the amount of circuit board area. As usually implemented, this approach stacks several memory or other chips vertically, landing TSVs on the upper chip onto conventional bond pads on the lower chip. Each chip within the stack represents a complete 2-D design, with all of its circuit-level interconnections.

In contrast, MonolithIC 3D proposes true 3-D design integration, in which the layers of a stack are designed as a single unit. Partitioning the design appropriately allows global interconnects to be vertical as well as horizontal, with shorter wires. Less area is needed for repeaters and similar elements; the total silicon area is lower. As Lili Zhou and co-workers at the University of Washington showed (ICCD 2007), multi-layer design can cut silicon area in half and total interconnect length by two-thirds.

The MonolithIC 3D approach depends on layer transfer technology — similar to that used in Soitec’s silicon-on-insulator wafers — to stack thin silicon device layers. Because the vias in such a structure only need to pass through the active layer, they can be much smaller than conventional TSVs, with dimensions only 3x larger than the top interconnect layer. The company claims that, for many applications, their approach provides a scaling benefit equivalent to one process node, without the extraordinary process and equipment costs. It’s an intriguing possibility, but hard to evaluate until it’s been realized in silicon.

Laser pulses per month for Gigaphoton's KrF and ArF lasers.

(Click for larger image.)

I thought this image was a nice illustration of exactly what happened in the most recent industry downturn. The graphic shows the number of pulses per laser, per month, for Gigaphoton’s installed base of ArF and KrF lasers. A stepper processing 1,000 wafers per month typically produces about 800 million pulses per month.

As you can see, in late 2008 and early 2009, wafer production fell off a cliff. It didn’t recover to pre-downturn levels for nearly a year. In a more typical cyclical capital spending downturn, equipment purchases slow down as new capacity exceeds new demand, but wafer unit volume keeps rising. When demand catches up, companies start building fabs again. For the most part, chipmakers and their suppliers have learned how to manage their way through these ups and downs: they’ve been part of the industry from the beginning.

Falling wafer volume, in contrast, means that the semiconductor industry downturn is tied to a macroeconomic recession: people don’t buy as many chips. Such dips are much more unusual, and much more challenging for company management. Capital expenditures don’t recover until capacity utilization improves, and that doesn’t happen until customers start buying again.

Image courtesy of Gigaphoton, Inc.

The recent announcement of 2010 silicon wafer shipments got me wondering: silicon consumption for solar cells passed silicon consumption for integrated circuits a number of years ago, but how do they compare now? A quick call to the very helpful Richard Winegarner at Sage Concepts answered the question. In 2009, solar cells consumed 10 times as many square inches, but generated about the same total revenue.

Source: SEMI for semiconductors, Sage Concepts for solar, polysilicon

As Winegarner explained, wafers for semiconductors cost about US$1.00 per square inch, while wafers for solar cells cost only about US$0.10 per square inch on average. I expect almost all of this price differential can be attributed to the extremely energy intensive Czolchralski growth process used for semiconductor wafers, and to their larger size and more stringent performance specifications.

Incidentally, SEMI analyst Dan Tracy reports that 300mm wafers have only just recently captured the majority of the market, accounting for 51% of the total in 2010 and 52% in 2009. That’s 10 years after the first 300mm wafer rolled off the Semiconductor300 pilot line, a timeline worth remembering as the industry considers a move to 450 mm wafers.

Welcome to Semiconductor Manufacturing & Design Community. I’m Katherine Derbyshire, your tour guide through the silicon rapids.

My background is in materials science, with degrees from MIT and UC Santa Barbara, and I’ve been following the IC industry since the 1990s, beginning with a stay at Solid State Technology. Through good years and bad, from the first dot com boom to the Great Recession, it’s never been boring. The technology keeps rolling on, and companies that try to anchor themselves often see their business swept away downstream.

I’m especially interested in the transistor process, but expect to cover the whole integrated circuit manufacturing space. I’m working on items on ultrashallow implants and through-silicon vias now, for example. I hope you’ll join me.