Comments for Semiconductor Manufacturing & Design Community

Comment on Soitec Touts FD-2D and FD-3D on SOI Wafers by Horacio Mendez

Horacio Mendez — Mon, 30 Apr 2012 17:37:08 +0000

To answer the question directly: This is absolutely NOT a SOITEC and ST only effort.

• At the Fully Depleted substrate level, there are multiple suppliers, SOITEC, MEMC and SEH with the technical capability, experience and scale to supply the volume requirements in the low power markets.

• The design portability bar for Fully Depleted SOI is much lower than Bulk and finFETs. This is because of the very well behaved transistor characteristics at low voltages and nearly ideal analog performance. There are no EDA or restrictive DFM rules on the design migration. Bottom line, the EDA support is inherent.

• From the very key mobile IP suppler, ARM , I would suggest you take a look at the earning reports interview from Warren East, CEO of ARM, when asked:

- How does ARM see FD-SOI?
– “We think it’s pretty good,” replies East, “we think SOI and fully depleted SOI are great approaches. We take note of it. They seem to be getting some excellent numbers.”

http://www.electronicsweekly.com/Articles/25/04/2012/53509/arm-expects-strong-q3.htm

— I would like to also note that ARM has done key benchmarking of FD SOI.

• While we are not in position to make announcements for any of the foundries, the foundry partners in the JDA have full access to Fully Depleted SOI and I personally believe that as the business demands increase (first product introduction has already been announced by STE), the foundry support is well positioned to respond rapidly.

• Finally, the R&D pipeline is very active within the JDA and Leti focused on effectively scaling Fully Depleted SOI to 14 nm and beyond.

The key point and upshot is that this is a comprehensive multi- company effort representing the entire Consortium ecosystem.

Horacio Mendez
Executive Director
SOI Industry Consortium

Comment on IC Roadmap Remains in Flux Amid Scaling Challenges by litho guy

litho guy — Mon, 30 Apr 2012 00:57:03 +0000

I couldn’t rely on EUV for beyond 14-15 nm anyway since the resist can’t resolve that. It’s time to start thinking about pitch division rather than new wavelength. The move beyond planar bulk transistors is complex enough already.

Comment on New DFM and Verification Hurdles Seen at 20/14nm by Chris EDA

Chris EDA — Sun, 29 Apr 2012 19:33:05 +0000

The casual and imprecise language in this article may make for a fun read, but it doesn’t inspire me with a lot of confidence in the technical rigor of the authors: Technologies can “swoop in”, the “NAND crowd”, Double-patterning is “doable”, “the sky is falling”.

Comment on Soitec Touts FD-2D and FD-3D on SOI Wafers by Adele Hars

Adele Hars — Fri, 27 Apr 2012 17:58:16 +0000

ST says there’s no particular impact to design flow/EDA, beyond extraction deck and SPICE models, which are available. They summarized their 28nm FD-SOI for ASN — see http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/. Or you can get the whole white paper from the SOI Consortium website: http://www.soiconsortium.org/link-812.php. ST’s fabbing for STE’s 28nm FD-SOI NovaThor, which tapes out in Q3. Also recommend ST-E’s blog on all this — see http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/

Comment on Soitec Touts FD-2D and FD-3D on SOI Wafers by SoC Guy

SoC Guy — Mon, 16 Apr 2012 19:55:56 +0000

Is this a SOITEC and ST effort only, is the rest of the support infrastructure involved. (IBM, foudry, EDA guys etc?)

Comment on Analog Vendors Eye Expansion Despite Market Lull by Colin

Colin — Fri, 13 Apr 2012 09:45:14 +0000

This is a good business survey. Thank you very much.

Comment on Intel Turns Up Heat in Silicon Foundry Business by Mike Bruzzone

Mike Bruzzone — Sat, 07 Apr 2012 04:28:32 +0000

My bet is that Intel will reserve 28 nm for majority of foundry sales and use this revenue stream like a lit rocket through jump gate into molecular electronics solidifying their current accelerated position.

Mike Bruzzone
Camp Marketing

Comment on Berkeley’s Hu Tips Industry Standard Model for finFETs by Sriram

Sriram — Sun, 01 Apr 2012 03:41:59 +0000

If I had known it would be published here I would have spent more time creating better figures

Comment on DNS Ponders Ice as New Wafer Cleaning Agent by Gary Hillman

Gary Hillman — Wed, 28 Mar 2012 17:35:06 +0000

The expanding phase from water to ice will tear features on the wafer surface from their underpinnings. If the particle is torn from the surface so will intended features. The expansion forces are enormous.

Comment on Altera Jumps on TSMC’s CoWoS Process Offering by DD

DD — Mon, 26 Mar 2012 16:23:24 +0000

Foundries are looking at 2.5 D / 3 D as a way to bridge the gap with Intel who now leads them by 2 nodes. They make sense to Fabless co.s like Xilinx & Altera ( large dies in less cost driven small markets ) or IDMs who do not want to invest in latest nodes and wafer dia.s ( e,g. IBM ) but not for Smart Phones etc. as a MCM with Interposer ( 2.5 D ) would always be more expensive than a single chip from a leading edge Fab, which is why MCMs did not make any headway in the cost driven PC world. But on the other hand Intel has a ARM problem.