Notes from The ConFab 2016 – Day 2
By Dick James, Senior Technology Analyst, Chipworks
The opening keynote for Day 2 was Wally Rhines of Mentor Graphics, always a lively and entertaining speaker. His topic this time was “What Will Stimulate the Next Wave of Semiconductor Industry Growth?”Wally Rhines of Mentor talking foundry costs at his ConFab keynote
Wally started by putting Moore’s Law in the context of a learning curve, in which
- cumulative transistors produced increase exponentially with time (e.g. 2x cumulative volume -> fixed % cost decrease)
- almost all cost reduction comes from shrinking feature sizes and growing wafer diameter
That gives us a nice log/log plot of revenue/transistor vs cumulative transistors produced;
He spent the first part of his talk putting the rest of the industry segments (equipment, EDA etc.) into that context, until we got to discussing the 28 – 20 nm transition, with no cost reduction, and with a 40% cost/wafer increase as we get to finFET-based 14-nm products.
However, the transistor learning curve continues, despite these challenges, because memory, especially NAND flash memory, dominates the transistor count – 99.7% of all transistors are now in memory chips, and 80% of those are flash. Now that we are in the 3D-NAND era, that trend will only keep going, Wally claims for the next 10 – 20 years.
A major driver for this will be image storage and processing; IC Insights predicts that the image sensor market will not flatten out until it reaches 30+ billion units per year, from the current ~6 billion; aside from consumer usage, autonomous vehicles and security applications will almost certainly demand more image handling.
Wally finished up by making the point that the conventional von Neumann computer architecture is not adequate for image processing, and if the transistor learning curve does continue, then different architectures will be needed, more akin to the human brain in terms of pattern recognition and power dissipation.
The theme of the morning session was “Success in Fab Management” and featured four speakers, the first Rick Glasmann from Infineon’s 150 mm fab in Temecula, a former International Rectifier fab. He described a case study whereby they tightened up the fab process control and achieved 19% improvement in on-time delivery, and a 10% improvement in Cpk, amongst other measures.
Second up was Sanchali Bhattacharjee of Intel, describing a SEMI initiative to drive defect control within equipment, specifically the SCIS (subcomponents instruments and systems) working group. Co-optimization is not just a buzz-word for product development, it also applies across the fab supply chain from the wafer level down to the individual components within the fab manufacturing equipment – valves, pumps, RF generator, seals, etc.
The components theme continued in the next talk by Ardy Sidwha, detailing QuantumClean’s capabilities of creating Atomically Clean Surface™ surfaces on everything from quartz components to complex showerheads. It was a bit of a sales pitch, but still impressive since the need is obviously there to maximize yields and reduce cost of ownership.
The last speaker of the morning was Mike Czerniak (Edwards), who went through the efforts by the industry to get rid of greenhouse gases. That has been successful in the case of per-fluorinated compounds (PFCs) such as carbon tetrafluoride, meeting the target to limit PFC emissions to 90% of 1995 levels by 2010, a significant challenge given the growth of the industry in that time period. This was mostly achieved by the replacement of PFC CVD chamber clean gases by nitrogen trifluoride, which is efficiently consumed by the process tool.
The World Semiconductor Council has now tightened up the target for equivalent carbon dioxide emissions, looking for a 30% reduction from 2010 levels.
Mike gave an example of a fab footprint, showing quite impressive reductions in emissions going across the fab:
Newer fabs start off with the advantage that they are designed for abatement, so the figures are actually better; though it seems that etch chemistries are more difficult, and the focus is now in that area.
After lunch we had set of four presentations preceding another panel, this time focusing on system level integration via packaging.
Bill Bottoms of 3MTS was the first up, noting that we have seen the final edition of the ITRS roadmap; essentially, CMOS has run out of steam. In its place we have a plethora of new roadmaps (or at least four) – the International Electronics Manufacturing Initiative (INEMI) Roadmap, the International Roadmap for Devices and Systems (IRDS), the Photonic Systems Manufacturing Roadmap (PSMR), and the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS).
Bill went on to describe HITRS, sponsored by IEEE CPMT Society, The IEEE Electron Devices Society and SEMI. There are working groups within the overall roadmap envelope;
- Heterogeneous Integration Components
- Cross Cutting Topics (Emerging Research Materials, Emerging Research Devices, Integrated Power Devices, Interconnect, and Test)
- Integration Processes (System in Package, 2.5D and 3D, Integrated Power Devices, Wafer Level Packaging)
- Packaging for Specialized Functions (Mobile, IoT and Wearables, Medical, Automotive)
The roadmap has an active workshop schedule, with nine meetings before year end, two during Semicon West week, one at the show and one in Palo Alto.
Brian Black (AMD) gave a review of the design/packaging co-optimization (there’s that word again!) of the Fiji chip in the new AMD Radeon Fury (Fiji) graphics processor. This is notable in that it uses the Hynix High-Bandwidth Memory (HBM), together with a silicon interposer, to give 60% higher memory bandwidth for 60% less power than GDDR5 memory.
As an illustration of the benefits of this type of integration, the GPU is made in 28nm technology, and the HBM is 25nm generation, and the performance is better than a competing graphics unit using 20nm logic and 20nm DRAM.
Islam Salama of Intel then detailed their approach to increasing memory bandwidth; one of their metrics is the number of I/O wires escaping per millimeter of die edge for each layer of the package, as a way of comparing different technologies.
This can then be used to help decide the most appropriate package type for a specific product, whether it be a co-packaged e-DRAM as in the Iris Pro series of processors, or a more complex multi-chip package as used in the new Knight’s Landing series.
Intel has been promoting their EMIB™ architecture of late, and claims an advantage over the silicon interposer in that it does not need a large piece of silicon, or TSVs, but gives similar bandwidth.Intel’s EMIB architecture
Rama Alapati from Amkor finished up; he gave a short and sweet exposition of integration trends across five key segments – mobility, IoT, auto, high-performance computing, and memory, and across those segments, Amkor’s place in the ecosystem. Considering that he had only been with the company for six weeks, he did pretty well!
The panel was moderated by Li Li of Cisco, and was also short and sweet, only half an hour or so, then a rest before the Tuesday night reception. Brian was asked if die stacking would help just as much with a 14 or 10-nm process; his answer was that a 14-nm die-stack would be better than a 7-nm fully integrated chip. Another question was about the high cost of 3D packaging, and Bill responded by saying that the high cost was due to high-aspect ratio TSVs, and most heterogeneous integration does not need them –simply thin the wafers, then 2D/3D becomes a cost reducer, not a cost adder.
All in all, a good afternoon session.
Stay tuned for a review of Day 3…