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Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium

Just published is the press release and tip-sheet on the 2012 VLSI Symposia on VLSI Technology and Circuits, this year in Hawaii. Listed first in the VLSI Technology highlight papers is Intel’s paper, “A 22nm High-Performance and Low-Power CMOS Technology Featuring Fully Depleted Tri-Gate Transistors, Self-Aligned Contacts and High-Density MIM Capacitors”, to be presented by Chris Auth in slot T15-2.

There was a fair bit of frustration at last year’s IEDM that there was no Intel paper on their tri-gate technology, although they had several others at the conference. The Intel folks I talked to said that there was reluctance to publish, since the other leading-edge semiconductor companies were not presenting – conferences were no longer the exchange of information that they have been in the past. I have to say I agree, some companies are keeping their technological cards very close to their corporate chests these days!

Also, no product was in the public domain at that point, though Intel claimed to be in production. By the time VLSI comes around in June, we should all be able to get Ivy Bridge based Ultrabooks, and we at Chipworks will have pulled a few chips apart.

In the paper the process is claimed to have “feature sizes as small as eight nm, third-generation high-k/metal gate stack technology, and the latest strained-silicon techniques. It achieves the highest drive currents yet reported for NMOS and PMOS devices in volume manufacturing for given off-currents and voltage. To demonstrate the technology’s versatility and performance, Intel researchers used it to build a 380-Mb SRAM memory using three different cell designs: a high-density 0.092- µm2 cell, a low-voltage 0.108- µm2 cell, and a high-performance 0.130-µm2 cell. The SRAM operated at 4.6 GHz at 1 V.”

The tip-sheet also posted the first Intel tri-gate images that I’ve seen in a while:

TEM images of Intel 22-nm PMOS tri-gate transistor (a) and source/drain region (b)

Here we are looking at sections parallel to the gate, across the fin. There is no scale bar, so fin width is an unknown; and the taper on the fin is a bit of a surprise. The top of the fin is rounded, likely to avoid reliability problems from electric field concentration at corners.

In the gate metal, there seems to be a layer of titanium nitride (TiN) above the thin dark line that is the high-k, so we can surmise that the PMOS work-function metal is TiN, as in previous generations. The gate fill itself is very black, so that appears to have been changed from the Al/Ti fill used before; possibly to tungsten or some other heavier metal.

The source/drain image confirms the use of epi, and the darker area is again likely SiGe, both for strain and resistance improvement. At the moment it’s hard to say if the taper is a function of manufacturing convenience (easier to etch?), or if there are some device physics advantages that improve transistor operation. We’ll see in June!

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