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Archive for April, 2012

Intel’s 22-nm Trigate Transistors Exposed

Tuesday, April 24th, 2012
Last week Intel had their Q1 conference call for financial analysts, and revealed that the 22-nm Ivy Bridge parts would make up 25% of their shipment volume in the second quarter of this year.  That means that a good quantity will already will have shipped, and we managed to track some down in Hong Kong a few weeks ago.  Of course we got in touch ASAP and the parts duly arrived, and they were the real thing.

Fig. 1 Intel Xeon E3-1230V2 Server CPU

We obtained samples of Xeon E3-1230 v2 CPUs, which are four-core, 3.3 GHz, 64-bit parts intended for the server market. Here is a die photo of the transistor level, with annotations from Intel’s Ivy Bridge launch yesterday:

Fig.2 Intel Xeon E3-1230V2 Die

A quick cross-section reveals that Intel have stayed with the nine metal layers used in the last two generations:

Fig. 3 Intel Xeon E3-130V2 General Structure

A closer TEM image (Fig. 4) shows the lower metal stack and a pair of multi-fin NMOS and PMOS transistors. This section is parallel to the gate, across the fins, and we can see the contact trenches and metal levels M1 up to M5.

We have to digress here a little to explain what we’re looking at.  A typical TEM sample is 80 – 100 nm thick, to be thin enough to be transparent to the electron beam and at the same time have enough physical rigidity so that it does not bend or fall apart.

Here we are trying to image structures in a die with a gate length of less than 30 nm; so if we make a sample parallel to the gate, and if the sample is aligned perfectly along the centre of the gate, then it will contain the gate plus at least part of the source/drain (S/D) silicon and contacts on either side.

Fig. 4 TEM Image of Lower Metals and NMOS and PMOS (right) Transistors

That is what we see above – I have labeled the gate and contact stripes, and we have PMOS on the right and NMOS on the left.  The tungsten-filled contacts obscure parts of the gate, but we can clearly see that the PMOS S/D fins have epitaxial growth on them, and the fins have an unexpected slope – a little different from Intel’s tri-gate schematic shown last year –see Fig.5.

Fig. 5 Intel Schematic of Tri-Gate Transistor

If we zoom in a bit further into the PMOS gate (Fig. 6), we can see how the gate wraps over the fin, and the rounded top of the fin.  The thin dark line adjacent to the fin is the high-k layer and just above that is a mottled TiN layer that is likely the PMOS work-function material, as in the 32-nm and 45-nm parts.

Fig. 6 TEM Image of PMOS Gate and Fin Structure

Fig. 7 shows a section of an NMOS transistor.  There is a ‘ghost’ of the contact behind the gate, but the gate structure itself looks similar to the PMOS, with the exception of the work-function material just above the high-k layer (as expected).

Fig. 7 TEM Image of NMOS Gate and Fin Structure

Fig. 8 gives me an opportunity to show off our new TEM – we have recently purchased an FEI Osiris machine, which upgrades our capability considerably. Here we have a lattice image of a fin in an NMOS transistor; the diamond-like layout of the pattern of dots is actually created by the columns of atoms in the silicon crystal lattice. This tells us that the sample is oriented in the <110> direction, which given that silicon has a face-centred cubic structure in which equivalent planes are at right angles, means that the channel direction is also <110>.

Fig. 8 TEM Lattice Image of NMOS Fin Structure

To fully understand what we’re looking at, of course, we need to see what’s happening in the orthogonal direction, along the fin and cross-sectioning the gate – as in Fig. 9. This shows an array of PMOS transistors over a single fin, four functional gates and two dummy gates at the ends of the fin. Again the TEM sample is thick compared with the feature size, so we are seeing the gate on the side(s) of the fin, not just the top. The fin ends have the same taper as in Figs 6 and 7.

Fig. 9 TEM Image of PMOS Transistors

As announced by Intel, there is embedded SiGe in the source/drains, although not etched to the <111> planes as in the 32- and 45-nm product. It also looks as though the tops of the gates have been etched back and back-filled with dielectric, and the contacts are self-aligned as in memory chips.

Zooming in on the PMOS transistor in Fig.10, the image is a bit fuzzy, but the SiGe is clearly in a rounded cavity with no facets on the top, though there are facets on the sides of the fin (see fig. 4).

Fig. 10 TEM Image of PMOS Transistor

Looking at the NMOS equivalent (Figs. 11 and 12), we see a similar structure – there seems to be an epitaxial interface, and the silicide(?) seems to protrude slightly above the fin.

Fig. 11 TEM Image of NMOS Transistors
Fig. 12 TEM Image of NMOS Transistors

 It is hard to say much about the gates here, either NMOS or PMOS, because of the sample thickness problem; we are viewing a slice that includes the gate on both sides of the fin and the fin itself. Fortunately we have images of gate metal over STI and they are less confusing. 

Figure 13 is a composite image of NMOS and PMOS gates so that the differences are highlighted. The dark line surrounding the gate structures is the Hf-based high-k, and within that are the two work-function materials, likely TiN for PMOS and TiAlN for NMOS. (The columnar structure of the PMOS TiN is visible in the right half of the image.)

Fig. 13 Composite TEM Image of NMOS/PMOS Gates

The fill has been changed from TiAl in the earlier parts to tungsten. It is more prominent in the NMOS gates than the PMOS, because the PMOS structure includes both work-function metals, whereas the TiN has been etched out of the NMOS gates. At the 45-nm node Intel used tensile tungsten in the contacts to apply channel stress – have they transposed this to the gates in the 22-nm process?

Just to finish up, so that this is still a blog, not a paper (I don’t want to go on too long) – fig. 14 shows a sample delayered to expose the transistors, and imaged on a tilt angle.  Both the gates and the fins show up nicely, and we can actually see tiny spikes of SiGe in the PMOS source/drains. The small pillars in between the fins in the NMOS areas are residual bits of contact metal.  I think it’s a cool image!

Fig. 14 Tilt SEM Image of NMOS/PMOS Transistors

We are just getting into the full scope of the analysis, so likely more to come in the next few weeks!
I’m still tweeting as @ChipworksDick, for those that way inclined..

Intel to Present on 22-nm Tri-gate Technology at VLSI Symposium

Thursday, April 12th, 2012
Just published is the press release and tip-sheet on the 2012 VLSI Symposia on VLSI Technology and Circuits, this year in Hawaii. Listed first in the VLSI Technology highlight papers is Intel’s paper, “A 22nm High-Performance and Low-Power CMOS Technology Featuring Fully Depleted Tri-Gate Transistors, Self-Aligned Contacts and High-Density MIM Capacitors”, to be presented by Chris Auth in slot T15-2.

There was a fair bit of frustration at last year’s IEDM that there was no Intel paper on their tri-gate technology, although they had several others at the conference. The Intel folks I talked to said that there was reluctance to publish, since the other leading-edge semiconductor companies were not presenting – conferences were no longer the exchange of information that they have been in the past. I have to say I agree, some companies are keeping their technological cards very close to their corporate chests these days!

Also, no product was in the public domain at that point, though Intel claimed to be in production. By the time VLSI comes around in June, we should all be able to get Ivy Bridge based Ultrabooks, and we at Chipworks will have pulled a few chips apart.

In the paper the process is claimed to have “feature sizes as small as eight nm, third-generation high-k/metal gate stack technology, and the latest strained-silicon techniques. It achieves the highest drive currents yet reported for NMOS and PMOS devices in volume manufacturing for given off-currents and voltage. To demonstrate the technology’s versatility and performance, Intel researchers used it to build a 380-Mb SRAM memory using three different cell designs: a high-density 0.092- µm2 cell, a low-voltage 0.108- µm2 cell, and a high-performance 0.130-µm2 cell. The SRAM operated at 4.6 GHz at 1 V.”

The tip-sheet also posted the first Intel tri-gate images that I’ve seen in a while:

TEM images of Intel 22-nm PMOS tri-gate transistor (a) and source/drain region (b)

Here we are looking at sections parallel to the gate, across the fin. There is no scale bar, so fin width is an unknown; and the taper on the fin is a bit of a surprise. The top of the fin is rounded, likely to avoid reliability problems from electric field concentration at corners.

In the gate metal, there seems to be a layer of titanium nitride (TiN) above the thin dark line that is the high-k, so we can surmise that the PMOS work-function metal is TiN, as in previous generations. The gate fill itself is very black, so that appears to have been changed from the Al/Ti fill used before; possibly to tungsten or some other heavier metal.

The source/drain image confirms the use of epi, and the darker area is again likely SiGe, both for strain and resistance improvement. At the moment it’s hard to say if the taper is a function of manufacturing convenience (easier to etch?), or if there are some device physics advantages that improve transistor operation. We’ll see in June!

Dialog Semi Gets the Girls for Apple

Monday, April 2nd, 2012
Over the years we have looked at a number of products from Apple, and in their mobile products we have seen a continuous series of design wins for power management chips from Dialog Semiconductor, all custom-made parts since they have not been in their normal product listings. 

One of the distinguishing features of each part has been the code names Dialog has used for them – as my colleague Jim Morrison has noted, they are all girl’s names starting with A! Now read on..

Contributed by Jim Morrison

When it comes to Apple, the letter “A” features very prominently at Dialog Semiconductor.

Why, you ask? Every time we take a look at the power management ICs in Apple products, we find another Dialog Semiconductor device that has been named with a female first name, beginning with “A,” as we previously blogged about with Dialog Semiconductor’s design win in the iPad 2.

Our most recent examination of the iPad 3 revealed Amelia in the PMIC for Apple’s newest tablet.


Amelia (D1974A) from the New iPad

Does Dialog like to code their products so that all devices developed for Apple begin with A? Does renowned secrecy at Apple require all suppliers to be so hush-hush that to avoid errors, they talk about Apple using code names? Or does the power management team at Dialog just have a thing for female first names beginning with "A"? Perhaps the design manager has a family of daughters that all have names beginning with A. My family is all names with J so it’s quite possible another family has all As.

The iPhone 3 and 3GS liked Amanda, the iPhone 4 and the iPad 1 liked Ashley (Dialog Semiconductor D1815A), the iPhone 4s has Angelina, Dialog Semiconductor D1881A (my favourite), the iPad 2 has Alison (Dialog Semiconductor D1946A), and now our iPad 3 has chosen Amelia.

Amanda (D1755A) from the iPhone 3 and 3GS



Ashley (D1815A) from the iPhone 4 and the iPad 1



Angelina (D1881A) from the iPhone 4S



Alison (D1946A) from the iPad 2

 These die markings are changing because the die design has changed to accommodate new power requirements as we went from A4 processors to A5 to A5X, and other modifications in products that required changes to the PMIC.

We will see if the series continues in the iPhone 5 expected in the next few months..