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Archive for March, 2012

Semicon China – SMIC Shows off 28-nm HKMG Development

Tuesday, March 20th, 2012
Another foundry goes gate-last

In the opening keynote at Semicon China today, Dr. Tzu-Yin Chiu, CEO of SMIC, gave a run-through of their technology portfolio, and in doing so let out a few details of their sub-40 nm process development.

SMIC’s Process/Application Portfolio

It appears that they are actually shipping some 40-nm pilot product for revenue, and to keep the ARM-world happy, they will have Cortex A9 cores running at 1.2 GHz by the end of the year.

Snapshot of advanced nodes at SMIC

Scheduled for mid-2013, their 28-nm offering will be both high-k, metal gate and poly/SiON, and feature one of the smallest SRAM cell sizes to date.

SMIC’s 28-nm schedule

The images are all distinctly fuzzy thanks to the challenges of using a phone camera at some distance from a dimly-lit screen, but they show what I’m talking about. It appears that the gate-last structure has more in common with TSMC’s 28-nm structure than Intel’s 32-nm, and also that the NMOS and PMOS labels have been reversed.

SMIC 28-nm transistors and SRAM cell

In all the other gate-last HKMG transistors we have seen, the thick TiN and Ta layers are in the PMOS (you have to squint to distinguish them in this image, but they are there), and I wouldn’t expect SMIC’s to be any different. We can also see the tell-tale notch at the base of the transistors that indicates that the gate dielectrics were formed before the dummy poly gate was put down.  At less than 0.13 sq. microns the SRAM cell is the smallest that I know of – TSMC is 0.15, and Intel 0.17 sq. microns.

Just for comparison, here’s a pair of composite images of Intel’s 45-nm transistors and TSMC’s 28-nm transistors. You can clearly see the notches at the bottom of the gate structures that I refer to above.
Intel 45-nm transistors (left) and TSMC 28HPL transistors

The inclusion of a poly/SiON variant (presumably low-power) at 28 nm puts them on a par with TSMC and UMC, and leaves GLOBALFOUNDRIES as the only major foundry without an announced non-HKMG LP process at that node. If the rumours about GloFo second-sourcing the Qualcomm S4 (currently on TSMC’s poly/SiON 28LP line) are true, presumably they’ll have to develop one!

GloFo’s FinFETS are Better than Intel’s! Musings from CPTF

Sunday, March 18th, 2012
This confident statement came from Subramani (Subi) Kengeri of GLOBALFOUNDRIES (GloFo) during the panel session in the GloFo/IBM/Samsung Common Platform Technology Forum (CPTF), held Wednesday in the Santa Clara Convention Center. I’m currently on one of my periodic road trips, and this one has given me the chance to sit in on the CPTF – last year I had to make do with the online version.

Towards the end of the panel discussions, the host, Jaga Jagannathan of IBM, asked Subi “How do you stack up against Intel? – especially in the SoC/smartphone space?” This clearly took Subi by surprise, but after some preamble, he focused on FinFET development, which AMD, then GloFo, have been working on for the last ten years.  In conjunction with customer input, they have been focusing their finFET efforts to optimise the (14 nm) process for mobile SoCs. He said that this was what would differentiate them from Intel, and in that space “We believe we have a much better finFET, that is optimised for mobile SoCs”.

CPTF panel session. Jaga is on the left, and Subi third from the right.  Source: Common Platform

Of course time will tell, and the CPTF 14-nm process will likely not show up for three or four years, while we are waiting for Intel’s imminent launch of their trigate product.

The panel session has been put online, so you can see it by going here, register if you need to, then select Agenda and click the relevant link; if you want to see this particular Q & A, move the slider to the 52:30 timepoint.

Also during the discussion Subi stated that GlobalFoundries is in production for 32-nm HKMG, and running the full flow of the 20-nm (gate-last) process in their Malta NY fab.

Earlier in the day he had given one of the keynote talks, and it was then that he gave the logic for the move to finFET at 14-nm that was a major theme of the day.  It boils down to the fact that by the time you get to the 20-nm node, there are no more knobs to turn to crank up the performance of a transistor.  In order to mitigate the short-channel effects and increase drive current, a 3D fully-depleted structure is needed. GloFo regards the mobile sector as one of the big drivers for leading-edge process development these days, so their finFET efforts have been focused in the mobile SoC arena, with a multiple Vt process in development.

Another nugget from the day was the public announcement that Samsung is in full production with their 32-nm HKMG process, and it appears in Austin as well as Korea.  I was hoping that we might see it in the new iPad, but we’ve now confirmed that the A5x chip is 45-nm. I guess we’ll have to wait for one of the new phones or tablets that will be out soon. Actually, that includes TVs too – Samsung had a TV with gesture recognition on the show floor, powered by a 32-nm HKMG processor, and that’s due out next month as well.

The following day I was at an Intel analyst meeting, but that’s under NDA so I can’t say too much; but it’s not letting too much out to say that it reinforced their messages from CES and the Mobile World Congress that there will be a big push on Ultrabooks and mobile phones.  Next month expect a huge marketing campaign for Ultrabooks – it was described as “epic” and “cinematic” at CES. Even now we’re seeing all sorts of product announcements by the OEMs, including plenty with the 22-nm Ivy Bridge chip inside.

At the moment I’m in Shanghai taking in the China Semiconductor Technology International Conference and Semicon China. I’m presenting on “Recent Innovations in Leading-Edge Silicon Devices”; hopefully it will get a good reception. And we’ll see if there’s anything blog-worthy this week. In the meantime I tweet @ChipworksDick if anything is noteworthy.