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XPoint NVM Array Process Engineering

Wednesday, October 18th, 2017


By Ed Korczynski, Sr. Technical Editor

Now that TECHINSIGHTS has published a teardown of a 3D XPoint array, we have seen cross-section transmission electron micrographs (TEM) of the device. From first principles of process engineering, we can make educated guesses as to the process flows and challenges in creating this type of non-volatile memory (NVM) integrated circuit (IC). Evolution of device technology over more than fifteen years has resulted in cross-point arrays connecting precise stacks of chalcogenide materials. Intel with “Optane” and Micron with “QuantX” branded ICs can now claim success in commercializing what has always looked good in R&D but was notoriously difficult to make in high-volume manufacturing (HVM).

Figure 1 shows the TEM cross-section, parallel to the wordline direction, of a XPoint memory cell array taken from an Intel Optane product. There are two levels of cross-point cell-stacks, connected in the middle by bitlines (orthogonal to the wordlines). The upper- and lower-wordlines have been analyzed as tungsten (W) metal with tungsten-nitride (WN) barriers. The memory cell material is a variant on a germanium-antimony-teluride (GeSbTe or “GST”) chalcogenide glass, while the selector material is made with arsenic-silicon-germanium-selenide.

Fig. 1: Cross-section TEM of Intel XPoint NVM array in the wordline direction, showing two levels of memory cell stacks separated by bitline arrays. (Source: greyscale image by TechInsights, color commentary by Ed Korczynski)

Details about the device architecture and memory circuitry are included in the Solid State Technology online blog post by TechInsights’ senior technical fellow Dr. Jeongdong Choe, “Comparing XPoint memory architecture with NAND and DRAM products”. In his presentation at the 2017 Flash Memory Summit, Choe disclosed that the composition of the memory material is Ge0.12Sb0.29Te0.54:Si0.05 and the selector material is As0.29Si0.17Ge0.10Se0.44 while there have been no public mentions yet of what materials are used as buffers to electrodes.

As explained in the Ed’s Threads blog post on June 22nd of this year under the title “PCM + ReRAM = OUM as XPoint,” there has been confusion regarding used of Phase-Change Memory (PCM) material in a device that has a completely different architecture, different switching mechanism, and different performance than what are now known as standard PCM ICs. In standard PCM chips, high current-flow through a bit cell heats up a small mass of material until it changes phase (from crystalline to amorphous or vice-versa). In XPoint arrays, a small current-flow through a bit cell causes ions and atoms to re-arrange following voltage potentials until it changes resistivity, while it is not yet public knowledge how much change happens in material phase. Intel has said that the resistance change is not due to conductive “filament” formation in the GeSbTe:Si but due to some change in the “bulk” of the material.

Processing Speculations

From a HVM perspective, all cross-bar memory architectures share similar constraints and opportunities to design for relatively low-cost and high-yield:

1)     Use PVD blanket layers of complex material stacks as memory and selector and buffers,

2)     Use lithography to mask memory cells in a regular two-dimensional array,

3)     Use ion-beam or chemically-neutral plasma to etch pillars of complex material stacks,

4)     Use ALD/CVD and spin-on-dielectrics to gap-fill electrical isolation around pillars, and

5)     Use dielectric CMP to prepare for metal deposition.

Physical Vapor Deposition (PVD) or “sputtering” processing is based on sublimating a solid material “target” inside a vacuum chamber, which provides a relatively fast and inexpensive way to coat surfaces. Thickness uniformity is typically excellent wafer-to-wafer, while within-wafer uniformity is controlled by process chamber and target geometries. The major concern with PVD using multi-component targets—such as the four element GeSbTe:Si—is that different elements sublimate at different rates such that targets “age” and experience slight predictable composition changes over time. PVD target aging can be compensated for by cleverly varying the ratio of the different elements through the thickness of the target.

When integrating PCM materials into NVM devices, the ability to use a blanket 2D PVD deposition is an inherent advantage over ALD into nano-scale 3D features:  faster, cheaper, and potentially more repeatable if target aging can be managed. Patterning of the memory cell stack requires excellent control over ion directionality to prevent sidewall erosion within the material stack. As can be seen in Figure 1, the sidewalls of the GST:Si are slightly recessed from the thin dark layers directly above and below, indicating a well-controlled process with relatively higher removal rate during etching/milling.

Dielectric gap-fill into what appears to be ~10:1 aspect-ratio features is certainly one of the integration challenges of this process flow. The cross-section shows at least one conformal barrier layer is used in the dielectric isolation between array elements and between bitlines. Dielectric ALD is likely used for barrier formation, while spin-on dielectric (SOD) technology likely provides the gap-filling capability. If the metal interconnects for the CMOS circuitry below the array are built using copper, then a 400°C upper limit on process temperatures would be required for all array fabrication.

Future R&D

Milind Weling, expert in materials/device innovation and senior vice president of programs and operations for Intermolecular, presented at the 2017 Flash Memory Summit on the company’s ability to accelerate the pace of R&D experimentation for the complex materials stacks needed in XPoint memory arrays. In an exclusive interview with SemiMD, Weling discussed the inherent challenges of finding the ideal material within a multi-element compositional space.

“We’ve been working on selectors, and a single-element material is almost useless. What you need is at least a binary, maybe a quaternary, and some people experiment with targets composed of up to seven elements! Once we find a composition that is interesting in our R&D tool, our customers create large targets for their HVM tools.” Figure 2 shows a wafer with 28 isolated circular regions within which different PVD compositions can be independent controlled in a custom R&D tool made by Intermolecular. This tool allows a complete design-of-experiments within a ternary compositional space to be run on a single 300mm-diameter silicon wafer.

Fig. 2: Site-isolated circular regions on a 300-mm silicon wafer A) can each have a different composition within B) a ternary phase diagram when deposited in a special PVD R&D tool. Chalcogenide alloys explored as memory and selector materials in cross-bar NVM arrays may have more than three elements. (Source: Intermolecular)

The materials stack is necessarily complex to be able to form chalcogenide-based NVM cells, and even more complex when buffers are added to allow for integration with CMOS-compatible materials. “Each memory cell is two electrodes sandwiching a GST-type of material, and the selector is two electrodes with one ‘magic’ layer,” explained Weling. “Except for the novel ‘magic’ selector, most of the other materials used in the stack have precedent as unit-process steps in HVM of DRAM or NAND. The difficulty is in tuning the compositions of all layers simultaneously.”


[DISCLOSURE:  Ed Korczynski has no ongoing business relationship with nor owns any equity in Intermolecular.]