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Mentor Graphics U2U Meeting April 26 in Santa Clara

Monday, April 11th, 2016


Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.

Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high.  What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.

He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.

After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth?  What types of designs will be staffed and funded? Is it IoT?  Wearables?  Automotive?  Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.

Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.

These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.

A few of the highlights:

  • Oracle’s use of advanced fill techniques for improving manufacturing yield
  • How Xilinx built a custom ESD verification methodology on the Calibre platform
  • Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
  • Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
  • Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
  • Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
  • A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
  • How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
  • Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements

Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.

The day winds up with a closing session and networking reception from 5:00-6:00pm.

Registration is from 8:00-9:00am in the morning.

Packaging Conference Addresses Challenges, Opportunities in New Technologies

Friday, December 18th, 2015


By Jeff Dorsch, Contributing Editor

On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.

The day began with Pioneer Awards presented to Mitsumasa Koyanagi of Tohoku University and Peter Ramm of Fraunhofer EMFT. Those two men then gave talks on their involvement in 3D packaging technology over the decades.

“It started with DRAM in 1974,” Koyanagi recalled.

Ramm reviewed various European initiatives in the field, including the development of InterChip Vias (ICVs), a precursor to through-silicon via (TSV) technology, and the concept of known good die.

Suresh Ramalingam of Xilinx discussed the attributes of Silicon-less Interconnect Technology (SLIT), which the chip company developed in cooperation with Siliconware Precision Industries (SPIL), the IC assembly, bumping, and testing contractor.

“It’s still a silicon platform,” he pointed out. SLIT promises to connect multiple die in a package without resorting to TSVs. “Wafer warpage is a big issue,” Ramalingam noted.

Amkor’s Mike Kelly followed Ramalingam. “There’s a kind of upturn or resurgence in 2.5D, driven by high-bandwidth memory,” he said.

Amkor is offering the Silicon-less Interposer Module (SLIM) as its TSV alternative technology, according to Kelly, while also providing Silicon Wafer Integrated Fan-out Technology (SWIFT) as another packaging alternative to TSV-based interconnections.

KC Yee of TSMC, filling in for an absent presenter, spoke at length about the foundry’s Integrated Fan-Out (InFO) wafer-level packaging technology. “InFO eliminates silicon, TSVs, interposers,” he said. At the same time, InFO “reduces cost,” he asserted.

DARPA’s Daniel Green spoke about the agency’s Diverse Accessible Heterogeneous Integration (DAHI) program, which succeeded its Compound Semiconductor Materials on Silicon (COSMOS) program.

He was followed by Augusto Gutierrez-Aitken of Northrop Grumman Aerospace Systems. “DAHI is not in competition with CMOS,” he said. NGAS is developing a foundry for heterogeneous integration projects, inviting in companies and universities to participate in the research and development.

Teledyne Scientific’s Miguel Urteaga spoke about his company’s CS-STACK 3D stacking chip program. “We’re looking to get the highest III-V performance we can,” he said.

TSMC Forum Emphasizes Industry Collaboration

Thursday, September 17th, 2015


By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing kicked off its Open Innovation Platform (OIP) Ecosystem Forum with thanks – not for another beautiful day in Silicon Valley, but for the collaborative work it does with its customers, suppliers, and other industry partners.

Rick Cassidy, the foundry’s senior vice president and president of TSMC North America, kicked off the all-day event in Santa Clara, Calif., saying he wanted to debunk the myth of the “lone creative genius” in the chip business. “It is a lot of geniuses working together,” he said. “Innovation happens collectively.”

While there has been much attention paid to the slowing growth in the smartphone market, mobile technology will continue to be a significant driver for the semiconductor industry, according to Cassidy. He reviewed the areas of mobile technology, the Internet of Things, and automotive electronics.

“IoT will require an incredible amount of interconnection technology,” Cassidy said.

Between IoT and automotive tech, there will be “a very significant amount of data that’s going to be needed to be stored and processed,” he added.

Cassidy emphasized TSMC’s relations with its many collaborators, large and small. “We’re a pure-play foundry,” he said. “We do not have any products.”

He added, “Nobody does yield better than TSMC.”

Cassidy noted that TSMC will spend more than $2.2 billion this year on research and development, compared with more than $1.9 billion last year. The foundry’s capital expenditure budget for 2015 is $10.5 billion to $11 billion, up from $9.5 billion in 2014, he added.

The opening session also heard from Jack Sun, TSMC’s vice president of R&D and chief technology officer, and Cliff Hou, vice president of the R&D design technology platform, as well as executives of Avago Technologies and Xilinx, two TSMC customers.

3D ASIP: “It’s Complicated”

Monday, December 15th, 2014


By Jeff Dorsch, Contributing Editor

The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status: “It’s complicated.”

They also could be summed up in one word: Progress.

This year has seen tremendous progress in implementation of 3DIC technology, according to speakers at the 11th annual conference, held in Burlingame, Calif. Those who have been touting and tracking 3D chips for years are looking forward to the 2015 introduction of Intel’s Xeon Phi “Knights Landing” processor for high-performance computing, which will incorporate the Hybrid Memory Cube technology in the same package as the CPU.

Activities began Wednesday, December 10, with a preconference symposium on “2.5/3D-IC Design Tools and Flows” and “3D Integration: 3D Process Technology.” Bill Martin of E-System Design kicked off the program with a presentation on path finding, a topic addressed several times over the next two days. He emphasized that preparing for a chip design project, such as choosing the right tools, is as important as the design and implementation phases when it comes to embracing 3DIC technology.

John Ferguson of Mentor Graphics later said there is “an infrastructure problem” in the semiconductor industry when it comes to process design kits (PDKs) for 2.5D and 3D chips. Taiwan Semiconductor Manufacturing has collaborated with Mentor and other leading suppliers of electronic design automation tools to offer PDKs to TSMC foundry customers, yet the next step must be taken to have outsourced semiconductor assembly and test contractors provide packaging PDKs.

Phil Garrou, a senior consultant for Yole Developpement, said 2014 has witnessed significant progress in implementation of 3DIC technology. “We no longer need to prove performance,” he said. “The remaining issue is cost.”

Several speakers addressed the topic of the Internet of Things and how it involves 3DICs on the first day of the conference. Steven Schulz of the Silicon Integration Initiative (Si2) said 3D chip designers should think of their products not as system-on-a-chip devices, but system-on-a-stack.

Yole’s Rozalia Beica said predictions that the Internet of Things market will be worth trillions of dollars in 2022 are “overoptimistic” and that “optimism is higher than current investment.” Yole looks for the market in IoT sensors to be worth $400 billion in 2024, she said.

Samta Bonsal of the GE Software Center spoke on the Industrial Internet. “That world is huge,” she said, and predicted it will have “a bigger impact” than consumer-oriented IoT applications. Gartner says the market for all IoT chips will be worth $7.58 billion in 2015, she noted. The market research firm also forecasts that 8 billion connected devices will be shipped during 2020, encompassing 35 billion semiconductor devices produced on 6 million wafers.

E. Jan Vardaman of TechSearch International presented a lively review of 3DIC technology, past and present. “There’s been a lot of good progress with TSV (through-silicon vias), enabling us to improve the process,” she said. Still, 3DIC has been a long time in coming, noting that Micron Technology began research and development on DRAM stacking a dozen years ago and Xilinx initiated development of a silicon-based interposer to be used with TSVs in 2006, six years before it was able to offer a field-programmable gate array with such technology, manufactured in volume by TSMC.

Dyi-Chung Hu of Unimicron looked past the silicon interposer to the era to using glass for interposers and substrate core materials. Glass has a low coefficient of thermal expansion compared with silicon, he noted, and is very flat. Its chief drawback is its brittleness, according to Hu.

Michael Gaynes of IBM’s Thomas J. Watson Research Center reported on his company’s two ICECool projects for the Defense Advanced Research Projects Agency, developing 3DICs that could run cooler in data-center servers.

The last day of the conference coincided with a convention devoted to the Star Trek television series in the adjacent hotel ballroom. Attendees dressed as Klingons and starship crew members mingled with the 3DIC technologists in the hotel lobby, all dreaming and thinking about the future.

Wafer-level packaging of ICs for mobile systems of the future

Monday, May 5th, 2014

Ed Korczynski, Senior Technical Editor, Solid State Technology/SemiMD

The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world. Integration of heterogeneous circuit functions—such as micro- and graphics-processing, field-programmable gate array (FPGA) logic, dynamic and static memory, radio-frequency (RF) and analog, and sensing and actuating—may also be needed at the package-level to be able to deliver complete systems (Figure 1).

FIGURE 1: Heterogeneous System-in-Package (SiP) as an extension of proven flip-chip (FC) packaging technology. (Source: Amkor)

In particular, electronic systems for high-growth mobile applications require low-power and low-volume per element which dis-allows circuit integration at the printed-circuit board (PCB) level. Instead, heterogeneous integration must occur as either a system-in-package (SIP) or a system on-chip (SOC). Dr. Eric Mounier of Yole Développement, presented at the recent European 3D TSV Summit 2014 held in Grenoble, and showed Yole forecasts that total world-wide semiconductor IC wafers packaged at the wafer-scale will be 19% this year, raising to 20% in 2015.

One way of looking at the history of the IC industry is to examine the dynamic between SIP and SOC approaches. New functionalities tend to be first integrated into hardware as dedicated additional chips, to be connected in to the rest of the system as part of a PCB or SIP. Since different functionalities often require different fab processes, it is generally less expensive at the chip-level to divide functionalities into different chips, but then the packaging costs tend to be higher. Relatively low-volume parts may be most economically delivered as SIP, while higher-volume parts can often justify the additional design and test expenses of delivering the same functionality as a single SOC.

The other major reason to go with an SIP is to improve the yield of large area chips at the leading edge of fab processing. Since defects/area tend to be relatively high with a new fab process, very large chip designs will have relatively low yield at first but then will improve as the fab learns how to reduce both random and systematic yield limiters. The recent excellent example of this trend is the Xilinx Vertex-7 FPGA which splits the chip into four sub-chips and then uses a silicon interposer for SIP re-integration. We may expect that a next-generation of the product would be build in a single SOC after the yield improves, at which point Xilinx would be expected to extend the product line with additional functionality added in using multi-chip SIP.

Fan-Out WLP

Steffen Kroehnert, director of technology for Nanium S.A., gave a recent presentation at SEMICON/Singapore 2014 entitled “Wafer Level Fan-Out as Fine-Pitch Interposer.” Fan-In WLP uses layout package connections within the chip area, and when the scale and count of on-chip bond pads does not match with standard packaging scales, a Re-Distribution Layer (RDL) of metal interconnect  can be used to Fan-In to ball-grid or pillar-grid arrays (BGA/PGA) within the chip-area. However, when the needed number of connections cannot be made within the chip area, packaging filler materials can be used to provide physical area adjacent to an original chip such that package connections can be arranged to Fan-Out WLP solutions use “Fan-Out” out from the chip center when seen from above.

Chip-Package-Board simultaneous co-design and co-development are becoming import instead of serial work according to Kroehnert. The penalty for re-design costs and losing strategic time-to-market for a new SiP is too high for allow for iterative R&D, such that products must be co-designed properly the first time.

FO-WLP Leveraging PV Fab Tricks

Deca Technologies, the electronic interconnect solutions provider to the semiconductor industry owned by Cypress Semiconductor, recently announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca’s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.

Leveraging volume production technologies from leading silicon PV manufacturer SunPower Corp., Deca quickly achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using conventional approaches to WLCSP manufacturing. Deca claims that other FO-WLP technologies suffer from inherent manufacturing and reliability issues due to discontinuity at the silicon:mold-compound interface, which are avoided by the company’s use of copper-pillars and an over-mold approach (Figure 2).

FIGURE 2: Cross-section of edge of FO-WLP using Cu-pillars and over-mold approach. (Source: Deca Technologies)

Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio, and power management components for mobile markets. Demand fluctuations in these markets can lead to challenges in managing inventories. “Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain.”

“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”

FO-WLP for the future

As thoroughly covered in our sister blog Insights From The Leading Edge, STATSChipPAC (SCP) recently announced FlexLine™ FO-WLP. The FlexLine flow dices and reconstitutes incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size. The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process (Figure 3). Single and multi die fan-out package solutions have been in high-volume manufacturing since 2009 with more than a half-billion units shipped.

FIGURE 3: Schematic cross-sections of various Fan-Out WLP packages. (Source: STATSChipPAC)

Earlier this month, Digitimes provided a brief English translation of some Chinese-language Economic Daily News (EDN) saying that Taiwan Semiconductor Manufacturing Company (TSMC) plans to increase IC packaging revenues to US$1 billion in 2015 and to US$2 billion in 2016. TSMC co-CEO CC Wei reportedly acknowledged that the production cost for silicon-substrate SIP (TSMC’s variant termed “chip-on-wafer-on-substrate” or “CoWoS”) packages is relatively high, and so the world’s leading IC foundry intends to invest in FO-WLP technologies to be able to offer advanced packaging at a reduced price.

Wafer-level packaging continues to gain slow IC market share, and novel fan-out redistribution drives the need for improvements in existing packaging materials within tight cost and reliability constraints. With silicon-interposers and copper-interconnects part of WLP technology, the lines between chip and package have never been less clear. Managing all of this complexity is business as usual when designing mobile systems of the future.


3D EDA brings together proven 2D solutions

Friday, March 14th, 2014

By Ed Korczynski, Senior Technical Editor, SST/SemiMD

With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

However, 3D ICs will likely always cost more than doing it in 2D, due to more step being needed in manufacturing. A recent variation of 2D IC packaging with some of the benefits of 3D is the use of silicon interposers containing TSV.

Current state-of-the-art electronic design automation (EDA) tools exist to handle complex IC systems, and can therefore handle complex 3D designs as long as the software has the proper inputs from a foundry’s Process-Design Kit. Figure 1 shows the verification flow for a multi-chip system using the “3DSTACK” capability within Mentor Graphics’ Calibre platform. Leading IC foundries GlobalFoundries and TSMC as well as 3D IC specialty foundry Tezzaron have all qualified 3DSTACK for their 2.5D and 3D design verifications.

FIGURE 1: “3DSTACK” functionality integrates with existing 2D Design Rule Check (DRC) modules within the Calibre platform. (Source: Mentor Graphics).

EDA tools have evolved in complexity such that Design-For-Test (DFT) methodologies and technologies now exist to tackle 3D ICs. Steve Pateras, product marketing director, DFT, Design to Silicon Division of Mentor Graphics advised, “If you’re stacking multiple die together, you need to work with known good die. The ROI basically changes for stacking, such that you need to get into a different regime of test.” In a die stack we have to think about not just known good die, but die known to be good after they are stacked, too. The latter condition mandates standards for DfT to allow test signals to flow between layers.

The IEEE 1838 working group on 3D interface standards is intended for heterogeneous integration, allowing for different IC process technologies, design set-ups, test, and design-for-test approaches. The standard defines test access features that enable the transportation of test stimuli and responses for both a target die and its inter-die connections.

Figure 2 shows the extra die interfaces that must be physically verified within a 3D IC system stack. Die interfaces can be mis-aligned due to translation or rotation during assembly, and with die from different fabs at different geometries it can be non-trivial to ensure that the rights pins are connected.

FIGURE 2: Schematic cross-section of a 3D IC system showing the die interfaces that require new Physical Verification (PV) checks. (Source: Mentor Graphics).

3D memory stacks are somewhat in their own category since they are primarily designed and manufactured by IDMs, though often with a logic layer on the bottom they are mostly homogenous, and since memory usually runs cooler than logic they generally have no cooling issues. For these reasons 3D memory stacks using wire-bonds have been in volume production for years, Micron leads the development of the Hybrid Memory Cube using TSV, and Samsung leads in growing multiple memory layers on a single silicon chip.

Future Demand for 3D Logic

So far, the only known commercial logic chips shipping with TSV are the Xilinx Virtex-7 product, where four 28nm node FPGAs (as reported by Phil Garrou in 2011 in his IFTLE blog) are connected to a silicon interposer. Xilinx has shown that much of the motivation for using 2.5D packaging was to improve yield when working with the maximum number of logic gates in the smallest available process node, and when foundry yields improve with learnings for a given node we would expect that the FPGA would be made using a single-chip 2D solution.

It appears that 2.5D is not so much a stepping-stone to 3D, as it is a clever variant on established 2D advanced packaging options. Silicon interposers with TSV offer certain advantages for integration of high-speed logic in 2D, but due to relatively greater cost compared to other WLP methods will likely only be used for high-margin parts like the Virtex-7. Also, Out-Sourced Assembly and Test (OSAT) companies have been offering both “fan-out” and “fan-in” wafer-level packaging (WLP) options, and heterogeneous integration can certainly be done using these approaches. “We have customers planning on using interposers, but they’re planning on lower-cost substrates,” commented Michael Buehler-Garcia, senior marketing director for Calibre, Design to Silicon Division of Mentor Graphics.

If high volume CMOS logic will always be most cost-effectively integrated in a single 2D slice of silicon, and heterogeneous integration of CMOS can be done in 2D using FD-SOI substrates, then what remains as the demand driver for future 3D logic stacks? What logic products require heterogeneous integration for basic functionality, would be band-width-limited by 2D packages, and also are anticipated to be shipped in sufficiently high-volume to allow for amortization of the integration costs?

Several vendor have recently launched 100G C form-factor pluggable (CFP) modules to increase speeds while reducing costs in communicating between data servers. ClariPhy produces a CFP SoC using a 28nm CMOS process that is packaged with laser diode chips from Sumitomo Electric Industries’ (SEI). “By combining ClariPhy’s SoC with SEI’s world class indium phosphide optics technology and deep experience in volume manufacturing of pluggable optical modules, we will deliver the benefits of coherent technology to metro and datacenter networks,” said Nobu Kuwata, general manager of the Technology and Marketing Department of Sumitomo Electric Device Innovations (SEDI). “We will provide first samples of our 100G coherent CFP next quarter.”

Even greater cost and power savings could derive from a revolution in the interconnections used not just between servers but inside the server farms that provide the ubiquitous “cloud computing” we are all coming to enjoy. “It’s still a couple of years out, but we’re doing research on DARPA projects now,” says Buehler-Garcia in reference to work Mentor Graphics is doing to bring the automation of its Calibre platform to this application space.

The EDA industry’s ability to handle system-on-chip (SoC) and system-in-package (SiP) layouts means that the differences between designing for 2D, 2.5D, and 3D logic should be minimal. “We don’t charge extra for 3D,” explained Buehler-Garcia, “it’s already part of the deal.” ‑E.K.

Blog review February 3, 2014

Monday, February 3rd, 2014

Ira Feldman provides an interesting perspective on last month’s SEMI Industry Strategy Symposium. He notes that numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved.

“Long live the FinFET,” says Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc. In this blog post, he describes how designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements, he writes.

Adele Hars of Advanced Substrate News reports that STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.

Phil Garrou finishes up his review of the IMAPS 2013 meeting, with an analysis of Xilinx/SPIL results from their 2.5D 28nm FPGA program, a review of the Copper TSV work presented by Nanyang/IME, Canon’s FPA-5510iV and FPA-5510iZ TSA steppers designed to support high density processes and the implementation of 2.5 & 3D technology, and a report on the embedded technology being developed by AT&S.

The Week in Review: Jan. 17, 2014

Friday, January 17th, 2014

Macroeconomic and microelectronic industry growth opportunities and innovation challenges underscored diverse perspectives from analysts, economists, technologists, semiconductor manufacturers and supply chain executives speaking at the SEMI Industry Strategy Symposium (ISS) that was held this week.  The executive conference offers the year’s first strategic outlook for the global microelectronics manufacturing industry and offered encouraging forecasts buttressed by the silicon requirements for the pervasive computing era.

The market for semiconductor packaging materials, including thermal interface materials, is expected to maintain its $20 billion value through 2017, despite shifts away from the use of precious metals such as gold in wire bonding.

Semiconductor Research Corporation, a university-research consortium for semiconductors and related technologies, has launched a significant new initiative on Trustworthy and Secure Semiconductors and Systems. The first major phase of T3S research is a $9 million joint effort over the next three years with the National Science Foundation (NSF) focused on Secure, Trustworthy, Assured and Resilient Semiconductors and Systems (STARSS).

SEMI this week announced that two teams — from the University of Florida and Xilinx — are recipients of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer and the University of Florida team was recognized for developing a cornerstone of the modern era of computational modeling of CMOS fabrication process with the Florida Object-Oriented Process Simulator, FLOOPS.  Liam Madden  accepted the award on behalf of the Xilinx team, and Mark Law and Kevin Jones (University of Florida) accepted their awards during a banquet at the 2014 SEMI Industry Strategy Symposium (ISS) yesterday in Half Moon Bay, Calif.

ARM and global semiconductor foundry UMC this week announced an agreement to offer the ARM Artisan physical IP platform along with POP IP for UMC’s 28nm high-performance low-power (HLP) process technology. UMC and ARM will provide an advanced process technology and comprehensive physical IP platform under this agreement, with the goal of supporting customers targeting a wide range of consumer applications such as smartphones, tablets, wireless and digital home services.

The Week in Review: Nov. 15, 2013

Friday, November 15th, 2013

SEMI Standards task forces are working on encouraging the industry to collaborate on key issues like the technical parameters for 450mm silicon wafers, physical interfaces, carriers, assembly and packaging. To date, SEMI has 13 task forces working on 450mm and has published nineteen (19) 450mm standards with 14 more in the pipeline. Here’s an update on the newly-published SEMI 450mm specifications as well as the other 450mm SEMI Standards.

Xilinx announced  first customer shipment of the semiconductor industry’s first 20nm product manufactured by TSMC, and the PLD industry’s first 20nm All Programmable device.  Xilinx UltraScale devices deliver an ASIC-class advantage  with  the industry’s only ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite and recently introduced UltraFast design methodology. The UltraScale devices enable 1.5X – 2X more realizable system-level performance and integration for customers, equivalent to a generation ahead of the competition.

SEMI also announced this that the deadline for presenters to submit an abstract for the 25th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 28.  ASMC, which takes place May 19-21, 2014 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity.

FlipChip International announced the 100% acquisition of Millennium Microtech (Shanghai) – (MMS), a provider of fully integrated semiconductor packaging and testing services situated in the Zhang Jiang Hi- Tech Park, Pudong New Area, Shanghai, China. The MMS name will be changed to FlipChip International.

Tosoh Corporation announced today that Tosoh Group company Tosoh SMD, Inc., will implement a major expansion at its Grove City, Ohio, operations to develop, produce, and support physical vapor deposition (PVD) sputtering targets for the new 450mm wafer semiconductor market. The expansion is the biggest investment in Tosoh SMD’s history and is meant to position the company for the next generation products and technologies. It will include facilities, novel equipment and tools for manufacturing, and a sputter deposition tool for R&D and evaluation purposes. The first stage is slated to be ready by December 2014.

3D-IC Testing With The Mentor Graphics Tessent Platform

Thursday, June 20th, 2013

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time.

3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematech [1]. Interposers are providing the logical first step to industrialization of 3D based on through-silicon vias (TSV)s. The next generation of 3D integration incorporates TSV technology as the primary method of interconnect between the die.

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