By Mark LaPedus

In a major move, Intel is expanding its efforts in the foundry business. Altera has entered into an agreement for the future manufacturing of its FPGAs, based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant.

Until now, Intel has been a bit player in the foundry business. Now, the chip giant is on a direct collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC.

Intel has been ramping up its 22nm tri-gate technology for some time, with plans to deliver its 14nm process by year’s end. The chip giant has yet to describe the details about its 14nm tri-gate technology.

Altera elected to skip Intel’s existing 22nm process. Instead, the company will move directly to Intel’s 14nm finFET technology, thereby leapfrogging its competition, namely Xilinx.

The move also represents a major switch in strategy at Altera. Prior to today’s agreement, Altera was exclusively procuring foundry wafers from Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). But TSMC and other foundries are lagging behind Intel in finFET development. In fact, Intel has a two- to three-year lead over its rivals in finFETs, prompting Altera to look at Intel as a foundry partner. Others could also follow suit.

Still, TSMC is Altera’s primary foundry, according to Altera. TSMC will continue to supply a wide array of processes to fulfill Altera’s product portfolio, including the soon-to-be-released 20nm products, existing mainstream products, and long-lived legacy components. Altera is fully engaged with TSMC on developing products based on next-generation process technologies.

But now, Altera is reaching out to Intel to get a jump in the finFET race. “Altera’s FPGAs using Intel 14nm technology will enable customers to design with the most advanced, highest-performing FPGAs in the industry,” said John Daane, president, CEO and chairman of Altera. “In addition, Altera gains a tremendous competitive advantage at the high end in that we are the only major FPGA company with access to this technology.”

Patrick Dorsey, senior director of product marketing for Altera, said the FPGA chip maker decided to skip Intel’s 22nm tri-gate process, because Intel’s 14nm technology represents a “better match” for Altera’s future product roll out. “This represents a giant leap in terms of capabilities,” Dorsey said.

Analysts agreed. “In our view, the move is mutually beneficial to Altera and Intel,” said Doug Freedman, an analyst with RBC Capital Markets.  “On the Altera side, the company is now on-track to reach sub-20nm before competitor Xilinx.”

Freedman added: “On the Intel side, we believe this is the first in what is likely to be more tier-one customer announcements in the future.” Indeed, Intel is talking to Apple about a similar arrangement.

“We look forward to collaborating with Altera on manufacturing leading-edge FPGAs, leveraging Intel’s leadership in process technology,” said Brian Krzanich, chief operating officer at Intel.  “Next-generation products from Altera require the highest performance and most power-efficient technology available, and Intel is well positioned to provide the most advanced offerings.”

Until now, Intel was only working with smaller fabless companies in the foundry business. For example, Achronix Semiconductor last week officially began shipping the first in a family of devices based on Intel’s 22nm finFET technology. Achronix’ FPGAs are built on a foundry basis by Intel, as part of a major agreement announced in 2010. Another company, Tabula, will also have its 22nm FPGAs made on a foundry basis by Intel.  And flow processor vendor, Netronome, is also having its 22nm products built by Intel.

Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

By Mark LaPedus
Is China set to bail out a U.S. government technology darling? Two Chinese automotive companies, Geely and Dongfeng Motor, are reported to have bid between $200 million and $350 million for a majority stake in Fisker, the maker of plug-in hybrid cars. If that happens Fisker—which has $192 million in U.S. federal government loan guarantees—could be headed to China, according to Lux Research.

Over the years, Apple has moved deeper into IC design. In an e-mail newsletter, Will Strauss, president of Forward Concepts, indicated that Apple could be expanding its efforts in wireless ICs, a move that might impact Broadcom, Qualcomm and others. “There is a rumor published in Israel that Apple will be designing its own baseband and Wi-Fi chips,” Strauss said. “When Texas Instruments dropped out of the cell-phone business, within a week about 100 of the former TI engineers in Israel were hired by Apple. Of course, Apple once hired a bunch of former VLSI Technology wireless engineers, but I understand that that operation came to naught. So, maybe Apple just wanted more engineering talent.”

In a separate research note, Doug Freedman, an analyst with RBC Capital Markets, said: “After talks with management dating back from CES to today (Feb. 25), we believe that Intel is becoming increasingly closer to inking a material foundry design win(s).” Intel is in consideration to be a potential foundry partner for Apple. “Intel’s foundry aspirations may come to light soon,” he said. Apple is also supposedly doing a 20nm foundry deal with TSMC.

Taking the process technology lead in the FPGA market, Achronix Semiconductor is shipping the first in a family of devices based on Intel’s 22nm finFET technology. Achronix’ FPGAs are built using Intel’s foundry services. Achronix says that it has a two- to three-year lead over Altera and Xilinx, which are still shipping 28nm planar devices. The event has prompted two questions. First, will Altera and Xilinx turn up the heat on their FPGA foundry partner, TSMC, to accelerate its finFET efforts? Or second, will Altera and Xilinx turn to Intel over time?

CEA-Leti will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding up the industrialization of the technology. Mentor Graphics, PhoeniX BV and Si2 will work together to develop a common reference platform. STMicroelectronics, Tyndall-UCC, Aifotec and others are also part of the group.

Mentor Graphics has expanded its automotive business unit by purchasing certain assets from MontaVista. This establishes Mentor as a bigger commercial provider of Linux-based automotive in-vehicle infotainment (IVI) solutions.

Mentor announced the 10.2 release of the Questa functional verification platform. In addition, Tesla Motors has standardized on Mentor’s Capital toolset for 12-volt electrical systems design.

With FD-SOI, STMicroelectronics said that application processors manufactured at its fab are capable of operating at 3 GHz.

Soitec and Sumitomo Electric have signed a licensing and technology-transfer agreement. Sumitomo will use Soitec’s Smart Cut technology to manufacture engineered gallium nitride (GaN) substrates. GaN substrates are used in high-performance light-emitting diode (LED) lighting applications.

GlobalFoundries announced enhancements to its 55nm Low-Power Enhanced (LPe) process technology platform. The so-called 55nm LPe 1V has been qualified with next-generation memory and logic IP solutions from ARM.

Are happy days here again for fab tool vendors? The book-to-bill ratio is above parity for the first time in recent memory. North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.14 in January, according to SEMI. This compares to a ratio of 0.92 in December.

Intersil cut its global work force by approximately 18%. This comes on the heels of the resignation of the company’s CEO.

Sony introduced the PlayStation 4, which is based on AMD’s single-chip, eight-core custom processor. The x86 processor, dubbed Jaguar, is a 28nm device built by TSMC.

Five IC suppliers are expected to hold one-third of 300mm wafer capacity in 2013, according to IC Insights. Samsung was by far the leader in 2012, having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.

Qualcomm dominated the LTE cell-phone modem market with a staggering 86% share in 2012, according to Forward Concepts. In total, Qualcomm shipped 47 million FDD-LTE cell-phone modems last year. Samsung followed with 9% of the shipments in 2012, while GCT Semiconductor managed to grab 3% of the market, primarily through LG handsets, according to the firm. Renesas Mobile and Nvidia-Icera each garnered 1% market shares.

The number of China Mobile 4G subscribers is forecast to reach 228.8 million in 2017, representing 52 percent of China’s 439.9 million total 4G users, according to IHS. In comparison, 4G users from China Unicom and China Telecom, the country’s two other major telecommunications operators, will number 114.4 million and 96.8 million, respectively.

By Mark LaPedus
The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.
FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments.

Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are separately developing 2.5D FPGAs, initially based more on homogenous devices. Both are also using Taiwan Semiconductor Manufacturing Co. Ltd.’s turnkey solution to integrate all or part of their 2.5D FPGAs.

Huawei is taking a different avenue, which is arguably more representative of the complex approach that many may take in their 2.5D efforts. The Chinese networking equipment giant is developing a heterogeneous 2.5D device that combines an FPGA from Altera and stacked DRAM from Tezzaron. The interposer comes from Singapore’s Institute of Microelectronics (IME). And fabless ASIC vendor eSilicon is handling the supply chain and integration process.

Putting the pieces together is expected to be a herculean effort. But having explored a multitude of options, Huawei decided to move down an arduous path—and for good reason. “The memory wall is a very serious problem,” said Anwar Mohammed, a senior staff scientist at Huawei. “The gap is becoming wider and wider. And all of the solutions we have for solving the problem are not working anymore.”

For the high-end networking space, Huawei sees a clear but challenging path to solve the problem. “We have to punch a tunnel through the memory wall,” Mohammed said. “For networking applications, 2.5D is the preferred solution.”

The roadblocks
The memory bottleneck and resistivity problems in planar devices have fueled the development of stacked 2.5D and 3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in 2.5D designs.

Mike Splinter, chairman and chief executive of Applied Materials, said the 2.5D/3D chip market represents a promising segment for the IC industry, but the business will take some time before it reaches mass production. “We’ve always said there will be a slow deployment of 2.5D,” Splinter said.

The 2.5D chip market is progressing somewhat faster than 3D. Several foundries and IC-packaging houses currently provide interposers and workable manufacturing flows to enable 2.5D designs. There are still some gaps in the technology, however.

“2.5D depends on having a stacked memory solution,” said E. Jan Vardaman, president of TechSearch International, a research firm. “The inability to obtain a memory stack is a gating factor. Some people also say the cost for 2.5D is too expensive.”

Test is also an important but sometimes overlooked part of the flow. “The test challenges for 2.5D are very similar to 3D. For die stacking, it is crucial to have each die pre-tested for KGD,” said Bassilios Petrakis, product marketing director at Cadence Design Systems.

“In the case of the interposer, the question often comes up as to whether it needs to be tested for connectivity upfront prior to bonding with other dies. There is also consideration for how to test partially populated interposers as well as multiple die stacks,” Petrakis said. “An example of that would be a logic die that talks to a Wide I/O DRAM and another logic die on top. If the bottom die of the interposer is the most expensive die, you may only want to attach it to an interposer with all other die attached that have been tested good so far. This may be the most economical way to produce good modules. Finally, all dies on interposers must have some form of a wrapper with boundary scan. We prefer the use of IEEE 1500-style wrappers, but we are also able to accommodate the simpler Wide I/O style boundary scan. Special I/O wrap test before die stacking/bounding can detect possible TSV shorts but not opens.”

Another challenge is to find a suitable manufacturing partner. In general, there are two schools of thought—turnkey versus a hybrid approach. TSMC and Samsung provide a turnkey solution, in which the companies provide both the front- and back-end work. In contrast, GlobalFoundries and UMC are sticking with their hybrid approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Both approaches have their advantages and disadvantages. In the turnkey approach, the foundry can assume the responsibility of the supply chain, thereby keeping costs and quality under strict control. The problem with the turnkey method is that some customers are nervous about handing over their sensitive front-end, assembly and test intellectual-property (IP) to a foundry, said Ajit Manocha, chief executive of GlobalFoundries. “We are not a closed fab,” Manocha said. “Customers prefer to take their proprietary information to the OSATS. We are not going to force customers to do the assembly with us.”

Taking the right path
As it turns out, each customer will choose its own path. To simplify its respective supply chains, Altera and Xilinx are working with a limited set of partners. Most others may end up dealing with a more complex supply chain.

Huawei, for example, is working with separate chipmakers, interposer suppliers, foundries, assembly houses and integrators. At present, Huawei is developing its 2.5D ASIC/FPGA device at IME, a Singapore R&D organization. IME has set up a complete front-end production flow using fab gear from Applied Materials. IME also developed its own interposer technology. IME is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

Huawei declined to comment on which foundry it will use once it moves into production, but the challenges are obvious. “This could be a logistics nightmare,” said Ron Leckie, president of Infrastructure Advisors, a consulting firm.

Unfazed by the challenges, Huawei believes it must move in a new and radical direction to address the memory bottleneck in the network. “At one time, when you went to a new node, your gains were pretty sharp,” said Huawei’s Mohammed. “Now, every time we go to the next node, the power becomes a challenge and you have to go with larger and larger die sizes.”

The current line of specialized networking memory chips and other components are unable to keep pace. “Commodity memory cannot handle it,” he said. “Serdes was able to help with the bandwidth at one time. But now, the gains are flatter.”

To solve the problem, the company evaluated several options. “A company like Huawei doesn’t jump into a technology. We have to go through many doors before we decide this is a technology we go after,” he said.

Last year, for example, Huawei looked at combining an ASIC and RLDRAMs in a 64mm x 64mm package, he said. After dropping that idea, the company looked at integrating those devices in larger substrates or smaller packages. Those options were scrapped. Then, it looked at combining a bare die FPGA and packaged memory in a $25 module. “It was not leading-edge technology,” he said. “Any one of our competitors could have picked it up.”

Finally, the company decided on 2.5D. 3D is more suited for mobile applications. “The size of our line cards is constant. We want to put more and more items on the line card to make it more functional and effective. 2.5D is a very powerful enabler for that,” he said. “Initially, this is going to be more expensive. But if you combined enough items, there is a strong potential for cost reduction. It also allows us a faster time to market.”

In Huawei’s proposed design, the FPGA from Altera and the memory stack from Tezzaron are situated on a silicon interposer. “Instead of 10 or 20 DDR DRAMs, all of this can be replaced by one Wide IO memory,” he said. “DDR memory performance is so slow. All of this goes away with Wide IO memory, which is only 12mm x 12mm.”

In total, the company’s proposed 2.5D device occupies less space. The bandwidth per watt is at least 30 times better than conventional approaches, he said.

To realize its design, the world’s largest networking equipment company must overcome some major hurdles, namely the KGD issues, the lack of EDA tools and the supply chain. “Hopefully, we can obtain known good dies and bare dies,” he said. “There is good work going on at Cadence, Mentor and others, but this is still an area of concern. There are also some business concerns like who’s responsible and who’s not responsible?”

Ultimately, to make 2.5D/3D a viable solution in the overall market, Huawei advocates another critical piece to the puzzle–collaboration. “We are advocating pre-competitive collaboration. Let’s makes sure the technology succeeds. When the technology can take care of itself, let’s start competing,” he added.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan.

SMD: What is ITRI doing in 3D TSVs?
Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was completed two years ago. We developed the process from the very beginning to the end. We don’t have products. We are demonstrating the feasibility for 3D TSVs.

SMD: What else is ITRI doing in the arena?
Lau: We also have a consortium call Ad-STAC (Advanced Stacked-System and Application Consortium). We have more than 22 members. We just develop the necessary technologies for 3D integration. The members are UMC, SPIL, Applied Materials, Brewer, Rambus, Cisco and others. In addition to that, we have some 80 people working on EDA. For 3D, EDA is very critical.

SMD: Where is the industry at with 3D TSVs?
Lau: For me, it’s still very early. You still have to bring the OEMs into the mix. The OEMs may say: ‘Oh, I’m interested.’ Then, you still have to wait three to five years. There are two different kinds of OEMs. One is consumer. 3D TSVs are still too expensive for them. However, it could be a different story for high-end, next-generation servers, networking and test and measurement gear.

SMD: Where is a good starting place for 3D?
Lau: Take the Hybrid Memory Cube Consortium. Several months ago, the group announced they would open up the spec by the end of this year. But that’s only for high-end servers, test and measurement, and networking. It’s for very high performance and not for the consumer. They may adopt 3D. But the Hybrid Memory Cube for mobile products? Come on. Of course, we hope 3D can be for the consumer market. In consumer, there are larger volumes.

SMD: What is the biggest challenge for 3D?
Lau: Cost. The consumer market is cost-driven. For the iPhone 5, the semiconductor bill of materials is less than $30. The ASICs and memory are less than $30. Now take Xilinx’s 2.5D FPGA. The CTO from Xilinx recently gave a keynote at Semicon West. His conclusion was that they need to reduce the cost. A 2.5D FPGA is still costly.

SMD: What are the manufacturing challenges?
Lau: Just to make the TSV is no more than 5% of the cost. But if you look at the other steps, you have temporary bonding, back grinding, and others. The biggest issue is thin wafer handling and temporary bonding/debonding. And then you need to debug it.

SMD: Who should make the TSVs? The OSATs or the foundries?
Lau: Xilinx is using 65nm technology for their 2.5D FPGAs. OSATs like ASE don’t have 65nm technology. If they did, they would become another foundry. The OSATs should not make the TSVs. I still say a dummy piece of silicon like an interposer, where the line widths are 3 microns and above, the OSATs can do that. Last year, Amkor said that they are not going to invest a penny to make TSVs. That’s the right direction.

SMD: Why is Wide I/O memory generating so much interest?
Lau: Memory bandwidth. Bandwidth is defined as the amount of data transferred per second. Typical dynamic random access memory has 4-, 8-, 16-, or 32-bit data width to communicate with CPU/logic/SoC and/or the outside world. These are called ×4-, ×8-, ×16-, or ×32-bit I/O. Wide I/O is defined as ×512-bit I/O or 512-bit data width or greater.

SMD: So memory bandwidth is the name of the game?
Lau: The memory bandwidth is proportional to memory I/O data width. For instance, the DDR3–1600 chip has a speed rating of 1600 Mb/s per I/O. If this DDR3-1600 chip has ×32-bit I/O data width, the chip would have a total memory bandwidth of 32 × 1600 = 51,200 Mb/s or 51.2-Gb/s. The larger the data width, the larger the memory bandwidth.

SMD: So where’s the bottleneck?
Lau: The data width is limited by IC packaging technology. With TSV technology, which provides very small via size (5- to 10-μm sizes are common) and pitch (20- to 40-μm pitches are common), a much wider I/O data path, such as 512-bit data width, is more than possible. On the other hand, wire-bonding technology has pad sizes and pitches that are many times larger than those of TSV. In order to achieve a 512-bit data width, the chip size, and thus the cost, has to be increased substantially. This is why TSV is so attractive for memory bandwidth. Let’s say that if we have TSVs run through a 4-DRAM stack with a ×512-bit data path, we could have the same DDR3-1600 chip with a total memory bandwidth of 102.4-GB/s. Of course, this DRAM stack has to interconnect to the logic/SoC in order to get this bandwidth.

By Mark LaPedus
Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing.

One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, Texas.

In addition, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is tweaking its 2.5D/3D foundry strategy. Last year, TSMC announced a controversial turnkey solution. The company not only provides the front-end steps, but also the back-end work traditionally handled by the IC packaging houses. Now, instead of locking in customers with its front-to-back solution, TSMC is rethinking its position.

“We prefer to do it ourselves,” said Morris Chang, chairman and chief executive of TSMC, in a recent conference call. “We have become more flexible to partner with the OSATs.”

Two other vendors, GlobalFoundries and UMC, are sticking with their collaborative approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Another foundry, IBM, has a slightly different strategy. Still to be seen, however, is what Intel and Samsung will do in the arena. And some of the IC packaging houses have given up the notion of doing fine-pitch interposers and through-silicon vias (TSVs). Instead, the OSATs are looking at doing course-pitch TSVs and interposers.

So, in general, there are two prevailing, leading-edge 2.5D/3D foundry models: TSMC’s turnkey solution and the rival collaborative approach. “I think both models will co-exist,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

Foundries go 3D
The memory bandwidth gap and resistivity problems in planar devices have fueled the development of 2.5D/3D chips. But advanced chip stacking has several challenges and is still a few years away from mass production. For example, TSMC will not see “significant revenue” in 2.5D/3D until 2015 or 2016, Chang said.

2.5D/3D technology and the associated supply chain are immature. Manufacturing costs are falling, but there is still a perception that the 3D devices will be prohibitively expensive, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials.

So far, only a few chipmakers have announced 3D chips. In 2010, Samsung rolled out one of the first 3D DRAMs using a 40nm process and TSVs. Then, last year, Samsung and Micron formed a consortium to develop a serial specification for a 3D DRAM technology called the Hybrid Memory Cube (HMC). Micron will sample HMC devices in 2013. Aimed at high-end applications, HMC will stack DRAM arrays on a logic chip. IBM is making the logic chip based on an SOI substrate.

Another 3D DRAM vendor, Tezzaron, recently has begun shipping its initial parts. But other 3D DRAM schemes, such as Wide I/O, have been delayed due to an assortment of technical issues. Still, the industry is making more progress on the 2.5D front. “The 2.5D era has arrived,” said E. Jan Vardaman, president of TechSearch International, a research firm.

To date, Altera, Cisco, IBM, Huawei and Xilinx have talked about or shipped 2.5D devices using interposers. In fact, Xilinx has shipped the Virtex-7 2000T FPGA, a product based on a 28nm process and a 65nm silicon interposer.

The device itself is built and assembled by TSMC, which refers to its 2.5D/3D turnkey solution as “Chip on Wafer on Substrate” (CoWoS). Using CoWoS, TSMC is also building a rival 2.5D FPGA for Altera. In CoWoS, the chip is attached to the substrate to form the final component. TSMC provides front-end manufacturing, TSV formation, interposers, chip-on wafer bonding, backside thinning, dicing and final test.

CoWoS has been given a lukewarm reception by the IC packaging houses, many of which believe that TSMC is taking a chunk of the backend business away from the OSATs. “For some customers, (CoWoS) works well. It doesn’t work for all customers,” Vardaman said.

TSMC has defended CoWoS, saying that the in-house, turnkey solution enables the foundry to ensure the quality of the chips and the production process. TSMC also assumes responsibility for the supply chain. “Technically, it is progressing well,” TSMC’s Chang said. “We are trying to reduce the costs.”

Beyond 2.5D FPGAs, TSMC recently taped out a Wide I/O device. To enable Wide I/O, the company requires DRAM from a third party. Originally, it was working with Elpida, which is being acquired by Micron. Now, TSMC is working with Micron and SK Hynix.

TSMC’s model may fall flat when customers ask for DRAM from Samsung. TSMC and Samsung are foundry competitors. It’s unlikely that Samsung will hand over DRAM wafers, along with its proprietary IP and test data to TSMC.

In some cases, it makes more sense to follow the collaborative model, where there are fewer conflicts. A customer can use its own logic and/or memory or buy it from a third party. The foundries do the front-end processing, while the OSATs collect and assemble the pieces.

With that scenario in mind, TSMC is warming up to the idea of working with OSATs to give customers more flexibility. TSMC also may be fending off its rivals, which are offering a collaborative approach.

More models

Others are moving full speed ahead with their strategies. Earlier this year, GlobalFoundries installed the tools to create 3D TSV devices on its 20nm platform within its fab in New York. It will handle the “via creation” steps. Then, it will hand off the traditional backend steps, such as temporary bonding/debonding, grinding and test, to the OSATs.

The foundry vendor also devised a low-volume, 2.5D line using 65nm interposers within its fab in Singapore. GlobalFoundries’ challenge is to demonstrate a smooth flow and good product yields at a competitive cost. “It’s going well,” said GlobalFoundries’ McCann. “The question is, can we make this collaborative supply chain model a one-to-one solution? We have to prove this to our customers.”

Another vendor, IBM, has been working on 2.5D/3D for years, including a specialized interposer technology. “IBM is working with Sematech to connect analog converter functions in a logic device with an interleaver IC in IBM’s BiCMOS SiGe technology,” said TechSearch’s Vardeman. “Applications are fiber optic telecom, high-performance RF, test equipment and processing for radar systems.”

The new kid on the foundry block is Tezzaron. In October, the company acquired the former SVTC fab in Austin. R&D foundry SVTC, which recently went bankrupt, originally acquired the fab from Sematech. Now, the fab operates under the name of Novati Technologies. Tezzaron is the sole shareholder in Novati. “We are going to become a 3D foundry,” said Robert Patti, chief technology officer at Tezzaron. “What we are trying to do is provide an open platform for 2.5D and 3D integration.”

Asked if Novati will compete against TSMC and GlobalFoundries, Patti said Novati can work with other foundries and will not compete against them. Novati will continue to serve SVTC’s customers. The Austin fab is a 200mm CMOS line, with 200mm/300mm backend capabilities.

As part of the plan, Tezzaron will shut down its current fab in Singapore and transfer the tools to the Austin fab by early 2013. By Q3 of next year, the company hopes to provide 3,000 wafer starts a week in Austin.

In the 2.5D/3D foundry arena, Novati will offer advanced stacking capabilities, TSVs and interposers. It can provide Tezzaron’s 3D DRAMs or procure third-party logic and memory chips. And Novati will offer both a turnkey and collaborative model. “We are willing to do a full turnkey solution,” Patti said. “I am willing to take the pieces and assemble them.”

The company prefers customers to use its so-called FaStack technology, which makes use of a proprietary bonding and tungsten process. Its 2.5D/3D technology is based on a 40nm process. By late 2013, it will offer a 28nm platform.

While the foundry landscape continues to evolve, several IC packaging houses are rethinking their plans. Some time ago, Taiwan’s Advanced Semiconductor Engineering (ASE) was looking at fine-pitch interposers and TSVs in a “via-last” production flow. “We have an interposer technology that we’ve promoted,” said Rich Rice, senior vice president of sales for North America at ASE. “We are not sure about the market acceptance.”

As it turns out, ASE discovered that leading-edge TSV and interposer work belongs in the foundries and not at the OSATs. “I think poking holes in silicon is mostly a foundry business,” he said at a recent event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

On the other hand, ASE and STATS are looking at course-pitch interposers and TSVs for niche applications like MEMS and RF. The OSATs will also play a major role in fine-pitch 2.5D/3D by offering the critical backend work.

TSMC and its turnkey model will not take all of the backend business away from the OSATs. TSMC is still going up the learning curve in the backend and may find the work a headache in the long run. “This is something we do day in and day out,” Rice added.

By Mark LaPedus
For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence.

The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skipping” in the fabless-foundry world could reach new heights.

Two foundry vendors, GlobalFoundries and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), recently accelerated their respective 14nm-class finFET shipment schedules by a year or so. In effect, the companies have shrunk the process cadence between their planar 20nm and 3D-like finFET technologies to roughly a year.

Samsung is expected to follow a similar path. In many respects, the foundries appear to be luring customers into making the giant leap from 28nm (or above) processes to finFETs, thereby skipping 20nm. The reason is largely due to lackluster demand for 20nm planar, and they are aggressively marketing their finFET technologies right now.

Rival United Microelectronics Corp. (UMC) has a different strategy. UMC will move directly from 28nm planar to 14nm-class finFETs, bypassing the 20nm planar node. UMC recently licensed finFET technology from IBM, but it will stick with bulk CMOS. For its part, IBM will ramp up finFETs using silicon-on-insulator (SOI) technology.

The foundries are speeding up their finFET efforts for several reasons. First, there is a perception that the foundries are falling further behind Intel. The chip giant rolled out finFETs at 22nm and is offering the technology to select foundry customers. Intel plans to begin ramping up its 14nm finFET process by the fourth quarter of 2013.

Some chipmakers have been openly critical about the 20nm foundry planar process, saying the technology puts the industry behind the traditional performance curve. “I know some customers want more,” acknowledged Morris Chang, chairman and chief executive of TSMC, in a recent conference call.

So, at 20nm and beyond, chipmakers are weighing their options and exploring the trade-offs. “There will be customers that will skip 20nm to get to (finFETs),” Chang said. “I think there will be customers that will be light on one (process technology) and heavy on another.”

The benefits of finFETs are clear, but the industry is finally coming to grips with the challenges associated with the transistor technology. Cost, patterning and variation are just a few of the issues. The complexity will require more and deeper collaboration between foundries and their customers. “The challenge for us is to work across the ecosystem with our partners and have earlier tapeouts that are fully debugged and tested,” said Gregg Bartlett, senior vice president and chief technology officer at GlobalFoundries.

All told, the fabless-foundry model is still alive and well, but the business continues to change. Going forward, leading-edge foundries will offer fewer process derivatives. Customers will have fewer choices. And in the future, expect possibly one foundry to exit from the leading-edge process race, with more consolidation seen on the horizon.

Skipping around the IC world
At one time, most leading-edge chipmakers followed the natural progression of process technology nodes. The dynamics began to change starting around the 90nm node, when chipmakers migrated towards sub-wavelength lithography, low-k, design-for-manufacturing (DFM) and other technologies.

IC design and manufacturing costs began to soar. As the complexity and cost escalated at each process node, it was no longer a clear-cut decision to follow the natural cadence of process nodes. Chipmakers weighed the various technical and economic trade-offs.

Starting at 90nm, node skipping among chipmakers became the rule instead of the exception. For example, Netronome is currently shipping communications processors based on a 65nm process from TSMC. Instead of moving to 40nm or 28nm, Netronome recently decided to make a giant leap from 65nm to Intel’s 22nm finFET foundry technology. The decision, according to Netronome, was based on density, power consumption and cost.

Node skipping is expected to reach new heights at the 20nm planar process. The so-called “time-to-market” IC makers, such as AMD, Altera, Nvidia, Qualcomm, Samsung, and Xilinx, likely will make the traditional progression from 28nm to the 20nm planar node before moving to finFETs.

Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

With that in mind, there is a temptation to skip 20nm and migrate to finFETs. FinFETs take the traditional 2D planar design and turn the conductive channel on its side, resulting in a 3D “fin” structure surrounded by a gate that controls the flow of current.

Compared to 32nm planar, finFET transistors enable a 37% performance increase at low voltages and a power reduction of 50% or more, according to Intel. Intel’s own Tri-Gate transistor enables a steeper sub-threshold slope at around 80 mV/decade or below, compared to 100 mV/decade for leading-edge planar transistors, said Mark Bohr, senior fellow at Intel, at a recent event.

“Vdd scaling has slowed down. Leakage is an issue as geometries shrink,” said Srinivas Nori, director of SoC marketing at GlobalFoundries. “The value (that finFETs) bring is that it enables one to lower the Vdd. Leakage is better controlled. The variation of the Vt is also much better controlled.”

The benefits are easy to grasp, but the hard part is obvious. “If I was a designer, I would be worried,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is promoting SOI. “If you go back to the standard way of doing things in bulk, and you want a transistor with a different Vt and that drives a different current, you printed different line widths. You just made a fatter transistor. And you paid a little a bit of a penalty in the capacitance,” Mendez said. “How the heck can do you that in finFETs? It’s impossible. So, to make finFETs, you go in quantum steps. The way you actually do this is that you put down one fin, two fins or three fins on a structure.”

Besides the quantum issues, there are other problems. “The fin height is now a huge variable. In a junction-isolated fin, I don’t know how that is accurately controlled. So, from my perspective, this is a tricky thing for an SoC guy to get around. I would imagine you would need pretty stiff design rules to account for this,” he said.

Because of fin height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. The SOI proponents are pushing fully-depleted SOI (FD-SOI), claiming the technology can reduce the process steps and variability with little or no cost penalty.

New roadmaps
The foundries are still pushing bulk, but they have changed their roadmaps. In September, GlobalFoundries rolled out its finFET technology, dubbed 14nm-XM, based on a “modular fin” approach. GlobalFoundries opted to marry a 14nm front-end fin with a 20nm planar BEOL flow. In doing so, the company has accelerated its finFET process by a year. Product tape-outs are expected in 2013, with production slated for 2014.

“Today, customers, IP vendors and the whole ecosystem can actually start working on finFETs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “There are about 7,000 design rules that will carry over from 20nm planar to finFET. From a design point of view, the very early PDKs are almost the same as 20nm.”

Earlier this year, TSMC thought 20nm planar would become a popular node and announced a 20nm pilot line to prepare for the big ramp. But initial 20nm demand is lukewarm. TSMC claims to have 50 tape-outs for the technology, roughly one-fifth compared to that of 28nm.

TSMC’s 20nm pilot line is still on track for 2013. But last month TSMC accelerated its finFET risk production schedule from February 2014 to November 2013. Mass production is slated a year after its 20nm planar process. “This is a somewhat faster cadence than the previous generation,” TSMC’s Chang said.

Meanwhile, UMC said it has developed 20nm planar capability, but the company is not pursuing it as a mainstream process offering. Instead, it is more or less skipping 20nm and pursing finFETs. “After 28nm, finFET will be our focus,” said Shih-Wei Sun, chief executive of UMC, during a recent conference call.

By Mark LaPedus
Intel reported quarterly revenue of $13.5 billion and net income of $3.0 billion. http://finance.yahoo.com/news/intel-reports-third-quarter-revenue-200100019.html C.J. Muse, an analyst with Barclays Capital, said: “Intel lowered its capex guidance to $11.3 billion for 2012 vs. our estimate of $11.8 billion. While we believe Intel will remain vigilant in the ramp of 14nm, as Intel looks to aggressively redirect space and equipment to 14nm (80-90% of equipment bought at 22nm is reusable at 14nm node), we see capex of ~$9 billion +/- $1 billion in 2013.”

Is AMD on the ropes again? AMD will cut its workforce by approximately 15%. It also announced revenue for the third quarter of 2012 of $1.27 billion and a loss of $157 million. “Management’s ongoing mis-execution in our opinion seems to be contributing to building too much inventory, firing top operational managers, channel misalignment (and) withdrawing from broad swaths of the market,” said Craig Berger, an analyst with FBR. Meanwhile, analyst, Hans Mosesmann of Raymond James, said: “The worrisome but not too surprising commentary by AMD management was that the PC market will take several quarters to recover. AMD now considers 85% of its current business ‘legacy’ PC, with the planned restructuring focused on attacking various adjacent high-volume markets.”

Seeking to accelerate the development of EUV lithography, ASML has entered into a definitive agreement to acquire Cymer for $2.6 billion. “Cymer’s light source is critical to EUV success and given recent slippage of key metrics, we think it makes sense for the technology to move in-house at ASML,” Muse said.

In response to its foundry rivals, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has updated and accelerated its finFET roadmap.

GlobalFoundries could employ as many as 3,000 workers at its Malta plant, according to reports.

STMicroelectronics’ 28nm Fully Depleted Silicon-On-Insulator (FDSOI) process, which uses substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP.

Soitec announced total consolidated sales of 130.2 million euros for the first half, down by 19.9% on a yearly basis.

European government representatives, consortia and suppliers discussed 450mm fabs at Semicon Europa in Dresden.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.81 in September, compared to 0.84 in August, according to SEMI.

Mentor Graphics has rolled out a formal-based technology in the Questa Verification Platform.  In addition, Mentor announced new capabilities to complement TSMC’s 20nm manufacturing processes.  Meanwhile, SpringSoft and Mentor announced that the Laker-Calibre RealTime custom layout flow has been selected for the TSMC Custom Design Reference Flow. In a related announcement, TSMC has presented Mentor with two “Partner of the Year 2012” awards in various categories. And, Mentor announced the winners of its 24th annual PCB Technology Leadership Awards.

At the Storage Networking World (SNW) conference, there was no shortage of SSD presentations. But none of the keynoters who shared their data center experiences had deployed any SSDs in their systems. This seemed particularly odd to The SSD Guy.

Amazon is in talks to buy the mobile chip business of Texas Instruments. TI’s chips are used in Amazon’s Kindle Fire tablet.

FormFactor completed its acquisition of Astria Semiconductor Holdings and its subsidiary MicroProbe.

Lam Research achieved revenue of $906.9 million, up 22.3% from prior quarter, in first full quarter of consolidated results with Novellus.  “Based on continued push-outs of NAND spending, Lam guided to December quarter revenues of $820-880 million, well below consensus of $927 million,” said Barclay’s Muse. “While management had previously suggested that 2012 WFE was tracking to the low end of the $29-30 billion outlook, management took the opportunity to lower their 2012 WFE outlook to about $28-29 billion.”

Xilinx announced fiscal Q2 2013 sales of $543.9 million, down 7% sequentially and down 2% from the second quarter of the prior fiscal year.  Barclay’s Muse said: “Xilinx reported mixed September quarter results and then guided to worse December quarter, highlighting continued macro pressure for semis.”

Microchip Technology has lowered its forecast. “Our lower than anticipated net sales activity in the September quarter was driven primarily by macroeconomic and industry conditions,” said Steve Sanghi, Microchip’s president and CEO. “The overall global economic outlook continues to be poor and is adversely impacting our business as well as the rest of the semiconductor industry.”

Marvell expects net revenue for the third quarter of fiscal 2013 will be in the range of $765 million to $785 million, compared with prior outlook of between $800 million to $850 million. “The continued slowdown in the global economy during the third quarter is resulting in a weaker PC market than previously anticipated and thus lower demand from our storage HDD customers,” said Sehat Sutardja, Marvell’s chairman and CEO. FBR’s Berger said: “We think Marvell has a structural management problem that inhibits the firm from realizing real change, may discourage the development of formalized engineering processes, and keeps the firm on what seems to be a self-destructive path of no growth and limited traction in cellular. With the board unwilling to make real changes, business at Marvell could migrate from bad to worse over time.”

The NAND and NOR flash memory market landscape is shifting rapidly, with increasingly sophisticated mobile handsets playing a leading role in driving industry trends and determining which suppliers will be successful, according to IHS iSuppli.

By Mark LaPedus
As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model.

Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the foundries are not only manufacturing partners, but there is a deeper collaboration within a customer’s design team.

In fact, given the variability challenges with finFETs, there is a school of thought that chipmakers must reside at the same physical location as their foundry partners’ fabs to ensure that design and manufacturing are on the same page. Otherwise, according to some experts, the chances for first-silicon success are shaky.

For this reason and others, Taiwan Semiconductor Manufacturing Co. (TSMC) may take the “virtual IDM” model a step further. TSMC is considering a plan to build separate fabs for individual companies. And as part of its strategy, TSMC has accelerated its finFET roadmap.

Rival GlobalFoundries is considering a plan to offer dedicated modules within a fab for customers. And taking another approach, United Microelectronics Corp. has floated an equity placement under which companies can buy a 10% stake in UMC. UMC also has licensed IBM’s 20nm and finFET technologies.

Another foundry vendor, Samsung Electronics Co, has perhaps set the tone for the industry: It has already built a dedicated fab for Apple. And separately, in a surprise move, fabless chipmaker Qualcomm is considering the idea of building its own fab to gain better control of the manufacturing process.

Qualcomm CEO “Paul Jacobs has discussed it openly of late,” said G. Dan Hutcheson, president of VLSI Research. “Qualcomm certainly has the revenues to build its own fab and start making its own wafers. The chance of success is still low. It would cost at least three times, and possibly as much as five times, to successfully get your first fab to viable production, or approximately $15 billion to $25 billion. In other words, it would be an out-of-body experience for the management team that tries it.”

Sea of change
In any case, there could be a sea of change taking place in the traditional fabless-foundry model. “The traditional foundry model, where you throw a GDS2 file over the wall, no longer works,” said Mojy Chian, senior vice president of design enablement at GlobalFoundries. “We have to work closer with the fabless guys. New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market. In fact, the collaboration should start two to two-and-a-half years ahead of tape out.”

In the late 1980s, the pure-play foundries emerged, which spawned a plethora of fabless companies. One of the drawbacks with the fabless-foundry model is that the design houses and foundries sometimes work in silos and do not cooperate. In some cases, fabless vendors will throw a clunky design “over the wall” to the foundries, which are still expected to make the chip on time. This brute-force methodology has experienced mixed success.

The fabless and foundry firms began to change their ways at the 130nm node amid soaring IC design and manufacturing costs. “130nm is when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then,” said VLSI’s Hutcheson.

Then, starting in the early part of this decade, several foundries billed themselves as “virtual IDMs,” claiming they would work more closely with customers. But some of those efforts have fallen short of expectations. “The leading fabless suppliers got hurt badly when the leading foundries hadn’t dealt well with variability at 40nm, and more recently, with design-manufacturing interactive yield losses at 28nm,” Hutcheson said.

Now, as the IC industry moves toward the 20nm node and beyond, the foundries have become more serious about embracing the “virtual IDM” model and for good reason: The stakes are higher. At 130nm, a fab was $1.45 billion, process R&D costs were $250 million, and design costs were $15 million. But at 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million.

Simply put, the traditional foundry model must evolve. “You can’t do it in silos,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “The key is to have a tighter integration between product design and manufacturing.”

This is especially true in the finFET era. Intel has moved finFETs into production at 22nm. Given the variability issues, the foundries face challenges to put finFETs into production at 14nm.

Intel and the foundries are in the bulk finFET camp. But to make the finFET transition easier, the foundries should look at silicon-on-insulator (SOI) technology, said Chenming Calvin Hu, professor of electrical engineering at the University of California at Berkeley. “We are going to see (both bulk and SOI finFETs) in volume manufacturing,” Hu said. “[SOI] is easier. The supply chain is the one thing that manufacturers need to be assured of.”

New business models
On the business side, the industry could take one of two routes: Maintain the fabless-foundry status quo or move toward a “virtual IDM” model. Morris Chang, chairman and chief executive of TSMC, sees yet another model: Build dedicated fabs or joint-venture fabs for larger customers.

“We made our mark serving many customers (in multiple fabs). We will retain that capability,” Chang said during a recent conference call. “There are going to be larger customers. So it makes complete sense to have one dedicated fab, or more than one fab, for one customer.”

GlobalFoundries, meanwhile, is considering a slightly different model. “This is hypothetical,” said GlobalFoundries’ Kengeri. “Within a fab, we have modules. If one of our customers wants a dedicated module, it’s open for discussion.”

In that arrangement, a chipmaker may have to share the risk and cost. And it must make economic sense. Clearly, though, Apple is one candidate for a dedicated fab. In fact, Samsung already has built a dedicated fab for Apple in Austin, Texas.

Altera, Broadcom, Nvidia, Qualcomm and Xilinx are also possible candidates to occupy part or all of a fab. Qualcomm, for one, has the volumes and already is sourcing parts from all of the leading-edge foundries to keep up with 28nm demand.

Qualcomm’s multi-foundry sourcing strategy “is a very expensive approach today, as designs don’t port to multiple foundries like they used to,” said VLSI’s Hutcheson. “Yields are far more difficult to obtain at these advanced nodes, and splitting production across multiple fabs means either less relevant data per learning cycle or longer learning cycle times. That results in longer time-to-money and higher costs, making going the IDM route seem more attractive.”

It’s unlikely that Qualcomm will build its own fab, but it is possible it will end up with a joint venture fab with a foundry. In addition, Qualcomm and others would like the foundries to speed up their process roadmaps. The foundries are falling behind Intel, which also offers foundry services on a limited basis.

TSMC, for one, plans to accelerate its finFET efforts. Originally, TSMC planned to introduce finFETs at 14nm by late 2014. Now, the company has no plans to brand its finFETs at 14nm, but rather it will introduce the technology at 16nm. TSMC’s finFET “risk production” is slated for the end of 2013 or early 2014, with production scheduled for the second half of 2015, Chang said.

TSMC is not banking on extreme ultraviolet (EUV) lithography for 16nm. “We are very confident we can make 16nm finFETs without EUV,” he said. “I think EUV will come in at 10nm.”

To accelerate 450mm fabs and EUV in the market, Intel recently inked a deal with ASML. ASML has also enabled customers to take a 25% stake in the company. Intel plans to acquire up to a 15% stake in ASML.

TSMC and Samsung are also negotiating with ASML to take separate stakes in ASML. Taking a page from the ASML-Intel deal, UMC separately floated private equity shares under which strategic partners can take up to a 10% stake in UMC.

This represents a change for UMC. The company has developed its own processes and has shied away from forming strategic alliances. UMC has controlled its own destiny, but it also has fallen behind its rivals.

To jumpstart its process roadmap, UMC recently licensed 20nm and finFET technology from IBM. UMC’s finFET technology is reportedly a 14nm or 16nm front-end, with 20nm backend. “For UMC to do a finFET from scratch is very challenging,” said Shih-Wei Sun, chief executive of UMC, in a recent conference call. “This will kick start our finFET efforts.”

GlobalFoundries and Samsung have yet to change their finFET strategies. GlobalFoundries still plans to roll out a finFET at the 14nm node in the fourth quarter of 2014 or first quarter of 2015, according to Kengeri.

By Mark LaPedus
The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market.

There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs.

The enormous risk to bring these chips to market means that vendors must develop a sound and cost-effective strategy on all fronts. In one part of the wafer-level packaging flow, for example, chipmakers must choose between one of the three main vertical stacking techniques: die-to-die, die-to-wafer and wafer-to-wafer.

Each stacking technique has its advantages and disadvantages. The decision to go with one technique or another depends on the product type, process flow, and, of course, cost. And it also involves some changes in the interconnect material and wafer bonding methodology.

The early stacking trends are becoming apparent: The 2.5D/3D chip market is currently embracing die-to-die (sometimes called chip-to-chip), with die-to-wafer in the works. Wafer-to-wafer has moved into applications such as image sensors, but the technology is still in the distant future for chip production.

“I think the biggest challenge for the whole process is yields,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

“Die-to-die is the first implementation. In die-to-die, you can manage the warpage and isolate the yield,” McCann said. “Wafer-to-wafer will take place in the future, but you bring yield issues into your business model.”

Another foundry, Taiwan Semiconductor Manufacturing Co. (TSMC), recently rolled out its Chip-on-Wafer-on-Substrate (CoWoS) offering. This is a turnkey line that includes both the front- and back-end steps for 2.5D/3D production. Technically, CoWoS is a die-to-die scheme, but it could also be classified as die-to-interposer.

Bottleneck in 3D flow
In the overall 2.5D/3D manufacturing flow, there are a number of process steps. There are five main front-end TSV or via creation process steps: etch, chemical-vapor deposition, physical-vapor deposition, electroplating, and chemical mechanical polishing.

The bigger manufacturing bottlenecks reside at the back-end. In this flow, a processed wafer with TSVs goes through the following steps: wafer bumping, thinning, stacking and bonding. Test is conducted at the wafer level and during various points in the flow.

Test and the temporary bonding/debonding steps are still the big challenges. Though not as daunting, there are some challenges in the various stacking techniques, including die-to-die.

One of the first 2.5D chips in the market is Xilinx’s Virtex-7 2000T FPGA. The recently announced 2000T is a 28nm part, in which four FPGA slices are stacked on a 65nm interposer. Technically, Xilinx’ FPGA utilizes chip-to-chip and die-to-interposer stacking.

Emerging 3D memory devices utilizing Wide I/O also will implement die-to-die. Related to stacking, the industry is also moving to an emerging interconnect scheme called fine-pitch copper pillar bumps for 2.5D/3D designs.

For years, many 2D designs have used conventional flip-chip solder bumps. More recently, copper pillar bumps have been implemented in various 2D designs, when there is a need for low-profile and high-connectivity applications.

“Copper pillar gives you a tighter pitch,” said Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials. Flip-chip solder bumps enable 40-u pitches, compared to 20-u for copper pillar, Ramaswami said.

The transition to copper pillar bumping appears to be rather painless, but there are some issues in the vertical stacking flow. Compared to the other stacking techniques, die-to-die is well understood, and the supply chain is relatively straightforward.

The die-to-die equation becomes more difficult in heterogeneous designs, where the individual parts may come from two or more vendors. This complicates the stacking flow and brings yield into the equation. “That’s where the (importance of a good) supply chain comes in,” Ramaswami said.

The other problem with die-to-die is throughput and cost. In die-to-die, the components are assembled and aligned with traditional pick-and-place tools. The throughputs are slow, sometimes averaging 360 dies an hour. “The problem is more pronounced if the dies are small,” said Thorsten Matthias, head of business development at EV Group, a supplier of semiconductor equipment.

Regarding the assembly flow, Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE), added: “It’s really a challenge to handle these thin wafers. Warpage is a big challenge.”

3D devices will require ultra-thin wafers of 100 µm and below, but these substrates are less stable and prone to stress in the flow. This will require a manufacturing step called temporary bonding and debonding, which is still a relatively slow and expensive process.

For this and other reasons, the 2.5D/3D devices themselves are expected to remain expensive. “But for very large die, you can still achieve a cost reduction,” Rice said.

Other stacking options
There are even more challenges in die-to-wafer, which appears to be in R&D or the pilot line stage. Die-to-wafer also has many of the same inherit problems as die-to-die. There are supply chain issues. Both flows will implement expensive temporary bonding/debonding steps.

“The question is how you are going to test it? You really need known-good die (KGD) to put these things together. You also need to make sure your interposer is good,” Rice said.

Still, many chip makers have put die-to-wafer on their roadmaps to lower their costs and boost their throughputs, EV Group’s Matthias said. The other advantage is that “you can control or eliminate warpage,” he said.

Meanwhile, for decades, the industry has been talking about wafer-to-wafer stacking. Wafer-to-wafer enables the highest throughput, but it requires that the dies have the exact same size when bonding. But if a defective die is bonded to a good die, it destroys the whole stack. “Wafer-to-wafer is a long ways off,” said E. Jan Vardaman, president of TechSearch International Inc., a research firm.

To accelerate wafer-to-wafer, the industry is exploring new bonding technologies. Today’s 2.5D/3D devices, based on TSVs and copper pillars, are implementing metal-to-metal thermocompression bonding. This methodology has the advantage of forming the mechanical and electrical bonds in one step.

The industry is also looking at copper-to-copper thermocompression bonding. “Copper-to-copper is a must if you are targeting the highest possible electrical performance at less than 10-u,” EV Group’s Matthias said. But this technology is a slower process and not expected to move into volume production for another two to three years.

Another technology, fusion wafer bonding, could one day enable wafer-to-wafer for 3D chip integration. Fusion bonding is a two-step process consisting of a room temperature bonding step and an annealing step at elevated temperature. EV Group and others sell fusion bonders.

Using one form of fusion bonding technology, dubbed direct oxide bonding, Ziptronix Inc. has demonstrated the ability to reduce distortion in backside illuminated (BSI) image sensors. Ziptronix’ ZiBond process can be performed as wafer-to-wafer or die-to-wafer. The process initiates at room temperature without external force required.

The rival bonding solutions “are limited in terms of stress, cost and scalability,” said Paul Enquist, CTO and vice president of R&D at Ziptronix.

Ziptronix’ technology is in production for BSI image sensors. It’s unclear when chipmakers will adopt fusion bonding for wafer-to-wafer 3D integration. The adoption of new technology takes time. “Our technology has been ready for awhile,” he said. “Finally, the market is ready for the technology.”

The Hybrid Memory Cube Consortium (HMCC) — the 3D DRAM effort led by Micron Technology Inc. and Samsung Electronics Co. Ltd. — said that software giant Microsoft Corp. has joined the group.

Last October, memory rivals Samsung and Micron announced the creation of a consortium to develop an open interface specification for a 3D memory technology called the Hybrid Memory Cube (HMC). The HMCC is developing 3D DRAM devices based on through-silicon-via (TSV) technology.

Members of the consortium include Micron, Samsung, Altera, Open-Silicon, Xilinx, IBM and now Microsoft. The technology will enable 3D memory solutions for applications ranging from industrial products to high-performance computing and large-scale networking.

“HMC technology represents a major step forward in the direction of increasing memory bandwidth and performance, while decreasing the energy and latency needed for moving data between the memory arrays and the processor cores,” said K.D. Hallman, general manager of Microsoft’s Strategic Software/Silicon Architectures group.

Last year, Micron disclosed the manufacturing flow for the HMC. Under the plan, IBM will manufacture the controller logic portions of the HMC within its own fab. Micron will make the memory portions – and will assemble and test – the HMC devices within its own operations. Micron has recently set up a 3D DRAM pilot and production line within its 300mm R&D fab in Boise, Ida.

Sandia National Laboratories is developing a supercomputer as part of a DARPA program. In the short term, the lab has found a memory solution for the system: Micron’s HMC.