Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.
Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.
Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high. What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.
He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.
After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth? What types of designs will be staffed and funded? Is it IoT? Wearables? Automotive? Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.
Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.
These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.
A few of the highlights:
- Oracle’s use of advanced fill techniques for improving manufacturing yield
- How Xilinx built a custom ESD verification methodology on the Calibre platform
- Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
- Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
- Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
- Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
- A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
- How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
- Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements
Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.
The day winds up with a closing session and networking reception from 5:00-6:00pm.
Registration is from 8:00-9:00am in the morning.