By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan.

SMD: What is ITRI doing in 3D TSVs?
Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was completed two years ago. We developed the process from the very beginning to the end. We don’t have products. We are demonstrating the feasibility for 3D TSVs.

SMD: What else is ITRI doing in the arena?
Lau: We also have a consortium call Ad-STAC (Advanced Stacked-System and Application Consortium). We have more than 22 members. We just develop the necessary technologies for 3D integration. The members are UMC, SPIL, Applied Materials, Brewer, Rambus, Cisco and others. In addition to that, we have some 80 people working on EDA. For 3D, EDA is very critical.

SMD: Where is the industry at with 3D TSVs?
Lau: For me, it’s still very early. You still have to bring the OEMs into the mix. The OEMs may say: ‘Oh, I’m interested.’ Then, you still have to wait three to five years. There are two different kinds of OEMs. One is consumer. 3D TSVs are still too expensive for them. However, it could be a different story for high-end, next-generation servers, networking and test and measurement gear.

SMD: Where is a good starting place for 3D?
Lau: Take the Hybrid Memory Cube Consortium. Several months ago, the group announced they would open up the spec by the end of this year. But that’s only for high-end servers, test and measurement, and networking. It’s for very high performance and not for the consumer. They may adopt 3D. But the Hybrid Memory Cube for mobile products? Come on. Of course, we hope 3D can be for the consumer market. In consumer, there are larger volumes.

SMD: What is the biggest challenge for 3D?
Lau: Cost. The consumer market is cost-driven. For the iPhone 5, the semiconductor bill of materials is less than $30. The ASICs and memory are less than $30. Now take Xilinx’s 2.5D FPGA. The CTO from Xilinx recently gave a keynote at Semicon West. His conclusion was that they need to reduce the cost. A 2.5D FPGA is still costly.

SMD: What are the manufacturing challenges?
Lau: Just to make the TSV is no more than 5% of the cost. But if you look at the other steps, you have temporary bonding, back grinding, and others. The biggest issue is thin wafer handling and temporary bonding/debonding. And then you need to debug it.

SMD: Who should make the TSVs? The OSATs or the foundries?
Lau: Xilinx is using 65nm technology for their 2.5D FPGAs. OSATs like ASE don’t have 65nm technology. If they did, they would become another foundry. The OSATs should not make the TSVs. I still say a dummy piece of silicon like an interposer, where the line widths are 3 microns and above, the OSATs can do that. Last year, Amkor said that they are not going to invest a penny to make TSVs. That’s the right direction.

SMD: Why is Wide I/O memory generating so much interest?
Lau: Memory bandwidth. Bandwidth is defined as the amount of data transferred per second. Typical dynamic random access memory has 4-, 8-, 16-, or 32-bit data width to communicate with CPU/logic/SoC and/or the outside world. These are called ×4-, ×8-, ×16-, or ×32-bit I/O. Wide I/O is defined as ×512-bit I/O or 512-bit data width or greater.

SMD: So memory bandwidth is the name of the game?
Lau: The memory bandwidth is proportional to memory I/O data width. For instance, the DDR3–1600 chip has a speed rating of 1600 Mb/s per I/O. If this DDR3-1600 chip has ×32-bit I/O data width, the chip would have a total memory bandwidth of 32 × 1600 = 51,200 Mb/s or 51.2-Gb/s. The larger the data width, the larger the memory bandwidth.

SMD: So where’s the bottleneck?
Lau: The data width is limited by IC packaging technology. With TSV technology, which provides very small via size (5- to 10-μm sizes are common) and pitch (20- to 40-μm pitches are common), a much wider I/O data path, such as 512-bit data width, is more than possible. On the other hand, wire-bonding technology has pad sizes and pitches that are many times larger than those of TSV. In order to achieve a 512-bit data width, the chip size, and thus the cost, has to be increased substantially. This is why TSV is so attractive for memory bandwidth. Let’s say that if we have TSVs run through a 4-DRAM stack with a ×512-bit data path, we could have the same DDR3-1600 chip with a total memory bandwidth of 102.4-GB/s. Of course, this DRAM stack has to interconnect to the logic/SoC in order to get this bandwidth.

By Mark LaPedus
In today’s systems, consumers want more performance and bandwidth with a longer battery life.

Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the past few years,” said Abe Yee, senior director of advanced technology and package development at Nvidia. “Memory bandwidth has not kept up.”

In fact, there is a growing gap between memory bandwidth and overall system requirements, creating an unwanted I/O bottleneck, Yee said. The memory bandwidth gap, resistance-capacitance (RC) delays and other factors are fueling the development of new 3D DRAM schemes like Wide I/O. “We need Wide I/O memory,” he said. “We also need a known good die stack.”

But advanced chip stacking has a multitude of challenges and is still a few years away from mass production. One of the bigger, and sometimes forgotten, challenges is the ability to obtain and test known good die (KGD). A KGD is an unpackaged part or a bare die that meets a given specification.

As chip complexity increases, the industry may need to lower its targets and not expect a perfect KGD. In other words, the idea of having a KGD may not be attainable. “Ensuring KGD is (expected to be) more difficult in the ‘more than Moore Era,’ “ said Bill Bottoms, chairman and chief executive of ATE vendor Third Millennium Test Solutions (3MTS), in a recent presentation. “The era of known good die is drawing to an end. The concept of known good die will be displaced by ‘probably good die’ for very complex systems.”

Not all is lost, however. To address the KGD problem, the industry is developing a new class of probe cards. Chipmakers also are counting on a range of design-for-test (DFT) technologies, such as boundary scan, built-in-self-test (BIST), redundancy and repair, to enable the “probably good die” era.

Live and let die
KGD became a major issue in the 1980s, when the industry began to push multi-chip modules (MCMs) in systems. In MCMs, several unpackaged dies are stacked or assembled side-by-side within a module as a means to create smaller and faster systems.

MCMs met with limited success and a plethora of startups that were pushing the technology folded in the 1980s and 1990s. “The problem (with MCMs) was the dielectrics,” recalled Richard Otte, president and chief executive of Promex Industries, an IC packaging house. “The dielectrics were crummy.”

The other problem with MCMs was (and still is) the ability to obtain KGD. For years, the industry has procured KGD or bare die for use in MCMs, RF modules and system-in-packages (SIPs). Generally, a bare die takes up less space in a system compared with a traditional packaged part. For this reason, a large percentage of RF chips are sold as bare die and then assembled in RF modules. Analog chips, discretes, memories, MCUs and passives also can be sold as bare die.

Still, IC makers prefer to sell packaged parts, which can be tested in conventional ATE to ensure their quality. Bare die are sometimes viewed as a nuisance because they require specialized testing and handling. As a result, they are sold at a premium.

Selling KGD or bare die “is something chipmakers would prefer not to do,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC. “It’s hard to guarantee the quality of KGD. It is sometimes not possible to access all of the test vectors at the die level.”

The challenges escalate for 2.5D/3D designs. In chip stacking, the probability of obtaining KGD decreases. For example, the average yield for a memory wafer is around 50% today, said Robert Patti, chief technology officer for Tezzaron Semiconductor, a 3D DRAM supplier. For a four-layer stacked memory device, the average yield could go as low as 6%, he said, which he described as “not economically viable.”

The inadvertent use of a defective die is catastrophic in 2.5D/3D designs. It will result in yield loss. And in many cases, the entire part must be discarded.

There are other challenges, especially as chipmakers move towards heterogeneous 2.5D/3D designs. In one scenario, an IC maker may use an internal part. Then, the company obtains and integrates a separate bare die from another vendor. But if the device fails in the field, it’s unclear who will take responsibility for the faulty part.

Settling for imperfection
To attack the KGD problem, chipmakers will require breakthroughs on two basic fronts: probe cards and DFT. It also requires a different test flow. The flow for conventional packaged chips includes IC manufacturing, wafer sort, packaging and final test. Wafer sort is considered an initial screening process for packaged ICs.

In contrast, a bare die is not tested at final test using conventional ATE. Instead, a die is tested at wafer sort using a wafer prober. In this flow, chipmakers claim they can achieve a reliable KGD, but overall test costs are sometimes higher. Die failure rates are reduced, but they are never totally eliminated in wafer-level testing.

For 2.5D/3D testing, the industry is working on new probe card technology. A wafer prober is incorporated with a custom probe card, which itself has thousands of probing needles that hit the bond pads on a die. In effect, the prober detects defective die, which are eliminated.

In complex designs, the needles may miss some of the tiny bond pads on the die. The contact force of the needles also could damage the die. Concerning KGD in 2.5D/3D designs, the industry requires “improvements in fine-pitch probe technology,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). Specifically, the big challenge for the industry is to develop probe cards that can handle greater than 1,000 contacts and pitches below 50um, Rice said.

In probe cards, there are two basic camps. FormFactor and others are working on fine-pitch probe cards using MEMS-based technology. In another camp, IMEC and Cascade Microtech have been working on a “rocking beam interposer” (RBI) probe card technology. RBI is based on Cascade’s membrane technology. “The metal energy doesn’t bend. It rocks,” said Ken Smith, vice president of technology development at Cascade, a supplier of wafer probers and probe cards.

In RBI, the probe tips are 6um square and 15um tall. With tip forces below 1 gram-force, RBI has demonstrated 40um and below pitches with a pad damage less than 100nm deep. “This technology is still in the early stages of the development cycle,” Smith said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

Even with breakthroughs in probe cards, 3D test still remains a challenge. In the flow, 3D devices will require at least four more test steps: a pre-bond test before stacking; a mid-bond test in the partial stacking phase; a post-bond test after final stacking; and a final test. The interposer and TSVs may also require separate testing.

Conventional ATE cannot be used in many, or possibly any, of these steps. So test must start in the design phase with various DFT techniques. In one scenario envisioned by Mentor Graphics, boundary scan can be used to test the bottom die in a 2.5D/3D design. Embedded core test can be used to test the middle or other dies, according to Mentor.

“The bigger challenge is with stacked logic die,” said Steve Pateras, product marketing director at Mentor. “There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question.”

For years, memory makers have made use of BIST, repair and redundancy in their 2D designs, which may translate in the 2.5D/3D world. “With memory it’s easier, because there’s a robust testing methodology for bare memory die. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BIST,” Pateras said.

Using such techniques, 3D DRAM maker Tezzaron claims to have obtained better yields in 3D over 2D. “You have to change the way you think about design,” said Tezzaron’s Patti. “The secret to KGD is design-for-repair.”

Tezzaron refers to its design-for-repair and BIST solution as “BiSTAR.” Designed to repair bad memory cells and ensure a known good memory stack, BiSTAR includes 256 BIST sequencers, which run independently in parallel.

Besides repair and BIST, Patti said the industry must rethink its definition of KGD and may need to settle for something less. “Will we ever have 100% perfect KGD? It’s probably not practical,” he said. “A ‘kind of a good die’ may be acceptable. We may also have to accept the idea of having ‘not bad die.’”

By Mark LaPedus
The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap.

As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architecture until 2015.

In the previous roadmap, mobile DRAMs were supposed to follow a simple progression from the conventional LPDDR2 to the LPDDR3 interface standards. Then, in 2013, the mobile industry was originally supposed to make a giant leap to Wide I/O, a 3D technology using through-silicon vias (TSVs).

Now, in JEDEC’s new roadmap, the industry will extend LPDDR3 with a new DRAM interface standard called LPDDR3E. After LPDDR3E, the industry will follow two simultaneous paths with a pair of new standards: LPDDR4 and Wide I/O-2. Devices built around 2D-based LPDDR4 and 3D-enabled Wide I/O-2 are due out in 2015. The first Wide I/O standard is still on JEDEC’s roadmap, but the devices are expected to be limited and mere point products.

The changes in the roadmap reflect the need to address the current and future bandwidth bottleneck issues in mobile devices. It also confirms the industry is still struggling to develop stacked 3D chips due to cost and technical issues. “It will take more time to sort out (3D issues like Wide I/O) than what people originally thought,” said Pat Moran, memory program manager at Qualcomm, at a recent JEDEC event.

The resistivity problems in planar devices have fueled the development of stacked 3D chips, whether those TSVs run through a die or a separate interposer die in so-called 2.5D chips. In either case, stacking is a viable way to circumvent the resistance-capacitance (RC) problems. But advanced chip stacking has a multitude of challenges and is still a few years away from mass production.

The industry is making progress in terms of reducing the manufacturing costs, and the technical hurdles, for 3D chips, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials. But when the 3D chips actually hit the market, there is still a perception that the cost of devices will be prohibitively expensive, Kumar said.

A brief history of Wide I/O
Not long ago, the big memory houses mainly focused on selling commodity DRAMs for PCs and servers. But for some time, DRAM makers have been engulfed in a prolonged downturn amid a slump for PCs. And the rapid rise of smartphones and tablets has prompted memory makers to put more emphasis on mobile DRAMs, which are specialty DRAMs with low power features.

In a sign of the growing importance of these parts, mobile DRAM represented 26% of all DRAM sales in the second quarter of 2012, compared to 19% in the like period a year ago, and 11% two years ago, according to IHS iSuppli. Average DRAM content in smartphones will expand to 666 megabytes (MB) this year, up from 453MB in 2011 and 202MB in 2010, according to the firm.

“As smartphones become more sophisticated, memory usage in the devices continues to rise, not only to satisfy user wants and needs, but also to accommodate demands made by ever-more powerful processors and increasingly refined LCD screens,” said Clifford Leimbach, an analyst at IHS iSuppli.

To keep up with the bandwidth requirements in portable systems, OEMs have migrated from mobile DRAMs based on the LPDDR1 interface standard to LPDDR2 technology. LPDDR1 has a data rate of 1.6-GB/s, while LPDDR2 runs at 4.3-GB/s.

In 2008, there were fears that LPDDR2 would run out of steam. So, at the time, the industry pushed a 3D architecture called Wide I/O. Wide I/O was a 4-channel scheme with a data rate of 17.2 GB/s. In the original roadmap, the goal was to stack the devices using TSVs.

Then, in 2010, the mobile market turned upside down, when a new class of smartphones and tablets emerged. Suddenly, Wide I/O, which was originally targeted for high-end smartphones, could only address limited mobile applications. “Wide I/O wasn’t going to cover the entire mobile space,” Moran said.

What’s next?
As a result, the industry saw an urgent need to fill a gap between LPDDR2 and Wide I/O. Starting in 2010, JEDEC and its members began to work on 2D-based LPDDR3, an extension of LPDDR2 that operates at speeds up to 12.8-GB/s in a dual channel mode.

Today, Hynix, Micron and Samsung are sampling their respective LPDDR3 mobile DRAMs. Instead of LPDDR3, some OEMs are opting for a low-power version of a desktop DRAM, dubbed DDR3L. OEMs are expected to migrate towards both technologies in 2013.

Needless to say, the industry must go beyond LPDDR3. The explosion of video, games and other technology in the mobile environment is driving the need for 4G LTE networks. “The bandwidth requirements are steep,” said Jung-Yong Choi, senior product planning manager at Samsung. “We need to react quickly.”

In response, JEDEC has unveiled a new, three-step plan. In the first step, the industry has devised LPDDR3E, an extension to LPDDR3 that has a data rate of 17-GB/s in a dual-channel mode at 1.2 volts.

Following LPDDR3E, the industry will follow two simultaneous avenues. It will take another evolutionary and safe path with 2D-based LPDDR4. It also will pursue the more revolutionary path with 3D-based Wide I/O-2. “Both candidates will have their own positions in the mobile industry,” Choi said.

LPDDR4-based mobile DRAMs, which require more space, are aimed at tablets. LPDDR4 will have 25.6-GB/s data rates and operate at 1.1 Volts. LPDDR4 will have 2-channels per die and 8-banks per channel. The LPDDR4 specification is due out by December of 2013. LPDDR4-based mobile DRAMs are expected in the first half of 2015.

Wide I/O-2 has the same specification and product roll out target dates as LPDDR4. Aimed for smartphones, Wide I/O-2 will launch in two phases. The first devices will have a 25.6-GB/s data rate, followed by parts at 51.2-GB/s.

Wide I/O-2 resembles the same architecture as the original Wide I/O scheme. It will stack memory on a logic controller and will connect them using TSVs. Wide I/O-2 will consist of four channels per die, x64 I/Os per channel (25.6-GB/s) and x128 I/Os per channel (51.2-GB/s). However, the industry is still debating the other specifications, such as the number of banks, page sizes, AC/DC parameters, pad order, pin description, addressing and command protocols.

In theory, LPDDR4 will have a power efficiency of 1 Watt at 25.6-GB/s. In terms of power, Wide I/O-2 is expected to be 50% to 60% lower than LPDDR4, Choi said. “Efficiency of CPU frequency could be improved largely by active heat dissipation,” he said.

One question still lingers, though: What ever happened to the original Wide I/O technology? Surprisingly, memory vendors insist the original Wide I/O devices will soon hit the market. If or when Wide I/O appears, the niche-oriented parts will likely be single-die solutions using micro-bumps, and not TSVs.

In fact, when the industry originally pushed for Wide I/O in 2008, it underestimated the challenges in developing 3D technology. The industry still faces many of the same problems today. TSV technology remains immature. It’s unclear how to deal with the thermal issues, and 3D test and the overall supply chain are not yet ready for prime time.

Cost is still a problem, as well. An applications processor based on conventional package-on-package (PoP) technology may run $28 each. If the same device was configured with a Wide I/O scheme, it could cost about $50, according to some experts. The cost of the substrate, coupled with the TSV production process, “eliminates the product margins for consumer applications,” said Pol Marchal, director of R&D at IMEC’s India unit. In fact, the TSV creation process is 40% or more of the total cost for a 3D device, Marchal said.

Applied’s Kumar disagreed, saying that the industry has reduced the cost for the TSV creation process. Many blame high 3D chip costs on the temporary bonding/debonding, test and other process steps.

There are a number of process steps to make a 3D chip. In the via creation process alone, there are five main manufacturing steps: etch, chemical-vapor deposition (CVD), physical-vapor deposition (PVD), electroplating, and chemical mechanical polishing (CMP).

Two years ago, the overall manufacturing cost-of-ownership (COO) for making a 5μ x 50μ TSV was about $150, Kumar said. Today, the COO is about $50, he said. “I think it will continue to drop,” he added.

Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries, recently summarized the situation. “There are many issues we need to work through, such as how do you handle thin wafers once they are shipped, how do you test them and ensure known good dies,” he said. “If those wafers are packaged, that’s not a problem. If they’re not, how do you ensure the known good die? Also, with memory, the key integration is logic plus memory. In that case, the co-design of different die comes into the picture.”

By Mark LaPedus
In total, silicon foundry capital spending is expected to reach about $21 billion in 2012, flat from 2011, according to Barclays Capital. In 2013, foundry CapEx is expected to fall 1% to 20.9 billion, according to the firm. TSMC will see its CapEx jump from $8 billion in 2012 to $9 billion in 2013, but Samsung LSI’s CapEx will fall from 8 trillion won in 2012 to 6 trillion won in 2013, according to the firm. “We model GlobalFoundries CapEx inching up slightly to $3.7 billion in 2013 from $3.4 billion in 2012, and UMC CapEx moving slightly higher to $2 billion in 2013 from $1.8 billion in 2012,” said C.J. Muse, an analyst with Barclays. Muse also predicts total CapEx will fall about 5% in 2012, compared to flat in the previous forecast. He lowered his overall CapEx outlook for 2013 to minus 10%, compared to flat to minus 5% in the previous forecast.

TSMC has taped out the foundry segment’s first 3D chip test vehicle using JEDEC’s Wide I/O mobile DRAM interface. TSMC’s partners in the effort include Wide I/O DRAM from SK Hynix, DRAM IP from Cadence, and EDA tools from Cadence and Mentor Graphics.

GlobalFoundries announced a partnership with Masdar Institute to help spur the continued development of Abu Dhabi as a center for semiconductor R&D and manufacturing.

Soitec and Shin-Etsu Handotai have agreed on an SOI licensing extension.

Chinese SOI supplier Shenyang Silicon Technology (SST) has emerged. SST has installed EV Group’s 300-mm, low-temperature automated production bonding system for SOI materials. The China-U.S. joint-venture SOI wafer provider has selected the 300mm bonder as a follow-on to its prior purchase of a 200mm tool from EV Group. The system already has shipped to SST’s facility, marking the first installation in China of a 300mm SOI wafer production tool.

Ericsson and STMicroelectronics currently are working with an external adviser to ensure the best possible future for ST-Ericsson. ST-Ericsson, a 50-50 joint venture between Ericsson and STMicroelectronics, is developing cell-phone chips based on SOI.

According to Strategy Analytics, Qualcomm led the smartphone applications processor market in the first half of 2012. Samsung, MediaTek, Broadcom and TI took the rest of the top-five spots. ST-Ericsson continued its recovery and showed 28% sequential growth in Q2.

SEMI released its annual silicon shipment forecast for the semiconductor industry

The LED industry has added roughly 100 new fabs in the last five years, for a total of 169 fabs worldwide, according to SEMI.

China will spend 250 billion yuan, or about $40 billion, and expects a half million people will be employed in the solar industry by 2015. Additionally, the plan sets a target of 50GW installed capacity by 2020, according to SEMI.

Soitec has completed delivery on a total of 5 megawatts (MW) of its concentrating photovoltaic (CPV) systems to seven solar power plants throughout Italy.

NPD Solarbuzz forecasts that polysilicon production will be greater than solar industry requires in 2012.

ARM has tipped its strategy to crack the server market.

Calxeda, which is developing ARM-based chips for servers, announced $55 million in additional funding.

Following the adoption of a new networking standard, suppliers of embedded computer systems based on AdvancedTCA technology are looking to expand their efforts into new and traditional markets.

Here’s the latest from the Cowan LRA Model: “According to the WSTS’ August actual global semi sales of $23.013 billion, the updated monthly forecast expectation for full year 2012’s total global semi sales is expected to be $294.6 billion. This latest update to the 2012 sales forecast estimate corresponds to a year-over-year sales growth expectation of minus 1.7%, which dropped from the previous month’s year-over-year sales growth forecast estimate of minus 0.5%. 2013′s full year forecasted sales growth expectations is (plus) 7.4%.”

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of marketing for advanced packaging and nanotechnology at Ultratech. What follows are excerpts of that conversation.

SMD: What are the main problems looming in 3D-IC from a manufacturing and design standpoint?
Ranjan: On the demand side there’s been a lot of talk, but customers have not committed to this yet. The reason is there are some supply chain issues with regard to who does what—who supplies memory, who supplies logic, who integrates everything, who’s responsible for yield, who does microbumping and who does test. That’s a big problem to solve. There are also problems on the tools side with respect to thermal management when you are putting logic plus memory together. There are no good 3D tools out there that can help you look through these issues. If you’re just doing memory plus memory integration it’s easier, but if you’re doing mixed-device convergence that’s a big problem.
Smith: From what I’ve seen, all of the partners in the ecosystem are doing their part to prepare for true 3D-IC—stacking die one on top of another. The foundries are preparing the manufacturing. The equipment guys have already got their equipment out there and it’s being installed in the fabs today. A lot of people point fingers to EDA because we don’t innovate in the usual way. What we’re really doing is automating existing processes. We’re waiting for the demand side to pick up. When we look at the real companies doing 3D-IC, there are very few doing active designs. Most is early research and prototyping, testing the manufacturing process, testing the reliability of the stacking mechanisms, looking at the electrical characteristics, and so on. We have done quite a lot of work in providing the basic toolkit that’s necessary for any design company to start that work. Most of the companies today are working on silicon interposer technologies, which is an intermediate point. The other thing a lot of people complain about is standards. Those typically come either from proprietary formats or languages that become popular, such as SystemVerilog. It’s a little premature to look at EDA interface standards for 3D-IC because there isn’t enough experience. The things being done today are fairly simplistic, anyway, so they won’t be applicable to a wide variety of customers.

SMD: How about the thermal tools?
Smith: From a technical standpoint, thermal is an issue. The analysis tools are too low in capacity or not high enough in capacity. But from an EDA standpoint there also isn’t enough business there to warrant an all-out attack with new tools. But I don’t see any major technical challenges.
Matthias: The future is very bright in terms of 3D IC. The train is moving and it’s accelerating. About five to seven years ago there were a lot of questions about how you manufacture a 3D stack. There was a question about how do unit processes interact with each other. At this point, there are no unsolved issues in manufacturing. There are baseline processes that work. We’re now in the phase where we’re really trying to make the manufacturing smarter. We started with the idea of doing one chip at a time, then think about how to stack them. Now we’re thinking it’s better to stack them first, then do the processing on the first layer and then the second layer, and then do a compression bond on top of that and do the bumping later on. There is a move to get into more intelligent manufacturing integration schemes. There’s confidence in the industry that we can actually manufacture 3D-ICs. Five years ago, it was only the MEMS companies, which are obscure. Today everyone knows you can get a yielding device. Now it’s a question of whether this is the best approach for a product. Progress is accelerating, though.
Patel: I totally agree. The unit processes are in place. The key is maturity now. We all need to work through the supply chain. We need to do the front end and hand it off to the OSATs, who are experts in handling the wafer thinning and backside processing. What we are doing today is working through many wrinkles and pushing through the lots, working through the supply chain to gain maturity and get higher yield. For volume manufacturing you need to define the design parameters and design processing windows.

SMD: Have we gotten beyond the test chips?
Patel: We are still in a test-chip phase. We do have some initial product tests, but there are many issues we need to work through such as how do you handle thin wafers once they are shipped, how do you test them and ensure known good dies, and how do you ship memory wafers. If those wafers are packaged, that’s not a problem. If they’re not, how do you ensure the known good die? Also, with memory, the key integration is logic plus memory. In that case, the co-design of different die comes into the picture. Also, do you adopt for the 3D memory standard Wide I/O 1, Wide I/O 2, and in 2.5D do you use Wide I/O memory or high bandwidth memory? Those are things we need to fold into manufacturing, along with robustness. We need to work through the entire supply chain—memory, EDA and design IP. The unit processes of filling the vias, backside thinning—each piece has been individually perfected. Now the time comes to put it into practice and make it a robust practice.
Pateras: When it comes to test, there are a number of different areas. Clearly 2.5D is being used a lot. We’re seeing a lot of need for testing memory stacks with an interposer on an SoC. It’s not quite mainstream. We’re seeing some customers moving to vertical stacks on an SoC this year. The testing problem there is well understood. The JEDEC standard is well defined, whether it’s Wide I/O 1 or 2. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BiST. We’re seeing this implemented by many different customers. There’s less of a need for standardization there because you’re generally just testing a memory bus. The bigger challenge is with stacked logic die. We have not yet seen that. There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With memory it’s easier, because there’s a robust testing methodology for bare memory die. With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question. And if you stack them together, you may have a yield issue.

SMD: How about when we actually stack the die together in a 3D-IC?
Pateras: That’s an even bigger problem. How do you access them in the stack? You can’t access those I/Os from the outside. You need to go through TSVs, so you need a way of being able to access those die. And if they’re heterogeneous, you really need some kind of standardization. There are some existing test standards, but these are not good enough for a vertical stack. This is still not solved. There are some proprietary solutions. IMEC has developed one. We have developed one. But if you want to bring parts together from different sources, you need standardization. The 1838 working group is addressing that, but progress is slow. Once the standard is in place, then the problem is much more tractable. Right now it’s divide and conquer. The stress of the TSVs may result in changes in timing characteristics of the transistors around the TSVs.

SMD: Is the business case for stacking compelling yet? For a long time everyone was saying stacking is too expensive, but 20nm or 14nm chips are expensive, too.
Ranjan: It’s a cost-to-performance issue. It depends on what products you’re manufacturing and what the lifecycle is. I don’t believe the costs have been well characterized yet. If you’re running 22nm, it becomes very complex very quickly—what kind of wafers, what kind of yield, what kind of utilization. How do you do apples-to-apples comparisons with TSVs? In general, going down Moore’s Law is very expensive, so companies will take a look at alternative solutions. Packaging may enable this cost-performance tradeoff. At what point does it become attractive? That isn’t well understood right now, especially for TSVs. With 2.5D, we see a lot of traction at 28nm. Companies are in production today, although in limited quantities. A lot of other device companies are lining up at foundries for 2.5D solutions. But with 3D, we don’t see that yet. My personal opinion is that real 3D won’t happen in any sort of meaningful volume until 14nm.
Smith: This is all based on ROI and economics, but we’re seeing some companies moving to stacking where they have control overall the aspects of the integration. If you have the economics figured out, you still have the ecosystem issue. The supply chain is not mature yet. We do see IDMs that have the manufacturing moving forward, though.

By Ed Sperling

Future memory technology inside of mobile devices will use less power and run faster at each rev of Moore’s Law, but that technology also will look different, use different materials, and will be manufactured with different equipment, processes and technologies.

While this technology will owe its heritage to research and testing of the past few decades, the differences are expected to be dramatic. A panel of vendors, their customers and researchers took a deep dive into the research that will change the memory market of the future at an IEEE International Memory Workshop held Monday in Monterey, Calif. The discussion, chaired by Raman Achutharaman, VP of strategy and marketing for Applied Materials’ silicon systems’ group, pointed to some interesting research, developments and future standards.

What’s next?
Laith Altimime, Imec’s program director for CMOS process technology, said that over the next decade memory makers will require new materials (graphene and/or carbon nanotubes, for example); new techniques, including EUV lithography, air gap insulation and 3D stacking with through-silicon vias; and new structures, including hybrid tunneling field effect transistors (TFETs), VFETs and TANOS cells.

“New materials and device architectures are the key,” said Altimime, noting that 3D stacking will “take over everything in its path.” That includes resistive RAM (RRAM), a non-volatile type of memory now in the research phase that relies on current applied to a filament; 1T-RAM, a higher-density version of RAM; and spin-transfer torque RAM, which changes the magnetization on a thin magnetic layer by running a spin-polarized current across it.

Altimime noted that scaling beyond 16nm most likely will require 3D cell architectures. He said the base material will still be CMOS, but it also will include higher-k dielectrics, metals, and stack engineering.

Fig. 1: Air gap insulation. Source: Applied Materials

NAND changes
Sung-Kye Park, of Hynix’s Memory R&D Division, noted that NAND will require a slew of changes to decrease charge loss and increase e-field retention. Those changes will include everything from air gap technology to an increased doping of the control gate. He expects new structures and new materials to start hitting the market within two years.

“3D flash is a possible candidate,” Park said, pointing to Toshiba’s pipe-shaped Bit Cost Scalable technology, Samsung’s Terabit Cell Array Transistor (TCAT), Hynix’s 3D-FG and hybrid chips. But he noted there also are potential hurdles in areas such as process integration, particularly in the areas of multistack deposition and word-line formation.

Fig. 2: 3D NAND architectures. Source: Applied Materials

DRAM shift
Joo Young Lee, strategic planning manager at Samsung, said the goal for DRAM is still a 35% cost reduction each year, but to achieve that will require moving to the next process nodes. DRAM is currently approaching 30nm, he said. He expects it to hit 25nm by 2015 and 14nm by 2020, with DDR4 hitting mainstream in 2013. EUV will be required at 14nm, he said.

Reaching those advanced nodes will require changes in some of DRAM’s basic structures—cell capacitors, cell array transistors and cell node contacts, all of which will need to be re-engineered.

Patterning issues
Yoshitaka Tsunashima, a leading researcher at Toshiba, said his company’s NAND technology already requires double patterning. At 14nm, double patterning and EUV both will be required.

EUV has its own issues, of course—light source performance, mask defect control, optical performance, mask data preparation, and resist performance. But he noted that 11 companies are now working to solve those issues as part of the EUV Infrastructure Development Engineering Center (EIDEC).

“The other way we can get there is 3D NAND,” he said, noting that either approach—lithography or stacking—or both will help reduce bit costs. He said that technology also can be extended to RRAM, organic memory and MEMS memory.

Customer view
Nokia’s Matti Floman said the ideal solution would be universal memory. But given that is an unlikely development, what’s needed from his company’s standpoint are higher bandwidth for DRAM and non-volatile memory, new package solutions, lower power consumption, higher temperature tolerance, pre-developed scalable modules, and standard solutions.

He noted that Wide I/O is seen as a strong candidate for replacing DDR2 and DDR3 in high-end products. Mass memory, meanwhile, is moving toward NAND and embedded MultiMediaCard (eMMC).