Posts Tagged ‘wafer-level packaging’
Mentor Graphics Corporation (NASDAQ: MENT) today announced a design, layout, and verification solution to support design applications for TSMC’s Integrated Fan-Out (InFO) wafer-level packaging technology. The solution comprises the Calibre® nmDRC physical verification product, the Calibre RVE™ results viewing platform, and the Xpedition® Package Integrator flow. It enables mutual customers to deploy the unique fan-out layer structures and interconnects in the TSMC InFO technology, targeting cost-sensitive applications such as mobile and consumer products.
The interplay between today’s advanced system-on-chip (SoC) technologies and packaging requirements is driving the need for co-validation between integrated circuit (IC) and package design environments. The Xpedition Package Integrator flow will be Mentor’s platform to support TSMC’s unique TSMC InFO design requirements, including integration with other Mentor solutions—the first being Calibre nmDRC and Calibre RVE.
The Mentor® solution allows IC and package designers to view and cross-probe results from the Calibre nmDRC tool directly inside the Xpedition Package Integrator flow for verification of TSMC InFO interconnect structures. Because this flow is based on proven integration via the Calibre RVE tool, it results in automated sign-off verification and easier correction of any issues highlighted by the Calibre nmDRC product. It also streamlines the addition of future features and capabilities.
IC designers have widely adopted the Calibre nmDRC tool as their sign-off solution for multiple process node generations. Through the integration with Xpedition Package Integrator, they now share a common view with package developers when performing co-verification.
“We are focused on making our solutions easier for customers to adopt by providing a design methodology that leverages proven EDA design tools,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Mentor and TSMC have established this InFO methodology through an integration of the Calibre and Xpedition platforms, and will continue to collaborate on enhancing that solution.”
“Integrating Calibre nmDRC technology with the Xpedition Package Integrator flow is a solid first step in Mentor’s support of TSMC’s InFO technology,” stated Joe Sawicki, vice president and general manager of Mentor Graphics Design to Silicon Division. “We continue to work with TSMC and its ecosystem to expand beyond this initial step by establishing a roadmap for additional capabilities to further accelerate time-to-market for users of TSMC’s InFO offering.”
By Jeff Dorsch, Contributing Editor
“There’s a lot of interest and a lot of excitement about fan-out wafer-level packaging,” the director of marketing for Mentor’s Calibre DRC product line said, presenting “opportunities and challenges.”
The process of “bringing IC design and package design close together” presents many questions, Ferguson observed. Package design software usually runs on Windows, while EDA tools are on Linux, he noted. “It’s not so easy to mix and match them,” he said.
What manufacturing output to employ? GDSII, Gerber, or OBD++?
“Not all these things have answers yet,” Ferguson acknowledged. “The pieces are not all there yet. We’re partnering with several companies.”
Ferguson touted Mentor’s Xpedition Package Integrator suite for dealing with fan-out wafer-level packaging design. “It brings you across all the domains,” he said. The Mentor software will enable designers to “visualize it and optimize it,” he added.
The conference also heard from executives of three semiconductor equipment companies.
Markus Wimplinger, corporate technology development and intellectual property director at EV Group, spoke about temporary and permanent bonding in chip packaging, comparing chip-to-chip, chip-to-wafer, and wafer-to-wafer bonding.
Chip-to-chip and chip-to-wafer “are more flexible,” while wafer-to-wafer “has great promise,” he said.
David Butler, vice president of product management and marketing at SPTS Technologies, may have taken the prize for longest presentation title with “More Die, Stronger Die. Smaller, Thinner Packages Drives Die Singulation by Plasma Etch.”
“Saws damage die,” he said. “Plasma dicing is better.”
SPTS partnered with DISCO to develop effective die singulation through plasma dicing, according to Butler. “Plasma dicing provides about two times [improvement] in die strength for small die, thin die,” he said.
Rajiv Roy, vice president of business development and director of marketing for Rudolph Technologies, spoke about lithography and inspection requirements for fan-out wafer-level packaging, while touting the company’s experience in those areas.
Wafer and panel warpage can be a concern in FO-WLP manufacturing, he noted. “JetStep successfully measured and corrected for die placement errors,” Roy said, referring to Rudolph’s JetStep Advanced Packaging Lithography Systems, which can accommodate round or square/rectangular substrates.
By Jeff Dorsch, Contributing Editor
On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.
The day began with Pioneer Awards presented to Mitsumasa Koyanagi of Tohoku University and Peter Ramm of Fraunhofer EMFT. Those two men then gave talks on their involvement in 3D packaging technology over the decades.
“It started with DRAM in 1974,” Koyanagi recalled.
Ramm reviewed various European initiatives in the field, including the development of InterChip Vias (ICVs), a precursor to through-silicon via (TSV) technology, and the concept of known good die.
Suresh Ramalingam of Xilinx discussed the attributes of Silicon-less Interconnect Technology (SLIT), which the chip company developed in cooperation with Siliconware Precision Industries (SPIL), the IC assembly, bumping, and testing contractor.
“It’s still a silicon platform,” he pointed out. SLIT promises to connect multiple die in a package without resorting to TSVs. “Wafer warpage is a big issue,” Ramalingam noted.
Amkor’s Mike Kelly followed Ramalingam. “There’s a kind of upturn or resurgence in 2.5D, driven by high-bandwidth memory,” he said.
Amkor is offering the Silicon-less Interposer Module (SLIM) as its TSV alternative technology, according to Kelly, while also providing Silicon Wafer Integrated Fan-out Technology (SWIFT) as another packaging alternative to TSV-based interconnections.
KC Yee of TSMC, filling in for an absent presenter, spoke at length about the foundry’s Integrated Fan-Out (InFO) wafer-level packaging technology. “InFO eliminates silicon, TSVs, interposers,” he said. At the same time, InFO “reduces cost,” he asserted.
DARPA’s Daniel Green spoke about the agency’s Diverse Accessible Heterogeneous Integration (DAHI) program, which succeeded its Compound Semiconductor Materials on Silicon (COSMOS) program.
He was followed by Augusto Gutierrez-Aitken of Northrop Grumman Aerospace Systems. “DAHI is not in competition with CMOS,” he said. NGAS is developing a foundry for heterogeneous integration projects, inviting in companies and universities to participate in the research and development.
Teledyne Scientific’s Miguel Urteaga spoke about his company’s CS-STACK 3D stacking chip program. “We’re looking to get the highest III-V performance we can,” he said.
By Jeff Dorsch, Contributing Editor
The element in the platinum group, atomic number 44 on the periodic table, could one day succeed copper in the advanced interconnects of chips, according to Christoph Adelmann of imec and other speakers at SEMI’s annual Strategic Materials Conference, held Tuesday and Wednesday, September 22-23, at the Computer History Museum in Mountain View, Calif.
In the same session, Adelmann was followed by Patrick Martin of Applied Materials and Greg Herdt of Micron Technology, with the latter taking “Copper Interconnect Scaling Challenges and Strategies” as his theme.
The overall theme for the conference was “Materials for a Smart and Interconnected World.” It featured sessions on “Material Enabling Silicon Everywhere” (read: the Internet of Things), “New Emerging Materials Technology & Opportunities at the Edge,” sustainable manufacturing, and a panel of executives from semiconductor manufacturers providing “A View from the Fabs.”
The attendees also heard from a number of speakers on economic and market trends.
Mark Thirsk of Linx Consulting said that among the top 50 chemical companies in the world, some are considering whether they want to remain suppliers to the semiconductor industry. In merger-and-acquisition activity, “there are no holy cows,” he observed.
While Europe, Japan, and the United States have traditionally dominated the semiconductor materials market, South Korea and Taiwan are taking higher profiles in the business. “China is coming,” Thirsk said, noting the multibillion-dollar initiative by China’s government to bolster its domestic semiconductor industry.
For all the talk about next-generation materials, there is “record silicon use” at present, with growth in 200-millimeter wafers, largely driven by demand for Internet of Things devices, he said.
Shawn DuBravac, chief economist and senior director of research for the Consumer Electronics Association, presented an economic perspective on China and the U.S. economy. “Anything under 7 percent growth in China is a recession,” he said. “A China recession is a global recession.”
He also discussed the leading consumer product categories of smartphones, tablet computers, televisions and displays, laptops, and desktop computers. “Tablets are maturing and are in decline,” DuBravac said.
Dan Tracy of SEMI reviewed developments in the IC packaging market. The packaging materials market is worth around $21 billion a year and represents 45 percent to 50 percent of all semiconductor materials, he noted.
While the large outsourced assembly and test contractors continue to dominate IC assembly and testing services, there are signs that Celestica, Flextronics, and other contract electronics manufacturers are pressing into the chip packaging field to complement their production of printed circuit boards, according to Tracy.
Wafer-level packages are becoming more prominent. The average smartphone has more than 25 wafer-level packages, Tracy said.
Lita Shon-Roy of Techcet said the “growth areas” in semiconductor materials are 3DICs, 10nm, and 7nm.
Gases represent a $3.7 billion annual market, Shon-Roy said, and she detailed the supply situation involving neon gas, which is used in excimer lasers for lithography. Prices for neon gas have risen five to 10 times, she noted, and the situation likely won’t settle down until the end of this year or early 2016, at best.
Rich Ray of Honeywell Electronic Materials spoke about “silicon everywhere” and the Internet of Things, a very popular topic at industry conferences this year. “It’s not in the things,” he said. “It’s the cloud, the big data.”
Ray said, “How do you manage all that data? When the insights come out, how do you store that? Access the cloud.” Big-data analytics are key to obtaining those IoT insights, he added.
Other speakers addressed developments in atomic-level processing and new materials, such as hafnium dioxide and yes, ruthenium.
“We are in a situation that is unprecedented in the industry,” said Ralph Dammel of EMD Performance Materials. “The breakdown of Moore’s Law is always around the corner.” The cost issue is consuming the semiconductor industry, he added.
The semiconductor industry is always changing and always moving on. SEMI’s Chemical and Gases Manufacturers Group will continue to address these and other issues for the next year, leading up to the 2016 Strategic Materials Conference.
By Ed Korczynski, Sr. Technical Editor, SST/SemiMD
Through-Silicon Vias (TSV) have finally reached mainstream commercial use for 3D ICs, though still for “high-end” high-performance applications. Despite allowing for extreme miniaturization, the demand for TSV has little to do with package size as evidenced by recent Samsung and TSMC product announcements for “enterprise servers” and “routers and other networking equipment.”
Used to connect opposite sides of a silicon substrate to allow for stacking of multiple Integrated Circuit (IC) chips in a single functional package, the industry has been using TSV in Micro-Electro-Mechanical Systems (MEMS) and Backside Image Sensors (BSI) manufacturing for many years now. Also, the first announcement of a commercial FPGA product using TSV in a so-called “2.5D” interposer package happened four years ago.
However, the Figure above shows that CIS and MEMS and 2.5D-FPGAs can all be categorized as “niche” applications with limited growth potentials. Specialty memory and logic (and eventually photonics) applications have long been seen as the major drivers of future TSV demand.
On September 25 of this year, TSMC announced it has collaborated with HiSilicon Technologies Co, Ltd. to create an ARM-based networking processor that integrates a 16nm-node logic chips with a 28nm-node I/O chip using silicon interposer technology. This is the same 2.5D TSMC-branded Chip-on-Wafer-on-Substrate (CoWoS) technology used in the Xilinx FPGA product. “This networking processor’s performance increases by three fold compared with its previous generation,” said HiSilicon President Teresa He. Package size reduction has nothing to do with the value of the products now demanding TSV.
Samsung announced last August that it has started mass producing the industry’s first 64GB DDR4 registered dual Inline memory modules (RDIMMs) using TSV. Targeting enterprise servers and “cloud” data centers, the new RDIMMs include 36 DDR4 packages, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dice. The low-power chips are manufactured using Samsung’s 20nm-node process. The company claims that the new 64GB TSV module performs twice as fast as a 64GB module that uses wire-bonding, while consuming about half the power. Samsung has invested in TSV R&D since 2010 for 40nm-node 8GB DRAM RDIMMs and 2011 for 30nm-node 32GB DRAM RDIMMs.
The Hybrid Memory Cube (HMC) and other heterogeneous 3D-IC stacks based on TSV should be seen as long-term strategic technologies. HMC R&D led by Micron continues to serve near-term customers demanding ultra-high performance such as supercomputers and performance networking, as detailed in an SST article from last year. Micron’s Scott Graham, General Manager, Hybrid Memory Cube, commented then, “As we move forward in time, we’ll see technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this technology being for mainstream memory.”
Elusive Demand for Mobile Applications
14 years ago, this editor—while working for an early innovator in TSV technology—was co-author of a “3D stacked wafer-level packaging” feature article in SST.
The lead paragraph of that article summarizes the advantages of using TSV to reduce package sizes:
As electronics applications shrink in size, integrated circuit (IC) packaged devices must be reduced both in footprint and in thickness. The main motivation for the development of smaller packages is the demand for portable communications devices, such as memory cards, smart cards, cellular telephones, and portable computing and gaming devices. End-users of such electronic devices are interested in greater functionality per unit volume, not relatively simplistic metrics, such as transistors per chip or circuit speed.
While still true, established and inherently lower-cost packaging technologies have been extended to allow for stacking of thinned silicon chips: wire-bonding can connect dozens of layers to a substrate, flip-chip with wire-bonding and substrate-vias can connect 4 layers easily, and both fan-in and fan-out packages can provide ample electrical Input/Output (I/O) connections. At SEMICON West this year in the annual Yield Forum breakfast sponsored by Entegris, Qualcomm vice president Dr. Geoffry Yu reminded attendees that, “TSV eventually will come, but the million dollar question is when. The market forces will dictate the answer.” What has become clear in the last year is that market demand for improved product performance will set the pace.
Ed Korczynski, Senior Technical Editor, Solid State Technology/SemiMD
The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world. Integration of heterogeneous circuit functions—such as micro- and graphics-processing, field-programmable gate array (FPGA) logic, dynamic and static memory, radio-frequency (RF) and analog, and sensing and actuating—may also be needed at the package-level to be able to deliver complete systems (Figure 1).
In particular, electronic systems for high-growth mobile applications require low-power and low-volume per element which dis-allows circuit integration at the printed-circuit board (PCB) level. Instead, heterogeneous integration must occur as either a system-in-package (SIP) or a system on-chip (SOC). Dr. Eric Mounier of Yole Développement, presented at the recent European 3D TSV Summit 2014 held in Grenoble, and showed Yole forecasts that total world-wide semiconductor IC wafers packaged at the wafer-scale will be 19% this year, raising to 20% in 2015.
One way of looking at the history of the IC industry is to examine the dynamic between SIP and SOC approaches. New functionalities tend to be first integrated into hardware as dedicated additional chips, to be connected in to the rest of the system as part of a PCB or SIP. Since different functionalities often require different fab processes, it is generally less expensive at the chip-level to divide functionalities into different chips, but then the packaging costs tend to be higher. Relatively low-volume parts may be most economically delivered as SIP, while higher-volume parts can often justify the additional design and test expenses of delivering the same functionality as a single SOC.
The other major reason to go with an SIP is to improve the yield of large area chips at the leading edge of fab processing. Since defects/area tend to be relatively high with a new fab process, very large chip designs will have relatively low yield at first but then will improve as the fab learns how to reduce both random and systematic yield limiters. The recent excellent example of this trend is the Xilinx Vertex-7 FPGA which splits the chip into four sub-chips and then uses a silicon interposer for SIP re-integration. We may expect that a next-generation of the product would be build in a single SOC after the yield improves, at which point Xilinx would be expected to extend the product line with additional functionality added in using multi-chip SIP.
Steffen Kroehnert, director of technology for Nanium S.A., gave a recent presentation at SEMICON/Singapore 2014 entitled “Wafer Level Fan-Out as Fine-Pitch Interposer.” Fan-In WLP uses layout package connections within the chip area, and when the scale and count of on-chip bond pads does not match with standard packaging scales, a Re-Distribution Layer (RDL) of metal interconnect can be used to Fan-In to ball-grid or pillar-grid arrays (BGA/PGA) within the chip-area. However, when the needed number of connections cannot be made within the chip area, packaging filler materials can be used to provide physical area adjacent to an original chip such that package connections can be arranged to Fan-Out WLP solutions use “Fan-Out” out from the chip center when seen from above.
Chip-Package-Board simultaneous co-design and co-development are becoming import instead of serial work according to Kroehnert. The penalty for re-design costs and losing strategic time-to-market for a new SiP is too high for allow for iterative R&D, such that products must be co-designed properly the first time.
FO-WLP Leveraging PV Fab Tricks
Deca Technologies, the electronic interconnect solutions provider to the semiconductor industry owned by Cypress Semiconductor, recently announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca’s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.
Leveraging volume production technologies from leading silicon PV manufacturer SunPower Corp., Deca quickly achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using conventional approaches to WLCSP manufacturing. Deca claims that other FO-WLP technologies suffer from inherent manufacturing and reliability issues due to discontinuity at the silicon:mold-compound interface, which are avoided by the company’s use of copper-pillars and an over-mold approach (Figure 2).
Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio, and power management components for mobile markets. Demand fluctuations in these markets can lead to challenges in managing inventories. “Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain.”
“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”
FO-WLP for the future
As thoroughly covered in our sister blog Insights From The Leading Edge, STATSChipPAC (SCP) recently announced FlexLine™ FO-WLP. The FlexLine flow dices and reconstitutes incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size. The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process (Figure 3). Single and multi die fan-out package solutions have been in high-volume manufacturing since 2009 with more than a half-billion units shipped.
Earlier this month, Digitimes provided a brief English translation of some Chinese-language Economic Daily News (EDN) saying that Taiwan Semiconductor Manufacturing Company (TSMC) plans to increase IC packaging revenues to US$1 billion in 2015 and to US$2 billion in 2016. TSMC co-CEO CC Wei reportedly acknowledged that the production cost for silicon-substrate SIP (TSMC’s variant termed “chip-on-wafer-on-substrate” or “CoWoS”) packages is relatively high, and so the world’s leading IC foundry intends to invest in FO-WLP technologies to be able to offer advanced packaging at a reduced price.
Wafer-level packaging continues to gain slow IC market share, and novel fan-out redistribution drives the need for improvements in existing packaging materials within tight cost and reliability constraints. With silicon-interposers and copper-interconnects part of WLP technology, the lines between chip and package have never been less clear. Managing all of this complexity is business as usual when designing mobile systems of the future.
Karen Savala of SEMI notes that the semiconductor industry is uncharted waters without the benefit of a GPS system. She says mega-mergers, massive supply chain investments by manufacturers and governments, new consortia and collaboration models are changing the rules for everyone in the ecosystem. Pervasive Computing, the theme of this blog post, is also the theme for the upcoming Industry Strategy Symposium (ISS), to be held January 12-14, 2014 in Half Moon Bay, California.
In Karen Lightman’s MEMS Industry Group blog, she turns the reins over to Silex Microsystem’s Peter Himes, vice president marketing & strategic alliances. Peter reflects on MEMS and while other might lament at the conundrum of the uniqueness of all MEMS process, Peter instead sees opportunity. In this example he describes Silex’s partnership with A.M. Fitzgerald and Associates and their Rocket MEMS program.
Phil Garrou covers several topics related to 3D integration in this week’s blog: A new report from Yole on flip chip (FC) technology, ASE’s report ASE – Board Level Reliability of Bump on Polymer (BoP) WLCSPs, and chip embedding at IMS.
Should the lifetime of EUV optics be a concern? Upon hearing about how EUV sources contaminate the optics inside the tool, Pete Singer blogs that there still must be lots of questions about the ultimate cost of ownership and how that will compare to double and triple patterning approaches with 193nm immersion.
Are we using Moore’s name in vain? That question is posed by Zvi Or-Bach, President & CEO of MonolithIC 3D in his blog post, where he notes that dimensional scaling was not an integral part of Moore’s assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore, he writes.
The Solid State Technology 2014 Editorial Calendar is out, blogs Pete Singer, noting the editorial mission remains that same: we’re dedicated to covering mainstream semiconductor manufacturing technology, with a strong focus on transistors, interconnects and packaging. We also cover other types of advanced electronics, including MEMs, LEDs, displays, bioelectronics, photonics and power electronics.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.