By David Lammers

Water is proving increasingly useful to the semiconductor industry. Just as immersion techniques came to the rescue of lithographers, ice could prove beneficial in removing small particles from wafers, speakers from Dai Nippon Screen (DNS) said at the Sematech Surface Preparation and Clean Conference (SPCC 2012) in Austin.

Ice is effective at dislodging small particles. (Source: DNS presentation at SPCC 2012)

Researchers at the central research laboratory of DNS (Kyoto, Japan) hypothesized that the expansive force which occurs when water freezes could nudge small particles stuck to a wafer’s surface. Water expands in volume by about 10 percent when it freezes, said Jim Snow, a chemist based at the DNS office in Dallas.

Early tests have shown that when water becomes ice it lifts particles adhering to a wafer surface. If water is frozen in a convex manner, i.e., from the inner part of the wafer out to the edge, there is no damage to the wafer. After the water is frozen with liquid nitrogen at minus 190° C, it is unfrozen with 80° C water. The result, said DNS CTO Soichi Nadahara, is an 80 percent particle removal efficiency (PRE), better than the company’s current state-of-the-art techniques.

While DNS has tested the ice cleaning method with 37nm poly lines and spaces, the test patterns were not very dense. “We believe this technique could be useful beyond 28nm and 20nm,” Snow said, adding that it is “a work in progress.”

Nadahara said “we are close to the beta or prototyping tool stage, and we will put it to the test somewhere at a customer site. We have been working on it internally for a couple of years.” The motivation, he said, is that ice seems more effective than other techniques at dislodging extremely small particles, with less damage than spray aerosols or megasonic techniques.

Cryogenic techniques have been used in wafer cleaning tools for some time. BOC earlier introduced its Eco Snow cleaning method, hitting the wafer with ice particles while rotating the wafer at different speeds.

FSI, for example, projects frozen nitrogen and argon at wafers at high velocity, with no side effects, said Jeff Butterbaugh, CTO at FSI International (Chaska, Minn.) DNS has used a two-fluid spray technique — most often nitrogen (N2) combined with water or SC1 chemistry for a 30 second period — using a tangential force in its Nanospray 2 product.

But as far as anyone could recall at the SPCC conference, the idea of freezing a wafer has not been tried before. Participants at the conference said many questions remain to be answered, including the impact on throughput, damage to sensitive structures, and the like.

One large wafer foundry is working with DNS on the tool, and participants at the conference that that foundry is most likely TSMC, which has pioneered single-wafer cleaning before. While working with SEZ (now part of Lam Research), TSMC engineers figured out that back end of the line (BEOL) cleaning with the ST250 chemistry at lower viscosity worked better in single-wafer chambers than in batch processing tools. TSMC’s move jump-started the move to single-wafer cleaning, and the major clean tool companies now offer tools with eight to 20 chambers.

Texas Instruments, which worked closely with TSMC and other foundries, had visibility into TSMC’s success with single-wafer cleaning, and began incorporating single-wafer cleaning tools into its DMOS 6 fab in Dallas at the 65nm generation, a participant at the SPCC conference said. Since then, single-wafer techniques have worked their way into the front-end of the line as well.

Nadahara said DNS estimates that single-wafer tools overtook sales of batch tools in 2008, accelerating as high-k/metal gate introduction began to pick up speed.

Ice seems to work better than dual-fluid cleaning techniques for the smallest particles. (Source: DNS presentation at SPCC 2012)

By David Lammers

Wafer cleaning faces tough technical and environmental challenges, particularly as the size of the gate shrinks and post-etch residues must be removed without material loss, said Soichi Nadahara, a vice president at Dai Nippon Screen (DNS) Semiconductor Equipment Company.

In a keynote speech at the recent Sematech Surface Preparation and Cleaning Conference (SPCC), Nadahara said 6-7 percent of wafer front-end equipment (WFE) spending goes for cleaning equipment. With the introduction of high-k dielectrics, more companies are turning to single-wafer cleaning with a lower thermal budget. “Most of the concern is post-etch cleaning of the gate structure. The very small size of the gate requires selective etching, and there are lots of post-etch materials that have to be cleaned.”

NAND memories have increasingly deep structures, and the tall FinFETs present another set of challenges. “Our industry asks for damage-free cleaning, and that is the toughest thing, to limit the material loss,” Nadahara said.

Particles can be detected down to about 25-28 nm, he said, adding that such small particles often have a surface tension which requires a relatively high capillary force to achieve a high particle removal efficiency (PRE).

Drying presents an ecological challenge. DNS is studying systems which avoid isopropanol (IPA) smog by removing 85 percent of the IPA before it is released into the atmosphere.

Other speakers at SPCC described a variety of cleaning challenges, including ways to reduce cross contamination from Front Opening Unified Pods (FOUPs) to wafers.

Thi-Quynh Nguyen, a researcher STMicroelectronics/CEA-Leti, presented a study of cross-contamination between wafers and FOUPs. Airborne molecular contamination (AMC) is able to cause defects by corroding the copper and aluminum interconnects, and causing a polysilicon crystal growth on the metal surfaces.

FOUPs can serve as a reservoir for contamination, the STMicro/Leti group said.

“Contamination can be outgassed from the wafer, and then from the FOUP to the wafer,” she said. Plastic FOUPs and PODs can trap the contaminants, acting as a reservoir, releasing the contaminants to new wafers.

The STMicro/Leti study found that cross contamination is time dependent. HF contamination in the FOUP does not depend primarily on the storage time after cleaning, but on the wafer storage time of wafers after line etching, she said. Etching steps are ionic contaminant sources.

The group studied the sources of contamination, including volatile acids, bases, and organics. They characterized the molecular contaminants in the FOUPs along the various process flows after the wafers were removed, using several different analytical techniques ranging from IMS (Adixenpod Analyser-APA), bubbling and ionic chromatography, and DIW leaching of the FOUP surfaces.

Nguyen said solutions include storing FOUPs in an N2 atmosphere, dry stripping without CF4, and vacuum purge steps.

Srini Raghavan, a professor at the University of Arizona, presented a study by colleagues at the Department of Materials Science and Engineering of cleaning formulations based on deep eutectic solvents (DES), which could replace traditional organic solvents in BEOL cleaning. The group studied residue removal with a variety of formulations, including choline chloride/urea (CC/U) and choline chloride/malonic acid (CC/MA).

DES formulations are low cost, operate at low vapor pressures, have low toxicity, are water soluble, and readily dissolve metal oxides. “The post-etch residue removal rate is slightly lower in DES than in conventional formulations, but DES systems are more environmentally benign,” Raghavan said.

Martin Knotter, representing a group of researchers at the Regional Quality Center of NXP Semiconductors (Nijmegen, Netherlands), described how fluoride contamination on wafers moves to bond pads, leading to corrosion and wire bond quality issues. Because NXP supplies automotive components, it must adhere to higher quality standards and lower PPM failure rates, he said.

The NXP group set out to determine the maximum allowable surface concentration for fluoride. The team used several analytical techniques, including auger electron spectroscopy (AES), as well as liquid phase extraction ion chromatography (LPE-IC) to examine the whole wafer for fluoride content.

“All fluoride on a patterned wafer will migrate to the bond pads,” Knotter concluded, recommending certain cleaning procedures and a first fluoride specification limit of 2.71016 at/cm².