Posts Tagged ‘videos’
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White Papers
The Final Days…Getting to Sign-Off Faster with Calibre
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RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
Automation of Sample Plan Creation For Process Model Calibration
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Extending Copper Interconnect Beyond The 14nm Node
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Events
SPIE Advanced Lithography
San Jose, CAhttp://SPIE.org/ral19sstvw
February 24, 2019 - February 28, 2019
SPIE Photomask Technology + EUV Lithography
Monterey, CAhttp://SPIE.org/rpuv19sstvw
September 15, 2019 - September 19, 2019